mirror of
https://github.com/RIOT-OS/RIOT.git
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239 lines
7.8 KiB
C
239 lines
7.8 KiB
C
/*
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* Copyright (C) 2013 INRIA
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* 2014 Freie Universität Berlin
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* 2016 TriaGnoSys GmbH
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* 2018 Kaspar Schleiser <kaspar@schleiser.de>
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* 2018 OTA keys S.A.
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*
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Implementation of the kernel cpu functions
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*
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* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
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* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Víctor Ariño <victor.arino@zii.aero>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Oleg Artamonov <oleg@unwds.com>
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* @author Francisco Molina <francisco.molina@inria.cl>
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*
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* @}
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*/
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#include "cpu.h"
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#include "stdio_base.h"
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#include "stmclk.h"
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#include "periph_cpu.h"
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#include "periph/init.h"
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#include "periph/gpio.h"
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#include "board.h"
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#if defined (CPU_FAM_STM32L4) || defined (CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32L5)
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#define BIT_APB_PWREN RCC_APB1ENR1_PWREN
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#elif defined (CPU_FAM_STM32G0)
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#define BIT_APB_PWREN RCC_APBENR1_PWREN
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#elif !defined(CPU_FAM_STM32MP1)
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#define BIT_APB_PWREN RCC_APB1ENR_PWREN
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#endif
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
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defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
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defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
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defined(CPU_FAM_STM32L1)
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#define STM32_CPU_MAX_GPIOS (12U)
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#if defined(CPU_FAM_STM32L1)
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#define GPIO_CLK (AHB)
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#define GPIO_CLK_ENR (RCC->AHBENR)
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#define GPIO_CLK_ENR_MASK (0x0000FFFF)
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#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
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#define GPIO_CLK (AHB)
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#define GPIO_CLK_ENR (RCC->AHBENR)
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#define GPIO_CLK_ENR_MASK (0xFFFF0000)
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#elif defined(CPU_FAM_STM32WL)
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#define GPIO_CLK (AHB2)
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#define GPIO_CLK_ENR (RCC->AHB2ENR)
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#define GPIO_CLK_ENR_MASK (0x00000087)
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#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
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defined(CPU_FAM_STM32F7)
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#define GPIO_CLK (AHB1)
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#define GPIO_CLK_ENR (RCC->AHB1ENR)
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#define GPIO_CLK_ENR_MASK (0x0000FFFF)
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#elif defined(CPU_FAM_STM32F1)
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#define GPIO_CLK (APB2)
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#define GPIO_CLK_ENR (RCC->APB2ENR)
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#define GPIO_CLK_ENR_MASK (0x000001FC)
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#endif
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#ifndef DISABLE_JTAG
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#define DISABLE_JTAG 0
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#endif
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/**
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* @brief Initialize gpio to AIN
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*
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* stm32f need to have all there pins initialized to AIN so the consumption
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* of the input Schmitt trigger is saved when running in STOP mode.
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*
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* @see https://comm.eefocus.com/media/download/index/id-1013834
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*/
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static void _gpio_init_ain(void)
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{
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uint32_t ahb_gpio_clocks;
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/* enable GPIO clock and save GPIO clock configuration */
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ahb_gpio_clocks = GPIO_CLK_ENR & GPIO_CLK_ENR_MASK;
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periph_clk_en(GPIO_CLK, GPIO_CLK_ENR_MASK);
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/* switch all GPIOs to AIN mode to minimize power consumption */
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for (uint8_t i = 0; i < STM32_CPU_MAX_GPIOS; i++) {
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GPIO_TypeDef *port;
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port = (GPIO_TypeDef *)(GPIOA_BASE + i*(GPIOB_BASE - GPIOA_BASE));
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if (IS_GPIO_ALL_INSTANCE(port)) {
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if (!DISABLE_JTAG) {
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#if defined(CPU_FAM_STM32F1)
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switch (i) {
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/* preserve JTAG pins on PORTA and PORTB */
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case 0:
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port->CRL = GPIO_CRL_CNF;
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port->CRH = GPIO_CRH_CNF & 0x000FFFFF;
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break;
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case 1:
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port->CRL = GPIO_CRL_CNF & 0xFFF00FFF;
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port->CRH = GPIO_CRH_CNF;
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break;
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default:
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port->CRL = GPIO_CRL_CNF;
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port->CRH = GPIO_CRH_CNF;
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break;
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}
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#else /* ! defined(CPU_FAM_STM32F1) */
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switch (i) {
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/* preserve JTAG pins on PORTA and PORTB */
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case 0:
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port->MODER = 0xABFFFFFF;
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break;
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case 1:
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port->MODER = 0xFFFFFEBF;
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break;
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default:
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port->MODER = 0xFFFFFFFF;
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break;
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}
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#endif /* defined(CPU_FAM_STM32F1) */
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}
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else {
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#if defined(CPU_FAM_STM32F1)
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port->CRL = GPIO_CRL_CNF;
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port->CRH = GPIO_CRH_CNF;
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#else
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port->MODER = 0xFFFFFFFF;
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#endif
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}
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}
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}
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/* restore GPIO clocks */
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periph_clk_en(GPIO_CLK, ahb_gpio_clocks);
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}
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#endif
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/**
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* @brief Initialize HW debug pins for Sub-GHz Radio
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*/
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void _wlx5xx_init_subghz_debug_pins(void)
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{
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#if IS_ACTIVE(CONFIG_STM32_WLX5XX_SUBGHZ_DEBUG)
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/* SUBGHZSPI Debug */
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gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT,
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CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT_AF);
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gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT,
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CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT_AF);
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gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT,
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CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT_AF);
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gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT,
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CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT_AF);
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/* Sub-GHz Radio Debug */
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gpio_init(CPU_STM32WL_SUBGHZ_RF_BUSY, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZ_RF_BUSY,
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CPU_STM32WL_SUBGHZ_RF_BUSY_AF);
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gpio_init(CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET,
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CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET_AF);
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gpio_init(CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY,
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CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY_AF);
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gpio_init(CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY,
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CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY_AF);
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gpio_init(CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY, GPIO_OUT);
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gpio_init_af(CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY,
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CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY_AF);
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#endif
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}
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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/* enable PWR module */
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#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && \
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!defined(CPU_FAM_STM32WL)
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periph_clk_en(APB1, BIT_APB_PWREN);
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#endif
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
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defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
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defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
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defined(CPU_FAM_STM32L1)
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_gpio_init_ain();
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#endif
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#if !defined(CPU_FAM_STM32MP1) || IS_USED(MODULE_STM32MP1_ENG_MODE)
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/* initialize the system clock as configured in the periph_conf.h */
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stmclk_init_sysclk();
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#endif
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#ifdef MODULE_PERIPH_DMA
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/* initialize DMA streams */
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dma_init();
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#endif
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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stdio_init();
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#ifdef STM32F1_DISABLE_JTAG
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RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
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AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE;
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#endif
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/* trigger static peripheral initialization */
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periph_init();
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if (IS_ACTIVE(CONFIG_STM32_WLX5XX_SUBGHZ_DEBUG)) {
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_wlx5xx_init_subghz_debug_pins();
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}
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}
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