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660 lines
16 KiB
C
660 lines
16 KiB
C
/*
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* Copyright (C) 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @brief Compute clock constants for STM32F[2|4|7] CPUs
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*
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @{
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*/
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#ifndef CLK_CONF_H
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#define CLK_CONF_H
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name STM32 families
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* @{
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*/
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enum fam {
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STM32F0,
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STM32F1,
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STM32F2,
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STM32F3,
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STM32F4,
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STM32F7,
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STM32MP1,
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FAM_MAX,
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};
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/** @} */
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/**
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* @name Supported models
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* @{
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*/
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enum {
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STM32F030,
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STM32F070,
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STM32F031,
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STM32F051,
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STM32F071,
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STM32F091,
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STM32F042,
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STM32F072,
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STM32F038,
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STM32F048,
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STM32F058,
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STM32F078,
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STM32F098,
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STM32F100,
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STM32F101,
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STM32F102,
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STM32F103,
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STM32F205,
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STM32F207,
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STM32F215,
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STM32F217,
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STM32F301,
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STM32F302,
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STM32F303,
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STM32F334,
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STM32F373,
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STM32F318,
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STM32F328,
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STM32F358,
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STM32F378,
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STM32F398,
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STM32F401,
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STM32F405,
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STM32F407,
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STM32F410,
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STM32F411,
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STM32F412,
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STM32F413,
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STM32F415,
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STM32F417,
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STM32F423,
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STM32F427,
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STM32F429,
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STM32F437,
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STM32F439,
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STM32F446,
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STM32F469,
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STM32F479,
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STM32F722,
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STM32F732,
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STM32F746,
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STM32F756,
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STM32F767,
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STM32F769,
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STM32F777,
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STM32F779,
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MODEL_F_MAX,
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};
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enum {
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STM32MP157,
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MODEL_MP_MAX,
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};
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/** @} */
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/**
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* @brief PLL configuration parameters
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*
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* PLL configuration follows the model:
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* ```
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*
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* pll_in +----+ vco_in +------------------------------+
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* --------| /M |----------|\ +----+ vco_out +----+ |
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* +----+ | --| xN |-------------| /P |--|-- pll_p_out
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* | +----+ \ +----+ |
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* | | +----+ |
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* | ---| /Q |--|-- pll_q_out
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* | | +----+ |
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* | | +----+ |
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* | ---| /R |--|-- pll_r_out
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* | +----+ |
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* +------------------------------+
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* ```
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*
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* vco_in = pll_in / M;
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* vco_out = vco_in * N;
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* pll_p_out = vco_out / P;
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* pll_q_out = vco_out / Q;
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* pll_r_out = vco_out / R;
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*/
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typedef struct {
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unsigned min_vco_input; /**< Min VCO input */
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unsigned max_vco_input; /**< Max VCO input */
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unsigned min_vco_output; /**< Min VCO output */
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unsigned max_vco_output; /**< Max VCO output */
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unsigned min_n; /**< Min N */
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unsigned max_n; /**< Max N */
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unsigned inc_n; /**< Increment between two values of N */
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unsigned min_m; /**< Min M */
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unsigned max_m; /**< Max M */
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unsigned inc_m; /**< Increment between two values of M */
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unsigned min_p; /**< Min P */
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unsigned max_p; /**< Max P */
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unsigned inc_p; /**< Increment between two values of P */
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unsigned min_q; /**< Min Q */
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unsigned max_q; /**< Max Q */
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unsigned inc_q; /**< Increment between two values of Q */
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} pll_cfg_t;
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/**
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* @brief Clock configuration
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*/
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typedef struct {
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enum fam family; /**< Family */
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unsigned max_coreclock; /**< Max coreclock */
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unsigned max_apb1; /**< Max APB1 clock */
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unsigned max_apb2; /**< Max APB2 clock */
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unsigned max_apb3; /**< Max APB3 clock */
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unsigned hsi; /**< HSI frequency */
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pll_cfg_t pll; /**< PLL configuration */
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bool has_pll_i2s; /**< PLL I2S available */
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bool has_pll_sai; /**< PLL SAI available */
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bool has_pll_i2s_m; /**< PLL I2S has a M factor */
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bool has_pll_sai_m; /**< PLL SAI has a M factor */
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bool has_pll_i2s_alt_input; /**< PLL I2S has an external input available */
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unsigned hsi_prediv; /**< Value if HSI has a fixed prediv, 0 otherwise */
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int has_alt_48MHz; /**< 48MHz can be generated by an alternate source */
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bool need_48MHz; /**< 48MHz is needed */
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} clk_cfg_t;
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/**
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* @name Alternative 48MHz sources
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* @{
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*/
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#define ALT_48MHZ_NO 0
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#define ALT_48MHZ_I2S 1
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#define ALT_48MHZ_SAI 2
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#define ALT_48MHZ_Q 0
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#define ALT_48MHZ_P 4
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/** @} */
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#define STM32F(x) [STM32F##x] = x
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#define STM32F0(x) [STM32F0##x] = x
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/** List of supported models */
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static const unsigned stm32_f_model[] = {
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STM32F0(30),
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STM32F0(70),
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STM32F0(31),
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STM32F0(51),
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STM32F0(71),
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STM32F0(91),
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STM32F0(42),
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STM32F0(72),
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STM32F0(38),
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STM32F0(48),
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STM32F0(58),
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STM32F0(78),
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STM32F0(98),
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STM32F(100),
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STM32F(101),
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STM32F(102),
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STM32F(103),
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STM32F(205),
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STM32F(207),
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STM32F(215),
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STM32F(217),
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STM32F(301),
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STM32F(302),
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STM32F(303),
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STM32F(334),
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STM32F(373),
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STM32F(318),
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STM32F(328),
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STM32F(358),
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STM32F(378),
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STM32F(398),
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STM32F(401),
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STM32F(405),
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STM32F(407),
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STM32F(410),
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STM32F(411),
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STM32F(412),
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STM32F(413),
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STM32F(415),
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STM32F(417),
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STM32F(423),
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STM32F(427),
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STM32F(429),
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STM32F(437),
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STM32F(439),
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STM32F(446),
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STM32F(469),
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STM32F(479),
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STM32F(722),
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STM32F(732),
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STM32F(746),
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STM32F(756),
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STM32F(767),
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STM32F(769),
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STM32F(777),
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STM32F(779),
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};
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#define STM32MP(x) [STM32MP##x] = x
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/** List of supported models */
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static const unsigned stm32_model_mp[] = {
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STM32MP(157),
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};
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/** STM32F2xx / STM32F401 PLL config */
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#define stm32f2_4_192_pll_cfg { \
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.min_vco_input = 1000000U, \
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.max_vco_input = 2000000U, \
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.min_vco_output = 192000000U, \
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.max_vco_output = 432000000U, \
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.min_n = 50, \
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.max_n = 432, \
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.inc_n = 1, \
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.min_m = 2, \
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.max_m = 63, \
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.inc_m = 1, \
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.min_p = 2, \
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.max_p = 8, \
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.inc_p = 2, \
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.min_q = 2, \
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.max_q = 15, \
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.inc_q = 1, \
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}
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/** STM32F4 (except 401) / STM32F7 PLL config */
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#define stm32f4_7_pll_cfg { \
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.min_vco_input = 1000000U, \
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.max_vco_input = 2000000U, \
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.min_vco_output = 192000000U, \
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.max_vco_output = 432000000U, \
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.min_n = 50, \
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.max_n = 432, \
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.inc_n = 1, \
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.min_m = 2, \
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.max_m = 63, \
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.inc_m = 1, \
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.min_p = 2, \
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.max_p = 8, \
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.inc_p = 2, \
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.min_q = 2, \
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.max_q = 15, \
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.inc_q = 1, \
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}
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/** STM32MP1 PLL config */
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#define stm32mp1_pll_cfg { \
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.min_vco_input = 4000000U, \
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.max_vco_input = 16000000U, \
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.min_vco_output = 400000000U, \
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.max_vco_output = 800000000U, \
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.min_n = 25, \
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.max_n = 100, \
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.inc_n = 1, \
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.min_m = 2, \
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.max_m = 63, \
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.inc_m = 1, \
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.min_p = 2, \
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.max_p = 127, \
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.inc_p = 1, \
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.min_q = 2, \
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.max_q = 127, \
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.inc_q = 1, \
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}
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/**
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* @brief Clock config for supported cpu
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*/
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static const clk_cfg_t stm32_f_clk_cfg[] = {
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[STM32F030 ... STM32F098] = {
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.family = STM32F0,
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.max_coreclock = 48000000U,
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.max_apb1 = 48000000U,
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.max_apb2 = 0,
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.hsi = 8000000U,
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.pll = {
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.min_vco_input = 1000000U,
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.max_vco_input = 24000000U,
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.min_vco_output = 16000000U,
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.max_vco_output = 48000000U,
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.min_m = 1,
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.max_m = 16,
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.inc_m = 1,
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.min_n = 2,
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.max_n = 16,
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.inc_n = 1,
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.min_p = 1,
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.max_p = 1,
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.inc_p = 1,
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},
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.has_pll_i2s = false,
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.has_pll_sai = false,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.hsi_prediv = 2,
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.need_48MHz = false,
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},
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[STM32F100] = {
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.family = STM32F1,
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.max_coreclock = 24000000U,
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.max_apb1 = 24000000U,
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.max_apb2 = 24000000U,
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.hsi = 8000000U,
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.pll = {
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.min_vco_input = 1000000U,
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.max_vco_input = 24000000U,
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.min_vco_output = 16000000U,
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.max_vco_output = 24000000U,
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.min_m = 1,
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.max_m = 16,
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.inc_m = 1,
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.min_n = 2,
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.max_n = 16,
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.inc_n = 1,
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.min_p = 1,
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.max_p = 1,
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.inc_p = 1,
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},
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.has_pll_i2s = false,
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.has_pll_sai = false,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.hsi_prediv = 2,
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.need_48MHz = false,
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},
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[STM32F101 ... STM32F103] = {
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.family = STM32F1,
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.max_coreclock = 72000000U,
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.max_apb1 = 36000000U,
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.max_apb2 = 72000000U,
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.hsi = 8000000U,
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.pll = {
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.min_vco_input = 1000000U,
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.max_vco_input = 25000000U,
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.min_vco_output = 1000000U,
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.max_vco_output = 72000000U,
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.min_m = 1,
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.max_m = 16,
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.inc_m = 1,
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.min_n = 2,
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.max_n = 16,
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.inc_n = 1,
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.min_p = 1,
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.max_p = 1,
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.inc_p = 1,
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},
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.has_pll_i2s = false,
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.has_pll_sai = false,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.hsi_prediv = 2,
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.need_48MHz = false,
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},
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[STM32F205 ... STM32F217] = {
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.family = STM32F2,
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.max_coreclock = 120000000U,
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.max_apb1 = 30000000U,
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.max_apb2 = 60000000U,
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.hsi = 16000000U,
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.pll = stm32f2_4_192_pll_cfg,
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.has_pll_i2s = true,
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.has_pll_sai = false,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.need_48MHz = true,
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},
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[STM32F301 ... STM32F398] = {
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.family = STM32F3,
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.max_coreclock = 72000000U,
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.max_apb1 = 36000000U,
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.max_apb2 = 72000000U,
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.hsi = 8000000U,
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.pll = {
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.min_vco_input = 1000000U,
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.max_vco_input = 25000000U,
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.min_vco_output = 1000000U,
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.max_vco_output = 72000000U,
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.min_m = 1,
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.max_m = 16,
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.inc_m = 1,
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.min_n = 2,
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.max_n = 16,
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.inc_n = 1,
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.min_p = 1,
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.max_p = 1,
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.inc_p = 1,
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},
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.has_pll_i2s = false,
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.has_pll_sai = false,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.hsi_prediv = 2,
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.need_48MHz = false,
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},
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[STM32F401] = {
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.family = STM32F4,
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.max_coreclock = 84000000U,
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.max_apb1 = 42000000U,
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.max_apb2 = 84000000U,
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.hsi = 16000000U,
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.pll = stm32f2_4_192_pll_cfg,
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.has_pll_i2s = true,
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.has_pll_sai = false,
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.has_pll_i2s_m = false,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.need_48MHz = true,
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},
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[STM32F405 ... STM32F407] = {
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.family = STM32F4,
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.max_coreclock = 168000000U,
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.max_apb1 = 42000000U,
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.max_apb2 = 84000000U,
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.hsi = 16000000U,
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.pll = stm32f4_7_pll_cfg,
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.has_pll_i2s = true,
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.has_pll_sai = false,
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.has_pll_i2s_m = false,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.need_48MHz = true,
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},
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[STM32F410] = {
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.family = STM32F4,
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.max_coreclock = 100000000U,
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.max_apb1 = 50000000U,
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.max_apb2 = 100000000U,
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.hsi = 16000000U,
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.pll = stm32f4_7_pll_cfg,
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.has_pll_i2s = false,
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.has_pll_sai = false,
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.has_pll_i2s_m = false,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.need_48MHz = true,
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},
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[STM32F411] = {
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.family = STM32F4,
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.max_coreclock = 100000000U,
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.max_apb1 = 50000000U,
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.max_apb2 = 100000000U,
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.hsi = 16000000U,
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.pll = stm32f4_7_pll_cfg,
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.has_pll_i2s = true,
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.has_pll_sai = false,
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.has_pll_i2s_m = true,
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.has_pll_i2s_alt_input = false,
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.has_alt_48MHz = 0,
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.need_48MHz = true,
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},
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[STM32F412 ... STM32F413] = {
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.family = STM32F4,
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.max_coreclock = 100000000U,
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.max_apb1 = 50000000U,
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.max_apb2 = 100000000U,
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|
.hsi = 16000000U,
|
|
.pll = stm32f4_7_pll_cfg,
|
|
.has_pll_i2s = true,
|
|
.has_pll_sai = true,
|
|
.has_pll_i2s_m = true,
|
|
.has_pll_sai_m = false,
|
|
.has_pll_i2s_alt_input = true,
|
|
.has_alt_48MHz = ALT_48MHZ_I2S,
|
|
.need_48MHz = true,
|
|
},
|
|
[STM32F415 ... STM32F417] = {
|
|
.family = STM32F4,
|
|
.max_coreclock = 168000000U,
|
|
.max_apb1 = 42000000U,
|
|
.max_apb2 = 84000000U,
|
|
.hsi = 16000000U,
|
|
.pll = stm32f4_7_pll_cfg,
|
|
.has_pll_i2s = true,
|
|
.has_pll_sai = false,
|
|
.has_pll_i2s_m = false,
|
|
.has_pll_i2s_alt_input = false,
|
|
.has_alt_48MHz = 0,
|
|
.need_48MHz = true,
|
|
},
|
|
[STM32F423] = {
|
|
.family = STM32F4,
|
|
.max_coreclock = 100000000U,
|
|
.max_apb1 = 50000000U,
|
|
.max_apb2 = 100000000U,
|
|
.hsi = 16000000U,
|
|
.pll = stm32f4_7_pll_cfg,
|
|
.has_pll_i2s = true,
|
|
.has_pll_sai = true,
|
|
.has_pll_i2s_m = true,
|
|
.has_pll_sai_m = false,
|
|
.has_pll_i2s_alt_input = true,
|
|
.has_alt_48MHz = ALT_48MHZ_I2S,
|
|
.need_48MHz = true,
|
|
},
|
|
[STM32F427 ... STM32F439] = {
|
|
.family = STM32F4,
|
|
.max_coreclock = 180000000U,
|
|
.max_apb1 = 45000000U,
|
|
.max_apb2 = 90000000U,
|
|
.hsi = 16000000U,
|
|
.pll = stm32f4_7_pll_cfg,
|
|
.has_pll_i2s = true,
|
|
.has_pll_sai = true,
|
|
.has_pll_i2s_m = false,
|
|
.has_pll_sai_m = false,
|
|
.has_pll_i2s_alt_input = false,
|
|
.has_alt_48MHz = 0,
|
|
.need_48MHz = true,
|
|
},
|
|
[STM32F446] = {
|
|
.family = STM32F4,
|
|
.max_coreclock = 180000000U,
|
|
.max_apb1 = 45000000U,
|
|
.max_apb2 = 90000000U,
|
|
.hsi = 16000000U,
|
|
.pll = stm32f4_7_pll_cfg,
|
|
.has_pll_i2s = true,
|
|
.has_pll_sai = true,
|
|
.has_pll_i2s_m = true,
|
|
.has_pll_sai_m = true,
|
|
.has_pll_i2s_alt_input = false,
|
|
.has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
|
|
.need_48MHz = true,
|
|
},
|
|
[STM32F469 ... STM32F479] = {
|
|
.family = STM32F4,
|
|
.max_coreclock = 180000000U,
|
|
.max_apb1 = 45000000U,
|
|
.max_apb2 = 90000000U,
|
|
.hsi = 16000000U,
|
|
.pll = stm32f4_7_pll_cfg,
|
|
.has_pll_i2s = true,
|
|
.has_pll_sai = true,
|
|
.has_pll_i2s_m = false,
|
|
.has_pll_sai_m = false,
|
|
.has_pll_i2s_alt_input = false,
|
|
.has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
|
|
.need_48MHz = true,
|
|
},
|
|
[STM32F722 ... STM32F779] = {
|
|
.family = STM32F7,
|
|
.max_coreclock = 216000000U,
|
|
.max_apb1 = 54000000U,
|
|
.max_apb2 = 108000000U,
|
|
.hsi = 16000000U,
|
|
.pll = stm32f4_7_pll_cfg,
|
|
.has_pll_i2s = true,
|
|
.has_pll_sai = true,
|
|
.has_pll_i2s_m = false,
|
|
.has_pll_sai_m = false,
|
|
.has_pll_i2s_alt_input = false,
|
|
.has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
|
|
.need_48MHz = true,
|
|
},
|
|
};
|
|
|
|
/**
|
|
* @brief Clock config for supported cpu
|
|
*/
|
|
static const clk_cfg_t stm32_mp_clk_cfg[] = {
|
|
[STM32MP157] = {
|
|
.family = STM32MP1,
|
|
.max_coreclock = 209000000U,
|
|
.max_apb1 = 104500000U,
|
|
.max_apb2 = 104500000U,
|
|
.max_apb3 = 104500000U,
|
|
.hsi = 64000000U,
|
|
.pll = stm32mp1_pll_cfg,
|
|
.has_pll_i2s = false,
|
|
.has_pll_sai = false,
|
|
.has_pll_i2s_m = false,
|
|
.has_pll_sai_m = false,
|
|
.has_pll_i2s_alt_input = false,
|
|
.has_alt_48MHz = 0,
|
|
.need_48MHz = true,
|
|
},
|
|
};
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* CLK_CONF_H */
|
|
/** @} */
|