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118 lines
5.1 KiB
C
118 lines
5.1 KiB
C
/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26xx_cc13xx
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* @{
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*
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* @file
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* @brief Interrupt vector definitions
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*
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* @author Leon M. George <leon@georgemail.eu>
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* @author Anton Gerasimov <tossel@gmail.com>
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "board.h"
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* CC26xx_CC13xx specific interrupt vectors */
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WEAK_DEFAULT void isr_edge(void);
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WEAK_DEFAULT void isr_i2c(void);
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WEAK_DEFAULT void isr_rfc_cpe1(void);
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WEAK_DEFAULT void isr_pka(void);
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WEAK_DEFAULT void isr_aon_rtc(void);
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WEAK_DEFAULT void isr_uart0(void);
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WEAK_DEFAULT void isr_aux0_aon(void);
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WEAK_DEFAULT void isr_ssi0(void);
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WEAK_DEFAULT void isr_ssi1(void);
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WEAK_DEFAULT void isr_rfc_cpe0(void);
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WEAK_DEFAULT void isr_rfc_hw(void);
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WEAK_DEFAULT void isr_rfc_cmd_ack(void);
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WEAK_DEFAULT void isr_i2s(void);
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WEAK_DEFAULT void isr_aux1_aon(void);
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WEAK_DEFAULT void isr_watchdog(void);
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WEAK_DEFAULT void isr_timer0_chan0(void);
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WEAK_DEFAULT void isr_timer0_chan1(void);
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WEAK_DEFAULT void isr_timer1_chan0(void);
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WEAK_DEFAULT void isr_timer1_chan1(void);
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WEAK_DEFAULT void isr_timer2_chan0(void);
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WEAK_DEFAULT void isr_timer2_chan1(void);
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WEAK_DEFAULT void isr_timer3_chan0(void);
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WEAK_DEFAULT void isr_timer3_chan1(void);
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WEAK_DEFAULT void isr_crypto_res(void);
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WEAK_DEFAULT void isr_dma(void);
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WEAK_DEFAULT void isr_dmaerr(void);
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WEAK_DEFAULT void isr_flash(void);
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WEAK_DEFAULT void isr_se0(void);
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WEAK_DEFAULT void isr_aux_ce(void);
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WEAK_DEFAULT void isr_aon_prog(void);
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WEAK_DEFAULT void isr_dyn_prog(void);
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WEAK_DEFAULT void isr_comp(void);
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WEAK_DEFAULT void isr_adc(void);
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WEAK_DEFAULT void isr_trng(void);
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#ifdef CPU_VARIANT_X2
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WEAK_DEFAULT void isr_osc(void);
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WEAK_DEFAULT void isr_aux_timer2(void);
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WEAK_DEFAULT void isr_uart1(void);
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WEAK_DEFAULT void isr_batmon(void);
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#endif // CPU_VARIANT_X2
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[] = {
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isr_edge, /* 16 AON edge detect */
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isr_i2c, /* 17 I2C */
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isr_rfc_cpe1, /* 18 RF Command and Packet Engine 1 */
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isr_pka, /* 19 PKA interrupt */
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isr_aon_rtc, /* 20 AON RTC */
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isr_uart0, /* 21 UART0 Rx and Tx */
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isr_aux0_aon, /* 22 AUX event 0, through AON domain */
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isr_ssi0, /* 23 SSI0 Rx and Tx */
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isr_ssi1, /* 24 SSI1 Rx and Tx */
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isr_rfc_cpe0, /* 25 RF Command and Packet Engine 0 */
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isr_rfc_hw, /* 26 RF Core Hardware */
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isr_rfc_cmd_ack, /* 27 RF Core Command Acknowledge */
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isr_i2s, /* 28 I2S */
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isr_aux1_aon, /* 29 AUX event 1, through AON domain */
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isr_watchdog, /* 30 Watchdog timer */
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isr_timer0_chan0, /* 31 Timer 0 subtimer A */
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isr_timer0_chan1, /* 32 Timer 0 subtimer B */
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isr_timer1_chan0, /* 33 Timer 1 subtimer A */
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isr_timer1_chan1, /* 34 Timer 1 subtimer B */
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isr_timer2_chan0, /* 35 Timer 2 subtimer A */
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isr_timer2_chan1, /* 36 Timer 2 subtimer B */
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isr_timer3_chan0, /* 37 Timer 3 subtimer A */
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isr_timer3_chan1, /* 38 Timer 3 subtimer B */
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isr_crypto_res, /* 39 Crypto Core Result available */
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isr_dma, /* 40 uDMA Software */
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isr_dmaerr, /* 41 uDMA Error */
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isr_flash, /* 42 Flash controller */
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isr_se0, /* 43 Software Event 0 */
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isr_aux_ce, /* 44 AUX combined event, directly to MCU domain */
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isr_aon_prog, /* 45 AON programmable 0 */
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isr_dyn_prog, /* 46 Dynamic Programmable interrupt (default source: PRCM) */
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isr_comp, /* 47 AUX Comparator A */
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isr_adc, /* 48 AUX ADC IRQ */
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isr_trng, /* 49 TRNG event */
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#ifdef CPU_VARIANT_X2
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isr_osc, /* 50 Combined event from oscillator control */
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isr_aux_timer2, /* 51 AUX Timer 2 event 0 */
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isr_uart1, /* 52 UART 1 RX and TX */
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isr_batmon, /* 53 BATMON interrupt */
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#endif // CPU_VARIANT_X2
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};
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/** @} */
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