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107 lines
2.3 KiB
C
107 lines
2.3 KiB
C
/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_lm4f120
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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* @}
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*/
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#include "cpu.h"
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#include "irq.h"
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#include "kernel.h"
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#include "kernel_internal.h"
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#include "sched.h"
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#include "thread.h"
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#include "arch/thread_arch.h"
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#include "arch/irq_arch.h"
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unsigned long __attribute__((naked))
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CPUipsrGet(void)
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{
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unsigned long ulRet;
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//
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// Read IPSR
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//
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__asm(" mrs r0, IPSR\n"
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" bx lr\n"
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: "=r" (ulRet));
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//
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// The return is handled in the inline assembly, but the compiler will
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// still complain if there is not an explicit return here (despite the fact
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// that this does not result in any code being produced because of the
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// naked attribute).
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//
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return(ulRet);
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}
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void __attribute__((naked))
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DisableInterrupts(void)
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{
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__asm(" CPSID I\n"
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" BX LR\n");
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}
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void __attribute__((naked))
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EnableInterrupts(void)
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{
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__asm(" CPSIE I\n"
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" BX LR\n");
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}
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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// initializes the Cortex-M core
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cortexm_init();
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/* initialize the clock system */
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cpu_clock_init(CLK40);
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}
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void setup_fpu(void)
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{
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ROM_FPUEnable();
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ROM_FPULazyStackingEnable();
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}
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void cpu_clock_init(int clk)
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{
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setup_fpu();
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switch(clk){
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case CLK80:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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case CLK50:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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case CLK40:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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case CLK16:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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case CLK1:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_1MHZ | SYSCTL_OSC_MAIN);
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break;
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default:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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}
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}
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