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Adding Support for Stellaris Launchpad LM4f120. This board is based on ARM Cortex M4 from TI.

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This commit is contained in:
Rakendra Thapa 2015-07-04 13:07:54 +05:30
parent 63cf9a3d4b
commit 0b673e66da
64 changed files with 45262 additions and 0 deletions
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4
boards/ek-lm4f120xl/Makefile Normal file
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# tell the Makefile.base which module to build
MODULE = $(BOARD)_base
include $(RIOTBASE)/Makefile.base

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boards/ek-lm4f120xl/Makefile.features Normal file
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FEATURES_PROVIDED += cpp
#FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_cpuid
FEATURES_MCU_GROUP = cortex_m4

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boards/ek-lm4f120xl/Makefile.include Normal file
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# define the cpu used by the ek-lm4f120xl board
export CPU = lm4f120
export CPU_MODEL = lm4f120
#define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)
# setup serial terminal
include $(RIOTBOARD)/Makefile.include.serial
# this board uses openocd
include $(RIOTBOARD)/Makefile.include.openocd
# include cortex defaults
include $(RIOTBOARD)/Makefile.include.cortexm_common
# define stellaris specific flags and includes
export STELLARISWARE = $(RIOTCPU)/stellaris_common/include
# define build specific options
PART = LM4F120H5QR
export CFLAGS += -I$(STELLARISWARE) -DPART_$(PART) -c -DTARGET_IS_BLIZZARD_RA1

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boards/ek-lm4f120xl/board.c Normal file
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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_ek-lm4f120xl
* @{
*
* @file board.c
* @brief Board specific implementations for the Stellaris Launchpad LM4F120 board
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*
* @}
*/
#include "board.h"
static void leds_init(void);
void board_init(void)
{
/* initialize the boards LEDs, this is done for debugging purpose */
leds_init();
/* initialize the CPU */
cpu_init();
}
/**
* @brief initialize the boards on-boards LEDS.
*/
static void leds_init(void)
{
// enable clock for PORTF
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
//configure the pins as general output
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);
// Turn Red led on
ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 2);
}

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boards/ek-lm4f120xl/cscope.out Normal file
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boards/ek-lm4f120xl/dist/openocd.cfg vendored Normal file
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source [find board/ek-lm4f120xl.cfg]

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boards/ek-lm4f120xl/include/board.h Normal file
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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup ek-lm4f120xl
* @ingroup boards_ek-lm4f120xl
* @brief Board specific files for the Stellaris Launchpad LM4F120 board
* @{
*
* @file
* @brief Board specific definitions for the Stellaris Launchpad LM4F120 board
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef __BOARD_H
#define __BOARD_H
#include "cpu.h"
#include "periph/uart.h"
#include "periph/timer.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Define the boards stdio
* @{
*/
#define STDIO UART_0
#define STDIO_BAUDRATE 115200
#define STDIO_RX_BUFSIZE UART0_BUFSIZE
/** @} */
/**
* @name Assign the hardware timer
*/
#define HW_TIMER TIMER_0
/**
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LED_GREEN_PIN 0x08
#define LED_BLUE_PIN 0x04
#define LED_RED_PIN 0x02
#define LED_GREEN_ON GPIO_PORTF_DATA_R |= LED_GREEN_PIN
#define LED_GREEN_OFF GPIO_PORTF_DATA_R &= ~(LED_GREEN_PIN)
#define LED_GREEN_TOGGLE /* not available */
#define LED_BLUE_ON GPIO_PORTF_DATA_R |= LED_BLUE_PIN
#define LED_BLUE_OFF GPIO_PORTF_DATA_R &= ~(LED_BLUE_PIN)
#define LED_BLUE_TOGGLE /* not available */
#define LED_RED_ON GPIO_PORTF_DATA_R |= LED_RED_PIN
#define LED_RED_OFF GPIO_PORTF_DATA_R &= ~(LED_RED_PIN)
#define LED_RED_TOGGLE /* not available */
/* @} */
#define TRACE printf("TRACE %s:%d: %s\n", __FILE__, __LINE__, __FUNCTION__)
#define VAL_I(x) printf(#x ": %d\n",x);
#define VAL_X(x) printf(#x ":0x%X\n", (unsigned int)x);
#define VAL_S(x) printf(#x ":%s\n", x);
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
extern void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /** __BOARD_H */
/** @} */

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boards/ek-lm4f120xl/include/periph_conf.h Normal file
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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_ek-lm4f120xl
* @{
*
* @file
* @name Peripheral MCU configuration for the ek-lm4f120xl board
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef __PERIPH_CONF_H
#define __PERIPH_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Timer configuration
* @{
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 0
#define TIMER_IRQ_PRIO 1
/* Timer 0 configuration */
//#define TIMER_0_DEV TIM2
#define TIMER_0_CHANNELS 2
#define TIMER_0_PRESCALER (39U)
#define TIMER_0_MAX_VALUE (0xffffffff)
#define TIMER_0_ISR WTIMER0IntHandler
#define TIMER_0_IRQ_CHAN Timer0A_IRQn
/* Timer 1 configuration */
#define TIMER_1_CHANNELS 2
#define TIMER_1_PRESCALER (39U)
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_ISR TIMER1IntHandler
#define TIMER_1_IRQ_CHAN Timer1A_IRQn
/** @} */
/** @} */
/**
* @name UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN 1
#define UART_1_EN 0
#define UART_IRQ_PRIO 1
#define UART_CLK ROM_SysCtlClockGet() /*RT clock runs with 40MHz */
/* UART 0 device configuration */
#define UART_0_DEV UART0_BASE
#define UART_0_CLK (40000000) /* UART clock runs with 42MHz (F_CPU / 4) */
#define UART_0_IRQ_CHAN UART0_IRQn
#define UART_0_ISR UARTIntHandler
/* UART 0 pin configuration */
#define UART_0_PORT GPIOA
#define UART_0_TX_PIN UART_PA1_U0TX
#define UART_0_RX_PIN UART_PA0_U0RX
#define UART_0_AF 7
/* UART 1 device configuration */
#define UART_1_DEV UART1_BASE
#define UART_1_CLK (40000000) /* UART clock runs with 40MHz (F_CPU / 4) */
#define UART_1_IRQ_CHAN UART1_IRQn
#define UART_1_ISR UART1IntHandler
/* UART 1 pin configuration */
#define UART_1_PORT GPIOD
#define UART_1_TX_PIN 8
#define UART_1_RX_PIN 9
#define UART_1_AF 7
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (2U)
#define ADC_0_EN 1
#define ADC_1_EN 1
#define ADC_MAX_CHANNELS 2
/** @} */
/* ADC 0 configuration */
#define ADC_0_DEV ADC0_BASE
#define ADC_0_CHANNELS 2
#define ADC_0_PORT GPIO_PORTE_BASE
/* ADC 0 channel 0 pin config */
#define ADC_0_CH0 1
#define ADC_0_CH0_PIN GPIO_PIN_3
/* ADC 0 channel 1 pin config */
#define ADC_0_CH1 4
#define ADC_0_CH1_PIN 4
/* ADC 1 configuration */
#define ADC_1_DEV ADC1_BASE
#define ADC_1_CHANNELS 2
#define ADC_1_PORT GPIO_PORTE_BASE
#define ADC_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
/* ADC 1 channel 0 pin config */
#define ADC_1_CH0 11
#define ADC_1_CH0_PIN GPIO_PIN_2
/* ADC 1 channel 1 pin config */
#define ADC_1_CH1 12
#define ADC_1_CH1_PIN 2
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (1U)
#define DAC_0_EN 1
#define DAC_MAX_CHANNELS 2
/* DAC 0 configuration */
#define DAC_0_DEV DAC
#define DAC_0_CHANNELS 2
#define DAC_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
#define DAC_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#define DAC_0_PORT GPIOA
#define DAC_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
/* DAC 0 channel config */
#define DAC_0_CH0_PIN 4
#define DAC_0_CH1_PIN 5
/**
* @name PWM configuration
* @{
*/
#define PWM_NUMOF (2U)
#define PWM_0_EN 1
#define PWM_1_EN 1
#define PWM_MAX_CHANNELS 4
/* PWM 0 device configuration */
#define PWM_0_DEV TIM1
#define PWM_0_CHANNELS 4
#define PWM_0_CLK (168000000U)
#define PWM_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_TIM1EN)
#define PWM_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN)
/* PWM 0 pin configuration */
#define PWM_0_PORT GPIOE
#define PWM_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN)
#define PWM_0_PIN_CH0 9
#define PWM_0_PIN_CH1 11
#define PWM_0_PIN_CH2 13
#define PWM_0_PIN_CH3 14
#define PWM_0_PIN_AF 1
/* PWM 1 device configuration */
#define PWM_1_DEV TIM3
#define PWM_1_CHANNELS 3
#define PWM_1_CLK (84000000U)
#define PWM_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN)
#define PWM_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN)
/* PWM 1 pin configuration */
#define PWM_1_PORT GPIOB
#define PWM_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
#define PWM_1_PIN_CH0 4
#define PWM_1_PIN_CH1 5
#define PWM_1_PIN_CH2 0
#define PWM_1_PIN_CH3 1
#define PWM_1_PIN_AF 2
/** @} */
/**
* @name Random Number Generator configuration
* @{
*/
#define RANDOM_NUMOF (1U)
/** @} */
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
#define SPI_1_BUS_DIV 0 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_IRQ_HANDLER isr_spi2
/* SPI 1 pin configuration */
#define SPI_1_SCK_PORT GPIOB
#define SPI_1_SCK_PIN 13
#define SPI_1_SCK_AF 5
#define SPI_1_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
#define SPI_1_MISO_PORT GPIOB
#define SPI_1_MISO_PIN 14
#define SPI_1_MISO_AF 5
#define SPI_1_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
#define SPI_1_MOSI_PORT GPIOB
#define SPI_1_MOSI_PIN 15
#define SPI_1_MOSI_AF 5
#define SPI_1_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (1U)
#define I2C_0_EN 1
#define I2C_IRQ_PRIO 1
#define I2C_APBCLK (42000000U)
/* I2C 0 device configuration */
#define I2C_0_DEV I2C1
#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define I2C_0_EVT_IRQ I2C1_EV_IRQn
#define I2C_0_EVT_ISR isr_i2c1_ev
#define I2C_0_ERR_IRQ I2C1_ER_IRQn
#define I2C_0_ERR_ISR isr_i2c1_er
/* I2C 0 pin configuration */
#define I2C_0_SCL_PORT GPIOB
#define I2C_0_SCL_PIN 6
#define I2C_0_SCL_AF 4
#define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
#define I2C_0_SDA_PORT GPIOB
#define I2C_0_SDA_PIN 7
#define I2C_0_SDA_AF 4
#define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
/** @} */
/**
* @name GPIO configuration
* @{
*/
#define GPIO_NUMOF 12
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_6_EN 1
#define GPIO_7_EN 1
#define GPIO_8_EN 1
#define GPIO_9_EN 1
#define GPIO_10_EN 1
#define GPIO_11_EN 1
#define GPIO_IRQ_PRIO 1
/* IRQ config */
#define GPIO_IRQ_0 GPIO_0 /* alternatively GPIO_1 could be used here */
#define GPIO_IRQ_1 GPIO_2
#define GPIO_IRQ_2 GPIO_3
#define GPIO_IRQ_3 GPIO_4
#define GPIO_IRQ_4 GPIO_5
#define GPIO_IRQ_5 GPIO_6
#define GPIO_IRQ_6 GPIO_7
#define GPIO_IRQ_7 GPIO_8
#define GPIO_IRQ_8 GPIO_9
#define GPIO_IRQ_9 GPIO_10
#define GPIO_IRQ_10 GPIO_11
#define GPIO_IRQ_11 -1/* not configured */
#define GPIO_IRQ_12 -1/* not configured */
#define GPIO_IRQ_13 -1/* not configured */
#define GPIO_IRQ_14 -1/* not configured */
#define GPIO_IRQ_15 -1/* not configured */
/* GPIO channel 0 config */
#define GPIO_0_PORT GPIOA /* Used for user button 1 */
#define GPIO_0_PIN 0
#define GPIO_0_CLK 0 /* 0: PORT A, 1: B ... */
#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA)
#define GPIO_0_IRQ EXTI0_IRQn
/* GPIO channel 1 config */
#define GPIO_1_PORT GPIOE /* LIS302DL INT1 */
#define GPIO_1_PIN 0
#define GPIO_1_CLK 4
#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PE)
#define GPIO_1_IRQ EXTI0_IRQn
/* GPIO channel 2 config */
#define GPIO_2_PORT GPIOE /* LIS302DL INT2 */
#define GPIO_2_PIN 1
#define GPIO_2_CLK 4
#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PE)
#define GPIO_2_IRQ EXTI1_IRQn
/* GPIO channel 3 config */
#define GPIO_3_PORT GPIOE
#define GPIO_3_PIN 2
#define GPIO_3_CLK 4
#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PE)
#define GPIO_3_IRQ EXTI2_IRQn
/* GPIO channel 4 config */
#define GPIO_4_PORT GPIOE /* LIS302DL CS */
#define GPIO_4_PIN 3
#define GPIO_4_CLK 4
#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PE)
#define GPIO_4_IRQ EXTI3_IRQn
/* GPIO channel 5 config */
#define GPIO_5_PORT GPIOD /* CS43L22 RESET */
#define GPIO_5_PIN 4
#define GPIO_5_CLK 3
#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PD)
#define GPIO_5_IRQ EXTI4_IRQn
/* GPIO channel 6 config */
#define GPIO_6_PORT GPIOD /* LD8 */
#define GPIO_6_PIN 5
#define GPIO_6_CLK 3
#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PD)
#define GPIO_6_IRQ EXTI9_5_IRQn
/* GPIO channel 7 config */
#define GPIO_7_PORT GPIOD
#define GPIO_7_PIN 6
#define GPIO_7_CLK 3
#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PD)
#define GPIO_7_IRQ EXTI9_5_IRQn
/* GPIO channel 8 config */
#define GPIO_8_PORT GPIOD
#define GPIO_8_PIN 7
#define GPIO_8_CLK 3
#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PD)
#define GPIO_8_IRQ EXTI9_5_IRQn
/* GPIO channel 9 config */
#define GPIO_9_PORT GPIOA
#define GPIO_9_PIN 8
#define GPIO_9_CLK 0
#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PA)
#define GPIO_9_IRQ EXTI9_5_IRQn
/* GPIO channel 10 config */
#define GPIO_10_PORT GPIOA /* LD7 */
#define GPIO_10_PIN 9
#define GPIO_10_CLK 0
#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PA)
#define GPIO_10_IRQ EXTI9_5_IRQn
/* GPIO channel 11 config */
#define GPIO_11_PORT GPIOD
#define GPIO_11_PIN 10
#define GPIO_11_CLK 3
#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PD)
#define GPIO_11_IRQ EXTI15_10_IRQn
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __PERIPH_CONF_H */
/** @} */

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!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/
!_TAG_PROGRAM_NAME Exuberant Ctags //
!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/
!_TAG_PROGRAM_VERSION 5.9~svn20110310 //
ADC_0_CH0 include/periph_conf.h 119;" d
ADC_0_CH0_PIN include/periph_conf.h 120;" d
ADC_0_CH1 include/periph_conf.h 122;" d
ADC_0_CH1_PIN include/periph_conf.h 123;" d
ADC_0_CHANNELS include/periph_conf.h 113;" d
ADC_0_CLKDIS include/periph_conf.h 115;" d
ADC_0_CLKEN include/periph_conf.h 114;" d
ADC_0_DEV include/periph_conf.h 112;" d
ADC_0_EN include/periph_conf.h 107;" d
ADC_0_PORT include/periph_conf.h 116;" d
ADC_0_PORT_CLKEN include/periph_conf.h 117;" d
ADC_1_CH0 include/periph_conf.h 134;" d
ADC_1_CH0_PIN include/periph_conf.h 135;" d
ADC_1_CH1 include/periph_conf.h 137;" d
ADC_1_CH1_PIN include/periph_conf.h 138;" d
ADC_1_CHANNELS include/periph_conf.h 127;" d
ADC_1_CLKDIS include/periph_conf.h 129;" d
ADC_1_CLKEN include/periph_conf.h 128;" d
ADC_1_DEV include/periph_conf.h 126;" d
ADC_1_EN include/periph_conf.h 108;" d
ADC_1_PORT include/periph_conf.h 131;" d
ADC_1_PORT_CLKEN include/periph_conf.h 132;" d
ADC_MAX_CHANNELS include/periph_conf.h 109;" d
ADC_NUMOF include/periph_conf.h 106;" d
CLK16 include/board.h 39;" d
CLK40 include/board.h 38;" d
CLK50 include/board.h 37;" d
CLK80 include/board.h 36;" d
DAC_0_CH0_PIN include/periph_conf.h 159;" d
DAC_0_CH1_PIN include/periph_conf.h 160;" d
DAC_0_CHANNELS include/periph_conf.h 153;" d
DAC_0_CLKDIS include/periph_conf.h 155;" d
DAC_0_CLKEN include/periph_conf.h 154;" d
DAC_0_DEV include/periph_conf.h 152;" d
DAC_0_EN include/periph_conf.h 148;" d
DAC_0_PORT include/periph_conf.h 156;" d
DAC_0_PORT_CLKEN include/periph_conf.h 157;" d
DAC_MAX_CHANNELS include/periph_conf.h 149;" d
DAC_NUMOF include/periph_conf.h 147;" d
F_CPU include/board.h 35;" d
GPIO_0_CLK include/periph_conf.h 329;" d
GPIO_0_EN include/periph_conf.h 294;" d
GPIO_0_EXTI_CFG include/periph_conf.h 330;" d
GPIO_0_IRQ include/periph_conf.h 331;" d
GPIO_0_PIN include/periph_conf.h 328;" d
GPIO_0_PORT include/periph_conf.h 327;" d
GPIO_10_CLK include/periph_conf.h 389;" d
GPIO_10_EN include/periph_conf.h 304;" d
GPIO_10_EXTI_CFG include/periph_conf.h 390;" d
GPIO_10_IRQ include/periph_conf.h 391;" d
GPIO_10_PIN include/periph_conf.h 388;" d
GPIO_10_PORT include/periph_conf.h 387;" d
GPIO_11_CLK include/periph_conf.h 395;" d
GPIO_11_EN include/periph_conf.h 305;" d
GPIO_11_EXTI_CFG include/periph_conf.h 396;" d
GPIO_11_IRQ include/periph_conf.h 397;" d
GPIO_11_PIN include/periph_conf.h 394;" d
GPIO_11_PORT include/periph_conf.h 393;" d
GPIO_1_CLK include/periph_conf.h 335;" d
GPIO_1_EN include/periph_conf.h 295;" d
GPIO_1_EXTI_CFG include/periph_conf.h 336;" d
GPIO_1_IRQ include/periph_conf.h 337;" d
GPIO_1_PIN include/periph_conf.h 334;" d
GPIO_1_PORT include/periph_conf.h 333;" d
GPIO_2_CLK include/periph_conf.h 341;" d
GPIO_2_EN include/periph_conf.h 296;" d
GPIO_2_EXTI_CFG include/periph_conf.h 342;" d
GPIO_2_IRQ include/periph_conf.h 343;" d
GPIO_2_PIN include/periph_conf.h 340;" d
GPIO_2_PORT include/periph_conf.h 339;" d
GPIO_3_CLK include/periph_conf.h 347;" d
GPIO_3_EN include/periph_conf.h 297;" d
GPIO_3_EXTI_CFG include/periph_conf.h 348;" d
GPIO_3_IRQ include/periph_conf.h 349;" d
GPIO_3_PIN include/periph_conf.h 346;" d
GPIO_3_PORT include/periph_conf.h 345;" d
GPIO_4_CLK include/periph_conf.h 353;" d
GPIO_4_EN include/periph_conf.h 298;" d
GPIO_4_EXTI_CFG include/periph_conf.h 354;" d
GPIO_4_IRQ include/periph_conf.h 355;" d
GPIO_4_PIN include/periph_conf.h 352;" d
GPIO_4_PORT include/periph_conf.h 351;" d
GPIO_5_CLK include/periph_conf.h 359;" d
GPIO_5_EN include/periph_conf.h 299;" d
GPIO_5_EXTI_CFG include/periph_conf.h 360;" d
GPIO_5_IRQ include/periph_conf.h 361;" d
GPIO_5_PIN include/periph_conf.h 358;" d
GPIO_5_PORT include/periph_conf.h 357;" d
GPIO_6_CLK include/periph_conf.h 365;" d
GPIO_6_EN include/periph_conf.h 300;" d
GPIO_6_EXTI_CFG include/periph_conf.h 366;" d
GPIO_6_IRQ include/periph_conf.h 367;" d
GPIO_6_PIN include/periph_conf.h 364;" d
GPIO_6_PORT include/periph_conf.h 363;" d
GPIO_7_CLK include/periph_conf.h 371;" d
GPIO_7_EN include/periph_conf.h 301;" d
GPIO_7_EXTI_CFG include/periph_conf.h 372;" d
GPIO_7_IRQ include/periph_conf.h 373;" d
GPIO_7_PIN include/periph_conf.h 370;" d
GPIO_7_PORT include/periph_conf.h 369;" d
GPIO_8_CLK include/periph_conf.h 377;" d
GPIO_8_EN include/periph_conf.h 302;" d
GPIO_8_EXTI_CFG include/periph_conf.h 378;" d
GPIO_8_IRQ include/periph_conf.h 379;" d
GPIO_8_PIN include/periph_conf.h 376;" d
GPIO_8_PORT include/periph_conf.h 375;" d
GPIO_9_CLK include/periph_conf.h 383;" d
GPIO_9_EN include/periph_conf.h 303;" d
GPIO_9_EXTI_CFG include/periph_conf.h 384;" d
GPIO_9_IRQ include/periph_conf.h 385;" d
GPIO_9_PIN include/periph_conf.h 382;" d
GPIO_9_PORT include/periph_conf.h 381;" d
GPIO_IRQ_0 include/periph_conf.h 309;" d
GPIO_IRQ_1 include/periph_conf.h 310;" d
GPIO_IRQ_10 include/periph_conf.h 319;" d
GPIO_IRQ_11 include/periph_conf.h 320;" d
GPIO_IRQ_12 include/periph_conf.h 321;" d
GPIO_IRQ_13 include/periph_conf.h 322;" d
GPIO_IRQ_14 include/periph_conf.h 323;" d
GPIO_IRQ_15 include/periph_conf.h 324;" d
GPIO_IRQ_2 include/periph_conf.h 311;" d
GPIO_IRQ_3 include/periph_conf.h 312;" d
GPIO_IRQ_4 include/periph_conf.h 313;" d
GPIO_IRQ_5 include/periph_conf.h 314;" d
GPIO_IRQ_6 include/periph_conf.h 315;" d
GPIO_IRQ_7 include/periph_conf.h 316;" d
GPIO_IRQ_8 include/periph_conf.h 317;" d
GPIO_IRQ_9 include/periph_conf.h 318;" d
GPIO_IRQ_PRIO include/periph_conf.h 306;" d
GPIO_NUMOF include/periph_conf.h 293;" d
HW_TIMER include/board.h 53;" d
I2C_0_CLKDIS include/periph_conf.h 273;" d
I2C_0_CLKEN include/periph_conf.h 272;" d
I2C_0_DEV include/periph_conf.h 271;" d
I2C_0_EN include/periph_conf.h 266;" d
I2C_0_ERR_IRQ include/periph_conf.h 276;" d
I2C_0_ERR_ISR include/periph_conf.h 277;" d
I2C_0_EVT_IRQ include/periph_conf.h 274;" d
I2C_0_EVT_ISR include/periph_conf.h 275;" d
I2C_0_SCL_AF include/periph_conf.h 281;" d
I2C_0_SCL_CLKEN include/periph_conf.h 282;" d
I2C_0_SCL_PIN include/periph_conf.h 280;" d
I2C_0_SCL_PORT include/periph_conf.h 279;" d
I2C_0_SDA_AF include/periph_conf.h 285;" d
I2C_0_SDA_CLKEN include/periph_conf.h 286;" d
I2C_0_SDA_PIN include/periph_conf.h 284;" d
I2C_0_SDA_PORT include/periph_conf.h 283;" d
I2C_APBCLK include/periph_conf.h 268;" d
I2C_IRQ_PRIO include/periph_conf.h 267;" d
I2C_NUMOF include/periph_conf.h 265;" d
LED_BLUE_OFF include/board.h 68;" d
LED_BLUE_ON include/board.h 67;" d
LED_BLUE_PIN include/board.h 60;" d
LED_BLUE_TOGGLE include/board.h 69;" d
LED_GREEN_OFF include/board.h 64;" d
LED_GREEN_ON include/board.h 63;" d
LED_GREEN_PIN include/board.h 59;" d
LED_GREEN_TOGGLE include/board.h 65;" d
LED_RED_OFF include/board.h 72;" d
LED_RED_ON include/board.h 71;" d
LED_RED_PIN include/board.h 61;" d
LED_RED_TOGGLE include/board.h 73;" d
MODULE Makefile /^MODULE = $(BOARD)_base$/;" m
PWM_0_CHANNELS include/periph_conf.h 173;" d
PWM_0_CLK include/periph_conf.h 174;" d
PWM_0_CLKDIS include/periph_conf.h 176;" d
PWM_0_CLKEN include/periph_conf.h 175;" d
PWM_0_DEV include/periph_conf.h 172;" d
PWM_0_EN include/periph_conf.h 167;" d
PWM_0_PIN_AF include/periph_conf.h 184;" d
PWM_0_PIN_CH0 include/periph_conf.h 180;" d
PWM_0_PIN_CH1 include/periph_conf.h 181;" d
PWM_0_PIN_CH2 include/periph_conf.h 182;" d
PWM_0_PIN_CH3 include/periph_conf.h 183;" d
PWM_0_PORT include/periph_conf.h 178;" d
PWM_0_PORT_CLKEN include/periph_conf.h 179;" d
PWM_1_CHANNELS include/periph_conf.h 188;" d
PWM_1_CLK include/periph_conf.h 189;" d
PWM_1_CLKDIS include/periph_conf.h 191;" d
PWM_1_CLKEN include/periph_conf.h 190;" d
PWM_1_DEV include/periph_conf.h 187;" d
PWM_1_EN include/periph_conf.h 168;" d
PWM_1_PIN_AF include/periph_conf.h 199;" d
PWM_1_PIN_CH0 include/periph_conf.h 195;" d
PWM_1_PIN_CH1 include/periph_conf.h 196;" d
PWM_1_PIN_CH2 include/periph_conf.h 197;" d
PWM_1_PIN_CH3 include/periph_conf.h 198;" d
PWM_1_PORT include/periph_conf.h 193;" d
PWM_1_PORT_CLKEN include/periph_conf.h 194;" d
PWM_MAX_CHANNELS include/periph_conf.h 169;" d
PWM_NUMOF include/periph_conf.h 166;" d
RANDOM_NUMOF include/periph_conf.h 206;" d
SPI_0_BUS_DIV include/periph_conf.h 222;" d
SPI_0_CLKDIS include/periph_conf.h 221;" d
SPI_0_CLKEN include/periph_conf.h 220;" d
SPI_0_DEV include/periph_conf.h 219;" d
SPI_0_EN include/periph_conf.h 214;" d
SPI_0_IRQ include/periph_conf.h 223;" d
SPI_0_IRQ_HANDLER include/periph_conf.h 224;" d
SPI_0_MISO_AF include/periph_conf.h 232;" d
SPI_0_MISO_PIN include/periph_conf.h 231;" d
SPI_0_MISO_PORT include/periph_conf.h 230;" d
SPI_0_MISO_PORT_CLKEN include/periph_conf.h 233;" d
SPI_0_MOSI_AF include/periph_conf.h 236;" d
SPI_0_MOSI_PIN include/periph_conf.h 235;" d
SPI_0_MOSI_PORT include/periph_conf.h 234;" d
SPI_0_MOSI_PORT_CLKEN include/periph_conf.h 237;" d
SPI_0_SCK_AF include/periph_conf.h 228;" d
SPI_0_SCK_PIN include/periph_conf.h 227;" d
SPI_0_SCK_PORT include/periph_conf.h 226;" d
SPI_0_SCK_PORT_CLKEN include/periph_conf.h 229;" d
SPI_1_BUS_DIV include/periph_conf.h 243;" d
SPI_1_CLKDIS include/periph_conf.h 242;" d
SPI_1_CLKEN include/periph_conf.h 241;" d
SPI_1_DEV include/periph_conf.h 240;" d
SPI_1_EN include/periph_conf.h 215;" d
SPI_1_IRQ include/periph_conf.h 244;" d
SPI_1_IRQ_HANDLER include/periph_conf.h 245;" d
SPI_1_MISO_AF include/periph_conf.h 253;" d
SPI_1_MISO_PIN include/periph_conf.h 252;" d
SPI_1_MISO_PORT include/periph_conf.h 251;" d
SPI_1_MISO_PORT_CLKEN include/periph_conf.h 254;" d
SPI_1_MOSI_AF include/periph_conf.h 257;" d
SPI_1_MOSI_PIN include/periph_conf.h 256;" d
SPI_1_MOSI_PORT include/periph_conf.h 255;" d
SPI_1_MOSI_PORT_CLKEN include/periph_conf.h 258;" d
SPI_1_SCK_AF include/periph_conf.h 249;" d
SPI_1_SCK_PIN include/periph_conf.h 248;" d
SPI_1_SCK_PORT include/periph_conf.h 247;" d
SPI_1_SCK_PORT_CLKEN include/periph_conf.h 250;" d
SPI_IRQ_PRIO include/periph_conf.h 216;" d
SPI_NUMOF include/periph_conf.h 213;" d
STDIO include/board.h 45;" d
STDIO_BAUDRATE include/board.h 46;" d
STDIO_RX_BUFSIZE include/board.h 47;" d
SetupClock board.c /^void SetupClock(int clk)$/;" f
SetupFPU board.c /^void SetupFPU(void)$/;" f
TIMER_0_CHANNELS include/periph_conf.h 43;" d
TIMER_0_CLKEN include/periph_conf.h 46;" d
TIMER_0_DEV include/periph_conf.h 42;" d
TIMER_0_EN include/periph_conf.h 37;" d
TIMER_0_IRQ_CHAN include/periph_conf.h 48;" d
TIMER_0_ISR include/periph_conf.h 47;" d
TIMER_0_MAX_VALUE include/periph_conf.h 45;" d
TIMER_0_PRESCALER include/periph_conf.h 44;" d
TIMER_1_CHANNELS include/periph_conf.h 52;" d
TIMER_1_CLKEN include/periph_conf.h 55;" d
TIMER_1_DEV include/periph_conf.h 51;" d
TIMER_1_EN include/periph_conf.h 38;" d
TIMER_1_IRQ_CHAN include/periph_conf.h 57;" d
TIMER_1_ISR include/periph_conf.h 56;" d
TIMER_1_MAX_VALUE include/periph_conf.h 54;" d
TIMER_1_PRESCALER include/periph_conf.h 53;" d
TIMER_IRQ_PRIO include/periph_conf.h 39;" d
TIMER_NUMOF include/periph_conf.h 36;" d
TRACE include/board.h 75;" d
UART_0_AF include/periph_conf.h 83;" d
UART_0_CLK include/periph_conf.h 75;" d
UART_0_CLKDIS include/periph_conf.h 74;" d
UART_0_CLKEN include/periph_conf.h 73;" d
UART_0_DEV include/periph_conf.h 72;" d
UART_0_EN include/periph_conf.h 67;" d
UART_0_IRQ_CHAN include/periph_conf.h 76;" d
UART_0_ISR include/periph_conf.h 77;" d
UART_0_PORT include/periph_conf.h 80;" d
UART_0_PORT_CLKEN include/periph_conf.h 79;" d
UART_0_RX_PIN include/periph_conf.h 82;" d
UART_0_TX_PIN include/periph_conf.h 81;" d
UART_1_AF include/periph_conf.h 99;" d
UART_1_CLK include/periph_conf.h 91;" d
UART_1_CLKDIS include/periph_conf.h 90;" d
UART_1_CLKEN include/periph_conf.h 89;" d
UART_1_DEV include/periph_conf.h 88;" d
UART_1_EN include/periph_conf.h 68;" d
UART_1_IRQ_CHAN include/periph_conf.h 92;" d
UART_1_ISR include/periph_conf.h 93;" d
UART_1_PORT include/periph_conf.h 96;" d
UART_1_PORT_CLKEN include/periph_conf.h 95;" d
UART_1_RX_PIN include/periph_conf.h 98;" d
UART_1_TX_PIN include/periph_conf.h 97;" d
UART_CLK include/periph_conf.h 70;" d
UART_IRQ_PRIO include/periph_conf.h 69;" d
UART_NUMOF include/periph_conf.h 66;" d
VAL_I include/board.h 76;" d
VAL_S include/board.h 78;" d
VAL_X include/board.h 77;" d
__BOARD_H include/board.h 22;" d
__PERIPH_CONF_H include/periph_conf.h 20;" d
board_init board.c /^void board_init(void)$/;" f

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cpu/lm4f120/1 Normal file
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cpu/lm4f120/Makefile Normal file
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# define the module that is build
MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(RIOTCPU)/cortexm_common
include $(RIOTBASE)/Makefile.base

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cpu/lm4f120/Makefile.include Normal file
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export CPU_ARCH = cortex-m4f
# use hwtimer compatibility module
USEMODULE += hwtimer_compat
include $(RIOTCPU)/Makefile.include.cortexm_common

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cpu/lm4f120/cpu.c Normal file
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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Implementation of the CPU initialization
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
* @}
*/
#include "cpu.h"
#include "irq.h"
#include "kernel.h"
#include "kernel_internal.h"
#include "sched.h"
#include "thread.h"
#include "arch/thread_arch.h"
#include "arch/irq_arch.h"
unsigned long __attribute__((naked))
CPUipsrGet(void)
{
unsigned long ulRet;
//
// Read IPSR
//
__asm(" mrs r0, IPSR\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
void __attribute__((naked))
DisableInterrupts(void)
{
__asm(" CPSID I\n"
" BX LR\n");
}
void __attribute__((naked))
EnableInterrupts(void)
{
__asm(" CPSIE I\n"
" BX LR\n");
}
/**
* @brief Initialize the CPU, set IRQ priorities
*/
void cpu_init(void)
{
// initializes the Cortex-M core
cortexm_init();
/* initialize the clock system */
cpu_clock_init(CLK40);
}
void setup_fpu(void)
{
ROM_FPUEnable();
ROM_FPULazyStackingEnable();
}
void cpu_clock_init(int clk)
{
setup_fpu();
switch(clk){
case CLK80:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK50:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK40:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK16:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
case CLK1:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_1MHZ | SYSCTL_OSC_MAIN);
break;
default:
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
break;
}
}

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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_lm4f120
* @ingroup cpu
* @brief CPU specific implementations for the Stellaris Launchpad LM4F120 board
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*12
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef __CPU_CONF_H
#define __CPU_CONF_H
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_nvic.h"
#include "hw_sysctl.h"
#include "hw_types.h"
#include "lm4f120h5qr.h"
#include "cortex-m4-def.h"
#include "stellaris_periph/cpu.h"
#include "stellaris_periph/debug.h"
#include "stellaris_periph/interrupt.h"
#include "stellaris_periph/sysctl.h"
#include "stellaris_periph/adc.h"
#include "stellaris_periph/gpio.h"
#include "stellaris_periph/timer.h"
#include "stellaris_periph/pin_map.h"
#include "stellaris_periph/uart.h"
#include "stellaris_periph/fpu.h"
#include "stellaris_periph/rom.h"
#include "hwtimer_cpu.h"
#include "periph/uart.h"
#include "stdio.h"
#include "stdlib.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ARM Cortex-M specific CPU configuration
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF (48U)
#define CPU_FLASH_BASE FLASH_BASE
/** @} */
/**
* @brief Length for reading CPU_ID
*/
#define CPUID_ID_LEN (12)
#define CPUID_ADDR NVIC_CPUID
/**
* @name CC110X buffer size definitions for the stm32f4
* @{
*/
#ifdef MODULE_CC110X
#define TRANSCEIVER_BUFFER_SIZE (10)
#define RX_BUF_SIZE (10)
#endif
/**
* @name Define the nominal CPU core clock in this board
*/
#define F_CPU 1000000
#define CLK80 1
#define CLK50 2
#define CLK40 3
#define CLK16 4
#define CLK1 5
extern unsigned long CPUipsrGet(void);
extern void DisableInterrupts(void);
extern void EnableInterrupts(void);
extern void setup_fpu(void);
extern void cpu_clock_init(int);
extern int uart_init_testing(uart_t uart, uint32_t baudrate);
extern void UARTSend(const unsigned char *pucBuffer, unsigned long ulCount);
#ifdef __cplusplus
}
#endif
#endif /* __CPU_CONF_H */
/** @} */

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cpu/lm4f120/include/hwtimer_cpu.h Normal file
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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 4 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS 0xffffffff /**< 32-bit timer */
#define HWTIMER_MSEC (HWTIMER_SPEED/1000)
#define HWTIMER_SEC (HWTIMER_SPEED/1000000)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

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cpu/lm4f120/include/lm4f120h5qr.h Normal file
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/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __LM4F120H5QR_H__
#define __LM4F120H5QR_H__
#ifdef __cplusplus
extern "C" {
#endif
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< LM4F120H5QR provides an MPU */
#define __NVIC_PRIO_BITS 3 /*!< LM4F120H5QR uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
/**
* @}
*/
/** @addtogroup cpu_specific_Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief LM4F120H5QR Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** LM4F specific Interrupt Numbers **********************************************************************/
GPIOPortA_IRQn = 0,
GPIOPortB_IRQn = 1,
GPIOPortC_IRQn = 2,
GPIOPortD_IRQn = 3,
GPIOPortE_IRQn = 4,
UART0_IRQn = 5,
UART1_IRQn = 6,
SSI0_IRQn = 7,
I2C0_IRQn = 8,
PWMFault_IRQn = 9,
PWM0_IRQn = 10,
PWM1_IRQn = 11,
PWM2_IRQn = 12,
Quadrature0_IRQn = 13,
ADC0_IRQn = 14,
ADC1_IRQn = 15,
ADC2_IRQn = 16,
ADC3_IRQn = 17,
WDT_IRQn = 18,
Timer0A_IRQn = 19,
Timer0B_IRQn = 20,
Timer1A_IRQn = 21,
Timer1B_IRQn = 22,
Timer2A_IRQn = 23,
Timer2B_IRQn = 24,
Comp0_IRQn = 25,
Comp1_IRQn = 26,
Comp2_IRQn = 27,
SysCtl_IRQn = 28,
FlashCtl_IRQn = 29,
GPIOPortF_IRQn = 30,
GPIOPortG_IRQn = 31,
GPIOPortH_IRQn = 32,
UART2_IRQn = 33,
SSI1_IRQn = 34,
Timer3A_IRQn = 35,
Timer3B_IRQn = 36,
I2C1_IRQn = 37,
Quadrature1_IRQn = 38,
CAN0_IRQn = 39,
CAN1_IRQn = 40,
CAN2_IRQn = 41,
Ethernet_IRQn = 42,
Hibernate_IRQn = 43,
USB0_IRQn = 44,
PWM3_IRQn = 45,
uDMA_IRQn = 46,
uDMA_Error_IRQn = 47,
} IRQn_Type;
/*
typedef enum
{
// ****** Cortex-M4 Processor Exceptions Numbers ****************************************************************
NonMaskableInt_IRQn = 2, //!< 2 Non Maskable Interrupt
MemoryManagement_IRQn = 4, //!< 4 Cortex-M4 Memory Management Interrupt
BusFault_IRQn = 5, //!< 5 Cortex-M4 Bus Fault Interrupt
UsageFault_IRQn = 6, //!< 6 Cortex-M4 Usage Fault Interrupt
SVCall_IRQn = 11, //!< 11 Cortex-M4 SV Call Interrupt
DebugMonitor_IRQn = 12, //!< 12 Cortex-M4 Debug Monitor Interrupt
PendSV_IRQn = 14, //!< 14 Cortex-M4 Pend SV Interrupt
SysTick_IRQn = 15, //!< 15 Cortex-M4 System Tick Interrupt
} IRQn_Type;
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include <stdint.h> /* standard types definitions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM4_H_GENERIC */

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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file lm4f120_linkerscript.ld
* @brief Linker description file for LM4FXXX microcontrollers.
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
}
INCLUDE cortexm_base.ld

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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Implementation of the kernels power management interface
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*
* @}
*/
#include "cpu.h"
#include "arch/lpm_arch.h"
void lpm_arch_init(void)
{
/* TODO */
}
enum lpm_mode lpm_arch_set(enum lpm_mode target)
{
/* TODO */
return 0;
}
enum lpm_mode lpm_arch_get(void)
{
/* TODO */
return 0;
}
void lpm_arch_awake(void)
{
/* TODO*/
}
void lpm_arch_begin_awake(void)
{
/* TODO */
}
void lpm_arch_end_awake(void)
{
/* TODO */
}

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MODULE = periph
include $(RIOTBASE)/Makefile.base

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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Low-level ADC driver implementation
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*
* @}
*/
#include "cpu.h"
#include "periph/adc.h"
#include "periph_conf.h"
/* guard in case that no ADC device is defined */
#if ADC_NUMOF
typedef struct {
int max_value;
} adc_config_t;
adc_config_t adc_config[ADC_NUMOF];
int adc_init(adc_t dev, adc_precision_t precision)
{
adc_poweron(dev);
// ADC0 is used with AIN0 on port E3.
// ADC1 is used with AIN1 on port E2.
// GPIO port E needs to be enabled so that these pinds can be used
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
// Set the ADC to 125KSPS.
// This requires less power and produce longer samping time,
// creating accurate conversions
ROM_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_125KSPS);
switch (precision) {
case ADC_RES_6BIT:
case ADC_RES_8BIT:
case ADC_RES_10BIT:
#if ADC_0_EN
ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_10BIT_S);
#endif
#if ADC_1_EN
ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_10BIT_S);
#endif
adc_config[dev].max_value = 0x3ff;
break;
case ADC_RES_12BIT:
#if ADC_0_EN
ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_12BIT_S);
#endif
#if ADC_1_EN
ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_12BIT_S);
#endif
adc_config[dev].max_value = 0xfff;
break;
case ADC_RES_14BIT:
case ADC_RES_16BIT:
break;
}
switch (dev) {
#if ADC_0_EN
case ADC_0:
// Select the Analog ADC Function for these pins.
ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);
// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
ROM_ADCSequenceDisable(ADC0_BASE, 3);
// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
// Configure step 0 on sequence 3.
// Sample channel 0 (ADC_CTL_CH0) in single-ended mode and configure the interrupt flag.
// (ADC_CTL_IE) to be set to enable Interrupt.
ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0,
ADC_CTL_CH0 | ADC_CTL_IE | ADC_CTL_END);
// Clear the interrupt status flag. This is done to make sure
// the interrupt flag is cleared before we sample.
ROM_ADCIntClear(ADC0_BASE, 3);
// Since sample sequence 3 is now configured, it must be enabled.
ROM_ADCSequenceEnable(ADC0_BASE, 3);
break;
#endif
#if ADC_1_EN
case ADC_1:
// Select the Analog ADC Function for these pins.
ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2);
// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
ROM_ADCSequenceDisable(ADC1_BASE, 3);
// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
ROM_ADCSequenceConfigure(ADC1_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
// Configure step 0 on sequence 3.
// Sample channel 0 (ADC_CTL_CH1) in single-ended mode and configure the interrupt flag.
// (ADC_CTL_IE) to be set to enable Interrupt.
ROM_ADCSequenceStepConfigure(ADC1_BASE, 3, 0,
ADC_CTL_CH1 | ADC_CTL_IE | ADC_CTL_END);
// Clear the interrupt status flag. This is done to make sure
// the interrupt flag is cleared before we sample.
ROM_ADCIntClear(ADC1_BASE, 3);
// Since sample sequence 3 is now configured, it must be enabled.
ROM_ADCSequenceEnable(ADC1_BASE, 3);
break;
#endif
default:
return -1;
}
return 0;
}
int adc_sample(adc_t dev, int channel)
{
unsigned long ulADC_val=0;
switch (dev) {
#if ADC_0_EN
case ADC_0:
// Trigger the ADC conversion
ROM_ADCProcessorTrigger(ADC0_BASE, 3);
// Wait for conversion to be completed.
while(!ROM_ADCIntStatus(ADC0_BASE, 3, false));
// Read ADC value.
ROM_ADCSequenceDataGet(ADC0_BASE, 3, &ulADC_val);
// Clear the ADC interrupt flag
ROM_ADCIntClear(ADC0_BASE, 3);
break;
#endif
#if ADC_1_EN
case ADC_1:
// Trigger the ADC conversion
ROM_ADCProcessorTrigger(ADC1_BASE, 3);
// Wait for conversion to be completed.
while(!ROM_ADCIntStatus(ADC1_BASE, 3, false));
// Read ADC value.
ROM_ADCSequenceDataGet(ADC1_BASE, 3, &ulADC_val);
// Clear the ADC interrupt flag
ROM_ADCIntClear(ADC1_BASE, 3);
break;
#endif
default:
return -1;
}
/* return result */
return ((int)ulADC_val);
}
void adc_poweron(adc_t dev)
{
switch (dev) {
#if ADC_0_EN
case ADC_0:
// The ADC0 Peripheral must be enabled for use
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
break;
#endif
#if ADC_1_EN
case ADC_1:
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
break;
#endif
}
}
void adc_poweroff(adc_t dev)
{
switch (dev) {
#if ADC_0_EN
case ADC_0:
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
break;
#endif
#if ADC_1_EN
case ADC_1:
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
break;
#endif
}
}
int adc_map(adc_t dev, int value, int min, int max)
{
return (int)adc_mapf(dev, value, (float)min, (float)max);
}
float adc_mapf(adc_t dev, int value, float min, float max)
{
return ((max - min) / ((float)adc_config[dev].max_value)) * value;
}
#endif /* ADC_NUMOF */

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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup driver_periph
* @{
*
* @file
* @brief Low-level CPUID driver implementation
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#include <string.h>
#include "cpu_conf.h"
#include "periph/cpuid.h"
void cpuid_get(void *id)
{
memcpy(id, (void *)(CPUID_ADDR), CPUID_ID_LEN);
}
/** @} */

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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Implementation of the low-level timer driver for the LM4F120
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
* @}
*/
#include <stdint.h>
#include "cpu.h"
#include "sched.h"
#include "thread.h"
#include "periph_conf.h"
#include "periph/timer.h"
/* guard file in case no timers are defined */
#if TIMER_0_EN
/**
* @brief Struct holding the configuration data
*/
typedef struct {
void (*cb)(int); /**< timeout callback */
} timer_conf_t;
static timer_conf_t config[TIMER_NUMOF];
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
{
if (dev == TIMER_0) {
config[dev].cb = callback; // User Function
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); //Activate Timer0
WTIMER0_CTL_R &= ~0x00000001; // Disable timer0A during setup
WTIMER0_CFG_R = TIMER_CFG_16_BIT;
WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // | TIMER_TAMR_TACDIR); // Configure for periodic mode
WTIMER0_TAPR_R = 39; // 1us timer0A
WTIMER0_ICR_R = 0x00000001; // clear timer0A timeout flag
WTIMER0_IMR_R |= 0x00000001; // arm timeout interrupt
// NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
ROM_IntPrioritySet(INT_WTIMER0A, 32);
ROM_IntEnable(INT_WTIMER0A);
ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT);
// timer_irq_enable(dev);
timer_start(dev);
DEBUG("startTimeout Value=%lu\n", ROM_TimerValueGet(WTIMER0_BASE, TIMER_A));
return 1;
}
return -1;
}
int timer_set(tim_t dev, int channel, unsigned int timeout)
{
if (dev == TIMER_0) {
unsigned int now = timer_read(dev);
DEBUG("timer_set now=%u\n",now);
DEBUG("timer_set timeout=%u\n", timeout);
return timer_set_absolute(dev, channel, HWTIMER_MAXTICKS-1-now+timeout);
}
return -1;
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
if (dev == TIMER_0) {
WTIMER0_TAILR_R = 0x00000000 | value; // period; Reload value
DEBUG("Setting timer absolute value=%u\n", value);
return 1;
}
return -1;
}
int timer_clear(tim_t dev, int channel)
{
if (dev == TIMER_0){
WTIMER0_TAILR_R = 0x00000000; // period; Reload value
return 1;
}
return -1;
}
unsigned int timer_read(tim_t dev)
{
if (dev == TIMER_0) {
unsigned int currTimer0Val=0;
currTimer0Val = (unsigned int)ROM_TimerValueGet(WTIMER0_BASE, TIMER_A);
return (HWTIMER_MAXTICKS - currTimer0Val);
}
return 0;
}
void timer_start(tim_t dev)
{
if (dev == TIMER_0) {
DEBUG("Starting the timer\n");
ROM_TimerEnable(WTIMER0_BASE, TIMER_A);
}
}
void timer_stop(tim_t dev)
{
if (dev == TIMER_0) {
ROM_TimerDisable(WTIMER0_BASE, TIMER_A);
}
}
void timer_irq_enable(tim_t dev)
{
if (dev == TIMER_0) {
DEBUG("Enabling Timer Interrupts\n");
ROM_IntEnable(INT_WTIMER0A);
ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT);
}
}
void timer_irq_disable(tim_t dev)
{
if (dev == TIMER_0) {
DEBUG("Disabling Timer Interrupts\n");
ROM_IntDisable(INT_WTIMER0A);
}
}
void timer_reset(tim_t dev)
{
if (dev == TIMER_0) {
// Performs a software reset of a peripheral
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_WTIMER0);
}
}
#if TIMER_0_EN
void TIMER0IntHandler(void)
{
TIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
config[TIMER_0].cb(0);
if (sched_context_switch_request){
thread_yield();
}
}
void WTIMER0IntHandler(void)
{
WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
config[TIMER_0].cb(0);
if (sched_context_switch_request){
thread_yield();
}
}
#endif
#endif /* TIMER_0_EN */

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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Implementation of the low-level UART driver for the LM4F120
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
* @}
*/
#include <stdint.h>
#include "cpu.h"
#include "sched.h"
#include "thread.h"
#include "periph/uart.h"
#include "periph_conf.h"
/* guard the file in case no UART is defined */
#if (UART_0_EN)
/**
* @brief Struct holding the configuration data for a UART device
*/
typedef struct {
uart_rx_cb_t rx_cb; /**< receive callback */
uart_tx_cb_t tx_cb; /**< transmit callback */
void *arg; /**< callback argument */
} uart_conf_t;
/**
* @brief Unified interrupt handler for all UART devices
*
* @param uartnum the number of the UART that triggered the ISR
* @param uart the UART device that triggered the ISR
*/
//static inline void irq_handler(uart_t uartnum, USART_TypeDef *uart);
/**
* @brief UART device configurations
*/
static uart_conf_t config[UART_NUMOF];
/**
* The list of UART peripherals.
*/
static const unsigned long g_ulUARTPeriph[3] =
{
SYSCTL_PERIPH_UART0,
SYSCTL_PERIPH_UART1,
SYSCTL_PERIPH_UART2
};
/**
* The list of all possible base address of the console UART
*/
static const unsigned long g_ulUARTBase[3] =
{
UART0_BASE,
UART1_BASE,
UART2_BASE
};
// The list of possible interrupts for the console UART.
//
//*****************************************************************************
static const unsigned long g_ulUARTInt[3] =
{
INT_UART0,
INT_UART1,
INT_UART2
};
int uart_init_testing(uart_t uart, uint32_t baudrate)
{
// Enable lazy stacking for interrupt handlers. This allows floating point instructions to be
// used within interrupt handers, but at the expense of extra stack usuage.
const unsigned long srcClock = ROM_SysCtlClockGet();
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
ROM_UARTDisable(UART0_BASE);
ROM_UARTConfigSetExpClk(UART0_BASE,srcClock, baudrate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
UART_CONFIG_WLEN_8));
//Enable the UART interrupt
ROM_UARTEnable(UART0_BASE);
// Prompt for text to be entered.
//
//UARTSend((unsigned char *)"\033[2JEnter text: ", 16);
//
// Loop forever echoing data through the UART.
//
printf("Passed Testing\n");
return 1;
}
void UARTSend(const unsigned char *pucBuffer, unsigned long ulCount)
{
//
// Loop while there are more characters to send.
//
while(ulCount--)
{
//
// Write the next character to the UART.
//
ROM_UARTCharPutNonBlocking(UART0_BASE, *pucBuffer++);
}
}
/**********************************************************************************/
/* Configuring the UART console
*/
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
{
// The base address of the Choosen UART
// unsigned long ulBase=0;
// Check the arguments
ASSERT(uart == 0);
// Check to make sure the UART peripheral is present
if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0))
{
return -1;
}
int res = uart_init_blocking(uart, baudrate);
if(res < 0){
return res;
}
/* save callbacks */
config[uart].rx_cb = rx_cb;
config[uart].tx_cb = tx_cb;
config[uart].arg = arg;
// Select the base address of the UART
// ulBase = g_ulUARTBase[uart];
// Configure the relevant UART pins for operations as a UART rather than GPIOs.
/* enable recieve interrupt */
switch (uart){
#if UART_0_EN
case UART_0:
NVIC_SetPriority(UART_0_IRQ_CHAN, UART_IRQ_PRIO);
// Enable the UART interrupt
NVIC_EnableIRQ(UART_0_IRQ_CHAN);
//ROM_UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
//ROM_IntEnable(INT_UART0);
break;
#endif
#if UART_1_EN
case UART_1:
NVIC_SetPriority(UART_1_IRQ_CHAN, UART_IRQ_PRIO);
// Enable the UART interrupt
NVIC_EnableIRQ(UART_1_IRQ_CHAN);
// ROM_UARTIntEnable(UART1_BASE, UART_INT_RX | UART_INT_RT);
// ROM_IntEnable(INT_UART1);
break;
#endif
}
return 0;
}
int uart_init_blocking(uart_t uart, uint32_t baudrate)
{
switch(uart){
#if UART_0_EN
case UART_0:
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
ROM_UARTDisable(UART0_BASE);
ROM_UARTConfigSetExpClk(UART0_BASE,ROM_SysCtlClockGet(), baudrate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
UART_CONFIG_WLEN_8));
ROM_UARTEnable(UART0_BASE);
break;
#endif
}
return 0;
}
void uart_tx_begin(uart_t uart)
{
// enable TX interrupt
ROM_UARTIntEnable(UART0_BASE, UART_INT_TX);
}
int uart_write(uart_t uart, char data)
{
ROM_UARTCharPutNonBlocking(UART0_BASE, data);
return 1;
}
int uart_read_blocking(uart_t uart, char *data)
{
*data = (char)ROM_UARTCharGet(UART0_BASE);
return 1;
}
int uart_write_blocking(uart_t uart, char data)
{
ROM_UARTCharPut(UART0_BASE, data);
return 1;
}
void uart_poweron(uart_t uart)
{
ROM_UARTEnable(UART0_BASE);
}
void uart_poweroff(uart_t uart)
{
ROM_UARTDisable(UART0_BASE);
}
//*****************************************************************************
//
// The UART interrupt handler.
//
//*****************************************************************************
void UARTIntHandler(void)
{
unsigned long ulStatus;
char cChar;
long lChar;
// Get the interrupt status
ulStatus = ROM_UARTIntStatus(UART0_BASE, true);
// Clear the asserted interrupts
ROM_UARTIntClear(UART0_BASE, ulStatus);
// Are we interrupted due to TX done
if(ulStatus & UART_INT_TX)
{
// Turn off the Transmit Interrupt
if (config[UART_0].tx_cb(config[UART_0].arg) == 0){
ROM_UARTIntDisable(UART0_BASE, UART_INT_TX);
}
}
// Are we interrupted due to a recieved character
if(ulStatus & (UART_INT_RX | UART_INT_RT))
{
// Get all the available characters from the UART
while(ROM_UARTCharsAvail(UART0_BASE))
{
// Read a character
lChar = ROM_UARTCharGetNonBlocking(UART0_BASE);
cChar = (unsigned char)(lChar & 0xFF);
config[UART_0].rx_cb(config[UART_0].arg, cChar);
}
}
if (sched_context_switch_request) {
thread_yield();
}
}
#endif /* (UART_0_EN || UART_1_EN) */

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/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file startup.c - Startup code
* @brief LM4F120H5QR startup code and interrupt vector definition.
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*
* @}
*/
#include <stdint.h>
#include "cpu.h"
/**
* memory markers as defined in the linker script
*/
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
//-----------------------------------------------------------------------------
// Functions declarations
//-----------------------------------------------------------------------------
void reset_handler(void);
static void NmiSR(void);
static void FaultISR(void);
extern void empty_def_handler(void);
extern void board_init(void);
extern void kernel_init(void);
extern void __libc_init_array(void);
/**
* Required by g++ cross compiler
*/
void *__dso_handle;
// External declaration for the interrupt handler used by the application
extern void UARTIntHandler(void); // UART 0 21
extern void UART1IntHandler(void); // UART 1 21
extern void TIMER0IntHandler(void); // 16 bit timer 0 A
extern void WTIMER0IntHandler(void); // 32 bit timer 0 A
extern void TIMER1IntHandler(void); // 16 bit timer 1 A
extern void isr_svc(void); // SV call
extern void isr_pendsv(void); // PendSV
extern void isr_bus_fault(void); // Bus Fault
extern void isr_usage_fault(void); // Usage Fault
/* interrupt vector table */
__attribute__ ((section(".vectors")))
const void *interrupt_vector[] = {
/* Stack pointer */
(void*) (&_estack), /* pointer to the top of the empty stack */
/* Cortex-M4 handlers */
(void*) reset_handler, /* entry point of the program */
NmiSR, // NMI handler. 2
FaultISR, // hard fault handler. 3
// Configurable priority interruts handler start here.
empty_def_handler, // Memory Management Fault 4
isr_bus_fault, // Bus Fault 5
isr_usage_fault, // Usage Fault 6
0, // Reserved 7
0, // Reserved 8
0, // Reserved 9
0, // Reserved 10
isr_svc, // SV call 11
empty_def_handler, // Debug monitor 12
0, // Reserved 13
isr_pendsv, // PendSV 14
empty_def_handler, // SysTick 15
// Peripherial interrupts start here.
empty_def_handler, // GPIO Port A 16
empty_def_handler, // GPIO Port B 17
empty_def_handler, // GPIO Port C 18
empty_def_handler, // GPIO Port D 19
empty_def_handler, // GPIO Port E 20
UARTIntHandler, // UART 0 21
UART1IntHandler, // UART 1 22
empty_def_handler, // SSI 0 23
empty_def_handler, // I2C 0 24
0, // Reserved 25
0, // Reserved 26
0, // Reserved 27
0, // Reserved 28
0, // Reserved 29
empty_def_handler, // ADC 0 Seq 0 30
empty_def_handler, // ADC 0 Seq 1 31
empty_def_handler, // ADC 0 Seq 2 32
empty_def_handler, // ADC 0 Seq 3 33
empty_def_handler, // WDT 0 and 1 34
TIMER0IntHandler, // 16/32 bit timer 0 A 35
empty_def_handler, // 16/32 bit timer 0 B 36
TIMER1IntHandler, // 16/32 bit timer 1 A 37
empty_def_handler, // 16/32 bit timer 1 B 38
empty_def_handler, // 16/32 bit timer 2 A 39
empty_def_handler, // 16/32 bit timer 2 B 40
empty_def_handler, // Analog comparator 0 41
empty_def_handler, // Analog comparator 1 42
0, // Reserved 43
empty_def_handler, // System control 44
empty_def_handler, // Flash + EEPROM control 45
empty_def_handler, // GPIO Port F 46
0, // Reserved 47
0, // Reserved 48
empty_def_handler, // UART 2 49
empty_def_handler, // SSI 1 50
empty_def_handler, // 16/32 bit timer 3 A 51
empty_def_handler, // 16/32 bit timer 3 B 52
empty_def_handler, // I2C 1 53
0, // Reserved 54
empty_def_handler, // CAN 0 55
0, // Reserved 56
0, // Reserved 57
0, // Reserved 58
empty_def_handler, // Hibernation module 59
empty_def_handler, // USB 60
0, // Reserved 61
empty_def_handler, // UDMA SW 62
empty_def_handler, // UDMA Error 63
empty_def_handler, // ADC 1 Seq 0 64
empty_def_handler, // ADC 1 Seq 1 65
empty_def_handler, // ADC 1 Seq 2 66
empty_def_handler, // ADC 1 Seq 3 67
0, // Reserved 68
0, // Reserved 69
0, // Reserved 70
0, // Reserved 71
0, // Reserved 72
empty_def_handler, // SSI 2 73
empty_def_handler, // SSI 2 74
empty_def_handler, // UART 3 75
empty_def_handler, // UART 4 76
empty_def_handler, // UART 5 77
empty_def_handler, // UART 6 78
empty_def_handler, // UART 7 79
0, // Reserved 80
0, // Reserved 81
0, // Reserved 82
0, // Reserved 83
empty_def_handler, // I2C 2 84
empty_def_handler, // I2C 4 85
empty_def_handler, // 16/32 bit timer 4 A 86
empty_def_handler, // 16/32 bit timer 4 B 87
0, // Reserved 88
0, // Reserved 89
0, // Reserved 90
0, // Reserved 91
0, // Reserved 92
0, // Reserved 93
0, // Reserved 94
0, // Reserved 95
0, // Reserved 96
0, // Reserved 97
0, // Reserved 98
0, // Reserved 99
0, // Reserved 100
0, // Reserved 101
0, // Reserved 102
0, // Reserved 103
0, // Reserved 104
0, // Reserved 105
0, // Reserved 106
0, // Reserved 107
empty_def_handler, // 16/32 bit timer 5 A 108
empty_def_handler, // 16/32 bit timer 5 B 109
WTIMER0IntHandler, // 32/64 bit timer 0 A 110
empty_def_handler, // 32/64 bit timer 0 B 111
empty_def_handler, // 32/64 bit timer 1 A 112
empty_def_handler, // 32/64 bit timer 1 B 113
empty_def_handler, // 32/64 bit timer 2 A 114
empty_def_handler, // 32/64 bit timer 2 B 115
empty_def_handler, // 32/64 bit timer 3 A 116
empty_def_handler, // 32/64 bit timer 3 B 117
empty_def_handler, // 32/64 bit timer 4 A 118
empty_def_handler, // 32/64 bit timer 4 B 119
empty_def_handler, // 32/64 bit timer 5 A 120
empty_def_handler, // 32/64 bit timer 5 B 121
empty_def_handler, // System Exception 122
0, // Reserved 123
0, // Reserved 124
0, // Reserved 125
0, // Reserved 126
0, // Reserved 127
0, // Reserved 128
0, // Reserved 129
0, // Reserved 130
0, // Reserved 131
0, // Reserved 132
0, // Reserved 133
0, // Reserved 134
0, // Reserved 135
0, // Reserved 136
0, // Reserved 137
0, // Reserved 138
0, // Reserved 139
0, // Reserved 140
0, // Reserved 141
0, // Reserved 142
0, // Reserved 143
0, // Reserved 144
0, // Reserved 145
0, // Reserved 146
0, // Reserved 147
0, // Reserved 148
0, // Reserved 149
0, // Reserved 150
0, // Reserved 151
0, // Reserved 152
0, // Reserved 153
0 // Reserved 154
};
//
//-----------------------------------------------------------------------------
// Function implementations.
//-----------------------------------------------------------------------------
/**
* @brief This function is the entry point after a system reset
*
* After a system reset, the following steps are necessary and carried out:
* 1. load data section from flash to ram
* 2. overwrite uninitialized data section (BSS) with zeros
* 3. initialize the newlib
* 4. initialize the board (sync clock, setup std-IO)
* 5. initialize and start RIOTs kernel
*/
void reset_handler(void)
{
uint32_t *dst;
uint32_t *src = &_etext;
/* load data section from flash to ram */
for (dst = &_srelocate; dst < &_erelocate; ) {
*(dst++) = *(src++);
}
/* default bss section to zero */
for (dst = &_szero; dst < &_ezero; ) {
*(dst++) = 0;
}
/* initialize the board and startup the kernel */
board_init();
/* initialize std-c library (this should be done after board_init) */
__libc_init_array();
/* startup the kernel */
kernel_init();
}
// NMI Exception handler code NVIC 2
static
void NmiSR(void){
// Just loop forever, so if you want to debug the processor it's running.
while(1){
}
}
// Hard fault handler code NVIC 3
static
void FaultISR(void){
// Just loop forever, so if you want to debug the processor it's running.
while(1){
}
}
void isr_bus_fault(void){ // Bus Fault
// Bus fault handler code
// Just loop forever, so if you want to debug the processor it's running.
while(1){
}
}
void isr_usage_fault(void){ // Usage Fault
// Usage fault handler code
// Just loop forever, so if you want to debug the processor it's running.
while(1){
}
}
// Empty handler used as default.
void empty_def_handler(void){
// Just loop forever, so if you want to debug the processor it's running.
while(1){
}
}
void TIMER1IntHandler(void){
// Just loop forever, so if you want to debug the processor it's running.
while(1){
}
}
void UART1IntHandler(void){
while(1){
}
}

400
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@ -0,0 +1,400 @@
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other than English is intended solely in order to comply with such laws or for
reference purposes, and the English language version shall be authoritative and
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c. Export Control.
(i). Diversions of Technology. You hereby agree that unless prior authorization
is obtained from the U.S. Department of Commerce, neither you nor your
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(ii). Assurance of Compliance. You understand and acknowledge that products,
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You shall comply with the United States and other applicable non-U.S. laws and
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from TI or its affiliates. You shall not undertake any action that is
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(iii). Licenses. Each party shall secure at its own expense, such licenses and
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13. Entire Agreement. This is the entire Agreement between you and TI, and
absent a signed and effective software license agreement related to the subject
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represent that you have obtained all authorizations and other applicable
consents required empowering you to enter into this Agreement.

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Software License Agreement
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the original copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the original copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// The following are defines for the GPIO register offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // GPIO Data
#define GPIO_O_DIR 0x00000400 // GPIO Direction
#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
#define GPIO_O_LOCK 0x00000520 // GPIO Lock
#define GPIO_O_CR 0x00000524 // GPIO Commit
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_IM register.
//
//*****************************************************************************
#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
#define GPIO_IM_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_RIS register.
//
//*****************************************************************************
#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
#define GPIO_RIS_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_MIS register.
//
//*****************************************************************************
#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
#define GPIO_MIS_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_ICR register.
//
//*****************************************************************************
#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
#define GPIO_ICR_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_LOCK register.
//
//*****************************************************************************
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
// and may be modified
#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
// and may not be modified
#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
// DustDevil-class devices and
// later
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_SI register.
//
//*****************************************************************************
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the GPIO register offsets.
//
//*****************************************************************************
#define GPIO_O_PeriphID4 0x00000FD0
#define GPIO_O_PeriphID5 0x00000FD4
#define GPIO_O_PeriphID6 0x00000FD8
#define GPIO_O_PeriphID7 0x00000FDC
#define GPIO_O_PeriphID0 0x00000FE0
#define GPIO_O_PeriphID1 0x00000FE4
#define GPIO_O_PeriphID2 0x00000FE8
#define GPIO_O_PeriphID3 0x00000FEC
#define GPIO_O_PCellID0 0x00000FF0
#define GPIO_O_PCellID1 0x00000FF4
#define GPIO_O_PCellID2 0x00000FF8
#define GPIO_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the GPIO Register reset values.
//
//*****************************************************************************
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV
#define GPIO_RV_PCellID1 0x000000F0
#define GPIO_RV_PCellID3 0x000000B1
#define GPIO_RV_PeriphID0 0x00000061
#define GPIO_RV_PeriphID1 0x00000010
#define GPIO_RV_PCellID0 0x0000000D
#define GPIO_RV_PCellID2 0x00000005
#define GPIO_RV_PeriphID2 0x00000004
#define GPIO_RV_LOCK 0x00000001 // Lock register RV
#define GPIO_RV_PeriphID7 0x00000000
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV
#define GPIO_RV_PeriphID4 0x00000000
#define GPIO_RV_PeriphID5 0x00000000
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV
#define GPIO_RV_PeriphID6 0x00000000
#define GPIO_RV_PeriphID3 0x00000000
#define GPIO_RV_DATA 0x00000000 // Data register reset value
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV
#endif
#endif // __HW_GPIO_H__

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//*****************************************************************************
//
// hw_hibernate.h - Defines and Macros for the Hibernation module.
//
// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_HIBERNATE_H__
#define __HW_HIBERNATE_H__
//*****************************************************************************
//
// The following are defines for the Hibernation module register addresses.
//
//*****************************************************************************
#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
#define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1
#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
#define HIB_CTL 0x400FC010 // Hibernation Control
#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
// Status
#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
#define HIB_DATA 0x400FC030 // Hibernation Data
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCC register.
//
//*****************************************************************************
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
#define HIB_RTCC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCM0 register.
//
//*****************************************************************************
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
#define HIB_RTCM0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCM1 register.
//
//*****************************************************************************
#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
#define HIB_RTCM1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCLD register.
//
//*****************************************************************************
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
#define HIB_RTCLD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CTL register.
//
//*****************************************************************************
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
// Comparator
#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IM register.
//
//*****************************************************************************
#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
// Interrupt Mask
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
// Mask
#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RIS register.
//
//*****************************************************************************
#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
// Interrupt Status
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
// Status
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
// Interrupt Status
#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_MIS register.
//
//*****************************************************************************
#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
// Interrupt Status
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Status
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
// Interrupt Status
#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
// Status
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IC register.
//
//*****************************************************************************
#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
// Interrupt Clear
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Clear
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
// Interrupt Clear
#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
// Clear
#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCT register.
//
//*****************************************************************************
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
#define HIB_RTCT_TRIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCSS register.
//
//*****************************************************************************
#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
#define HIB_RTCSS_RTCSSM_S 16
#define HIB_RTCSS_RTCSSC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_DATA register.
//
//*****************************************************************************
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
#define HIB_DATA_RTD_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Hibernation module register
// addresses.
//
//*****************************************************************************
#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCC
// register.
//
//*****************************************************************************
#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCM0
// register.
//
//*****************************************************************************
#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCM1
// register.
//
//*****************************************************************************
#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCLD
// register.
//
//*****************************************************************************
#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RIS
// register.
//
//*****************************************************************************
#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_MIS
// register.
//
//*****************************************************************************
#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCT
// register.
//
//*****************************************************************************
#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_DATA
// register.
//
//*****************************************************************************
#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
#endif
#endif // __HW_HIBERNATE_H__

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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following are defines for the I2C register offsets.
//
//*****************************************************************************
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
#define I2C_O_SDR 0x00000008 // I2C Slave Data
#define I2C_O_MDR 0x00000008 // I2C Master Data
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
// Status
#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
// Status
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
#define I2C_O_SACKCTL 0x00000020 // I2C Slave ACK Control
#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
// Count
#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//*****************************************************************************
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
#define I2C_MSA_RS 0x00000001 // Receive not send
#define I2C_MSA_SA_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//*****************************************************************************
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
#define I2C_SOAR_OAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//*****************************************************************************
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
#define I2C_SCSR_DA 0x00000001 // Device Active
#define I2C_SCSR_RREQ 0x00000001 // Receive Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
#define I2C_MCS_QCMD 0x00000020 // Quick Command
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
#define I2C_MCS_HS 0x00000010 // High-Speed Enable
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
#define I2C_MCS_STOP 0x00000004 // Generate STOP
#define I2C_MCS_ERROR 0x00000002 // Error
#define I2C_MCS_START 0x00000002 // Generate START
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//*****************************************************************************
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
#define I2C_SDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//*****************************************************************************
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
#define I2C_MDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//*****************************************************************************
#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
#define I2C_MTPR_TPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//*****************************************************************************
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//*****************************************************************************
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
// Status
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
// Status
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
// Status
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//*****************************************************************************
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
// Status
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
// Status
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//*****************************************************************************
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
// Status
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
//
//*****************************************************************************
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
#define I2C_SOAR2_OAR2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//*****************************************************************************
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
//
//*****************************************************************************
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
//
//*****************************************************************************
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
#define I2C_MCLKOCNT_CNTL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBMON register.
//
//*****************************************************************************
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PP register.
//
//*****************************************************************************
#define I2C_PP_HS 0x00000001 // High-Speed Capable
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PC register.
//
//*****************************************************************************
#define I2C_PC_HS 0x00000001 // High-Speed Capable
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the I2C register offsets.
//
//*****************************************************************************
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SIMR
// register.
//
//*****************************************************************************
#define I2C_SIMR_IM 0x00000001 // Interrupt Mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SRIS
// register.
//
//*****************************************************************************
#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SMIS
// register.
//
//*****************************************************************************
#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SICR
// register.
//
//*****************************************************************************
#define I2C_SICR_IC 0x00000001 // Clear Interrupt
//*****************************************************************************
//
// The following are deprecated defines for the I2C master register offsets.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following are deprecated defines for the I2C slave register offsets.
//
//*****************************************************************************
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C master
// slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
#define I2C_MASTER_SA_SA_SHIFT 1
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Control and Status register.
//
//*****************************************************************************
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
//*****************************************************************************
//
// The following are deprecated defines for the values used in determining the
// contents of the I2C Master Timer Period register.
//
//*****************************************************************************
#define I2C_SCL_FAST 400000 // SCL fast frequency
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Raw Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Configuration register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Own
// Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Control/Status register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Raw
// Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
#endif
#endif // __HW_I2C_H__

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//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following are defines for the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following are defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_GPIOD 19 // GPIO Port D
#define INT_GPIOE 20 // GPIO Port E
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI0 23 // SSI0 Rx and Tx
#define INT_I2C0 24 // I2C0 Master and Slave
#define INT_PWM0_FAULT 25 // PWM0 Fault
#define INT_PWM0_0 26 // PWM0 Generator 0
#define INT_PWM0_1 27 // PWM0 Generator 1
#define INT_PWM0_2 28 // PWM0 Generator 2
#define INT_QEI0 29 // Quadrature Encoder 0
#define INT_ADC0SS0 30 // ADC0 Sequence 0
#define INT_ADC0SS1 31 // ADC0 Sequence 1
#define INT_ADC0SS2 32 // ADC0 Sequence 2
#define INT_ADC0SS3 33 // ADC0 Sequence 3
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_TIMER2A 39 // Timer 2 subtimer A
#define INT_TIMER2B 40 // Timer 2 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
#define INT_COMP1 42 // Analog Comparator 1
#define INT_COMP2 43 // Analog Comparator 2
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
#define INT_FLASH 45 // FLASH Control
#define INT_GPIOF 46 // GPIO Port F
#define INT_GPIOG 47 // GPIO Port G
#define INT_GPIOH 48 // GPIO Port H
#define INT_UART2 49 // UART2 Rx and Tx
#define INT_SSI1 50 // SSI1 Rx and Tx
#define INT_TIMER3A 51 // Timer 3 subtimer A
#define INT_TIMER3B 52 // Timer 3 subtimer B
#define INT_I2C1 53 // I2C1 Master and Slave
#define INT_QEI1 54 // Quadrature Encoder 1
#define INT_CAN0 55 // CAN0
#define INT_CAN1 56 // CAN1
#define INT_CAN2 57 // CAN2
#define INT_ETH 58 // Ethernet
#define INT_HIBERNATE 59 // Hibernation module
#define INT_USB0 60 // USB 0 Controller
#define INT_PWM0_3 61 // PWM0 Generator 3
#define INT_UDMA 62 // uDMA controller
#define INT_UDMAERR 63 // uDMA Error
#define INT_ADC1SS0 64 // ADC1 Sequence 0
#define INT_ADC1SS1 65 // ADC1 Sequence 1
#define INT_ADC1SS2 66 // ADC1 Sequence 2
#define INT_ADC1SS3 67 // ADC1 Sequence 3
#define INT_I2S0 68 // I2S0
#define INT_EPI0 69 // EPI0
#define INT_GPIOJ 70 // GPIO Port J
#define INT_GPIOK 71 // GPIO Port K
#define INT_GPIOL 72 // GPIO Port L
#define INT_SSI2 73 // SSI2
#define INT_SSI3 74 // SSI3
#define INT_UART3 75 // UART3
#define INT_UART4 76 // UART4
#define INT_UART5 77 // UART5
#define INT_UART6 78 // UART6
#define INT_UART7 79 // UART7
#define INT_I2C2 84 // I2C2
#define INT_I2C3 85 // I2C3
#define INT_TIMER4A 86 // Timer 4A
#define INT_TIMER4B 87 // Timer 4B
#define INT_TIMER5A 108 // Timer 5A
#define INT_TIMER5B 109 // Timer 5B
#define INT_WTIMER0A 110 // Wide Timer 0A
#define INT_WTIMER0B 111 // Wide Timer 0B
#define INT_WTIMER1A 112 // Wide Timer 1A
#define INT_WTIMER1B 113 // Wide Timer 1B
#define INT_WTIMER2A 114 // Wide Timer 2A
#define INT_WTIMER2B 115 // Wide Timer 2B
#define INT_WTIMER3A 116 // Wide Timer 3A
#define INT_WTIMER3B 117 // Wide Timer 3B
#define INT_WTIMER4A 118 // Wide Timer 4A
#define INT_WTIMER4B 119 // Wide Timer 4B
#define INT_WTIMER5A 120 // Wide Timer 5A
#define INT_WTIMER5B 121 // Wide Timer 5B
#define INT_SYSEXC 122 // System Exception (imprecise)
#define INT_PECI0 123 // PECI 0
#define INT_LPC0 124 // LPC 0
#define INT_I2C4 125 // I2C4
#define INT_I2C5 126 // I2C5
#define INT_GPIOM 127 // GPIO Port M
#define INT_GPION 128 // GPIO Port N
#define INT_FAN0 130 // FAN 0
#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
#define INT_GPIOP1 133 // GPIO Port P1
#define INT_GPIOP2 134 // GPIO Port P2
#define INT_GPIOP3 135 // GPIO Port P3
#define INT_GPIOP4 136 // GPIO Port P4
#define INT_GPIOP5 137 // GPIO Port P5
#define INT_GPIOP6 138 // GPIO Port P6
#define INT_GPIOP7 139 // GPIO Port P7
#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
#define INT_GPIOQ1 141 // GPIO Port Q1
#define INT_GPIOQ2 142 // GPIO Port Q2
#define INT_GPIOQ3 143 // GPIO Port Q3
#define INT_GPIOQ4 144 // GPIO Port Q4
#define INT_GPIOQ5 145 // GPIO Port Q5
#define INT_GPIOQ6 146 // GPIO Port Q6
#define INT_GPIOQ7 147 // GPIO Port Q7
#define INT_PWM1_0 150 // PWM1 Generator 0
#define INT_PWM1_1 151 // PWM1 Generator 1
#define INT_PWM1_2 152 // PWM1 Generator 2
#define INT_PWM1_3 153 // PWM1 Generator 3
#define INT_PWM1_FAULT 154 // PWM1 Fault
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 155
//*****************************************************************************
//
// The following are defines for the total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI 29 // Quadrature Encoder
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_PWM3 61 // PWM Generator 3
#endif
#endif // __HW_INTS_H__

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//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI0_BASE 0x40008000 // SSI0
#define SSI1_BASE 0x40009000 // SSI1
#define SSI2_BASE 0x4000A000 // SSI2
#define SSI3_BASE 0x4000B000 // SSI3
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define UART2_BASE 0x4000E000 // UART2
#define UART3_BASE 0x4000F000 // UART3
#define UART4_BASE 0x40010000 // UART4
#define UART5_BASE 0x40011000 // UART5
#define UART6_BASE 0x40012000 // UART6
#define UART7_BASE 0x40013000 // UART7
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master
#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave
#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master
#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
#define QEI0_BASE 0x4002C000 // QEI0
#define QEI1_BASE 0x4002D000 // QEI1
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define TIMER3_BASE 0x40033000 // Timer3
#define TIMER4_BASE 0x40034000 // Timer4
#define TIMER5_BASE 0x40035000 // Timer5
#define WTIMER0_BASE 0x40036000 // Wide Timer0
#define WTIMER1_BASE 0x40037000 // Wide Timer1
#define ADC0_BASE 0x40038000 // ADC0
#define ADC1_BASE 0x40039000 // ADC1
#define COMP_BASE 0x4003C000 // Analog comparators
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
#define CAN0_BASE 0x40040000 // CAN0
#define CAN1_BASE 0x40041000 // CAN1
#define CAN2_BASE 0x40042000 // CAN2
#define ETH_BASE 0x40048000 // Ethernet
#define MAC_BASE 0x40048000 // Ethernet
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
#define USB0_BASE 0x40050000 // USB 0 Controller
#define I2S0_BASE 0x40054000 // I2S0
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC)
#define FAN0_BASE 0x40084000 // Fan Control (FAN)
#define EEPROM_BASE 0x400AF000 // EEPROM memory
#define PECI0_BASE 0x400B0000 // Platform Environment Control
// Interface (PECI)
#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master
#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave
#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master
#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave
#define EPI0_BASE 0x400D0000 // EPI0
#define SYSEXC_BASE 0x400F9000 // System Exception Module
#define HIB_BASE 0x400FC000 // Hibernation Module
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define UDMA_BASE 0x400FF000 // uDMA Controller
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the base address of the memories
// and peripherals.
//
//*****************************************************************************
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define SSI_BASE 0x40008000 // SSI
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define PWM_BASE 0x40028000 // PWM
#define QEI_BASE 0x4002C000 // QEI
#define ADC_BASE 0x40038000 // ADC
#endif
#endif // __HW_MEMMAP_H__

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//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following are defines for the SSI register offsets.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // SSI Control 0
#define SSI_O_CR1 0x00000004 // SSI Control 1
#define SSI_O_DR 0x00000008 // SSI Data
#define SSI_O_SR 0x0000000C // SSI Status
#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR0 register.
//
//*****************************************************************************
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
// Serial Frame Format
#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
#define SSI_CR0_SCR_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR1 register.
//
//*****************************************************************************
#define SSI_CR1_EOT 0x00000010 // End of Transmission
#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
// Enable
#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DR register.
//
//*****************************************************************************
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
#define SSI_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_SR register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CPSR register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
#define SSI_CPSR_CPSDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_IM register.
//
//*****************************************************************************
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
// Mask
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_RIS register.
//
//*****************************************************************************
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
// Status
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
// Status
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
// Interrupt Status
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_MIS register.
//
//*****************************************************************************
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
// Interrupt Status
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
// Interrupt Status
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
// Interrupt Status
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_ICR register.
//
//*****************************************************************************
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
// Clear
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DMACTL register.
//
//*****************************************************************************
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CC register.
//
//*****************************************************************************
#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
// PLL bypass is in effect) or the
// PLL output (default)
#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SSI_O_CR0
// register.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_DSS 0x0000000F // Data size select
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SSI_O_CPSR
// register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
//*****************************************************************************
//
// The following are deprecated defines for the SSI controller's FIFO size.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the interrupt
// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
// registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif
#endif // __HW_SSI_H__

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//*****************************************************************************
//
// hw_sysexc.h - Macros used when accessing the system exception module.
//
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SYSEXC_H__
#define __HW_SYSEXC_H__
//*****************************************************************************
//
// The following are defines for the System Exception Module register
// addresses.
//
//*****************************************************************************
#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
// Status
#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
#define SYSEXC_MIS 0x400F9008 // System Exception Masked
// Interrupt Status
#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_RIS register.
//
//*****************************************************************************
#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
// Raw Interrupt Status
#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
// Exception Raw Interrupt Status
#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
// Exception Raw Interrupt Status
#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
// Raw Interrupt Status
#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
// Exception Raw Interrupt Status
#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
// Exception Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_IM register.
//
//*****************************************************************************
#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
// Interrupt Mask
#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
// Exception Interrupt Mask
#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
// Exception Interrupt Mask
#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
// Interrupt Mask
#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
// Exception Interrupt Mask
#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
// Exception Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_MIS register.
//
//*****************************************************************************
#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
// Masked Interrupt Status
#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
// Exception Masked Interrupt
// Status
#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
// Exception Masked Interrupt
// Status
#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
// Masked Interrupt Status
#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
// Exception Masked Interrupt
// Status
#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
// Exception Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_IC register.
//
//*****************************************************************************
#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
// Interrupt Clear
#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
// Exception Interrupt Clear
#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
// Exception Interrupt Clear
#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
// Interrupt Clear
#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
// Exception Interrupt Clear
#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
// Exception Interrupt Clear
#endif // __HW_SYSEXC_H__

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//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following are defines for the Timer register offsets.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // GPTM Configuration
#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
#define TIMER_O_CTL 0x0000000C // GPTM Control
#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
#define TIMER_O_TAR 0x00000048 // GPTM Timer A
#define TIMER_O_TBR 0x0000004C // GPTM Timer B
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_M 0x00000007 // GPTM Configuration
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
// counter configuration
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
// function is controlled by bits
// 1:0 of GPTMTAMR and GPTMTBMR
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
// Operation
#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
// Update
#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
// Enable
#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
// Enable
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
// Select
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
// Operation
#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
// Update
#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
// Enable
#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
// Enable
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
// Select
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
// Enable
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
// Enable
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_SYNC register.
//
//*****************************************************************************
#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
// 5
#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
// affected
#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 5 is triggered
#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
// 4
#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
// affected
#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 4 is triggered
#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
// 3
#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
// affected
#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 3 is triggered
#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
// 2
#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
// affected
#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 2 is triggered
#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
// 1
#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
// affected
#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 1 is triggered
#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
// 0
#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
// affected
#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 0 is triggered
#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
// 5
#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
// affected
#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 5 is triggered
#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
// 4
#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
// affected
#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 4 is triggered
#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
// 3
#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
// affected
#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 3 is triggered
#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
// 2
#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
// affected
#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 2 is triggered
#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
// 1
#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
// affected
#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 1 is triggered
#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
// 0
#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
// affected
#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 0 is triggered
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error
// Interrupt Mask
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
// Mask
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
// Interrupt Mask
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
// Interrupt Mask
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
// Mask
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
// Mask
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
// Interrupt Mask
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
// Interrupt Mask
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw
// Interrupt
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
// Raw Interrupt
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
// Raw Interrupt
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
// Interrupt
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
// Raw Interrupt
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
// Raw Interrupt
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked
// Interrupt
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
// Interrupt
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
// Masked Interrupt
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
// Masked Interrupt
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
// Interrupt
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
// Interrupt
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
// Masked Interrupt
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
// Masked Interrupt
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Clear
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
// Clear
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
// Interrupt Clear
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
// Interrupt Clear
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
// Clear
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
// Clear
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
// Interrupt Clear
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
// Interrupt Clear
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
// Register
#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
// Register High
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
// Register Low
#define TIMER_TAILR_TAILRH_S 16
#define TIMER_TAILR_TAILRL_S 0
#define TIMER_TAILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_S 0
#define TIMER_TBILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
// register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
#define TIMER_TAMATCHR_TAMRH_S 16
#define TIMER_TAMATCHR_TAMRL_S 0
#define TIMER_TAMATCHR_TAMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
// register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
#define TIMER_TBMATCHR_TBMR_S 0
#define TIMER_TBMATCHR_TBMRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPR register.
//
//*****************************************************************************
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
#define TIMER_TAPR_TAPSRH_S 8
#define TIMER_TAPR_TAPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPR register.
//
//*****************************************************************************
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
#define TIMER_TBPR_TBPSRH_S 8
#define TIMER_TBPR_TBPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
//
//*****************************************************************************
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
// Byte
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
#define TIMER_TAPMR_TAPSMRH_S 8
#define TIMER_TAPMR_TAPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
//
//*****************************************************************************
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
// Byte
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
#define TIMER_TBPMR_TBPSMRH_S 8
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAR_TARH_S 16
#define TIMER_TAR_TARL_S 0
#define TIMER_TAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
#define TIMER_TBR_TBRL_S 0
#define TIMER_TBR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAV register.
//
//*****************************************************************************
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAV_TAVH_S 16
#define TIMER_TAV_TAVL_S 0
#define TIMER_TAV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBV register.
//
//*****************************************************************************
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
#define TIMER_TBV_TBVL_S 0
#define TIMER_TBV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
//
//*****************************************************************************
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
#define TIMER_RTCPD_RTCPD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPS register.
//
//*****************************************************************************
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
#define TIMER_TAPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPS register.
//
//*****************************************************************************
#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TBPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPV register.
//
//*****************************************************************************
#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TAPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPV register.
//
//*****************************************************************************
#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
#define TIMER_TBPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_PP register.
//
//*****************************************************************************
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
// 16 bits each with an 8-bit
// prescale counter
#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
// 32 bits each with a 16-bit
// prescale counter
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_CFG
// register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_CTL
// register.
//
//*****************************************************************************
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_RIS
// register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
// register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
// register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_O_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_O_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TAR
// register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TBR
// register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the timer
// registers.
//
//*****************************************************************************
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnMR
// register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPR
// register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPMR
// register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
#endif
#endif // __HW_TIMER_H__

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//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGH(x) \
(*((volatile unsigned short *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
//*****************************************************************************
//
// Helper Macros for determining silicon revisions, etc.
//
// These macros will be used by Driverlib at "run-time" to create necessary
// conditional code blocks that will allow a single version of the Driverlib
// "binary" code to support multiple(all) Stellaris silicon revisions.
//
// It is expected that these macros will be used inside of a standard 'C'
// conditional block of code, e.g.
//
// if(CLASS_IS_SANDSTORM)
// {
// do some Sandstorm-class specific code here.
// }
//
// By default, these macros will be defined as run-time checks of the
// appropriate register(s) to allow creation of run-time conditional code
// blocks for a common DriverLib across the entire Stellaris family.
//
// However, if code-space optimization is required, these macros can be "hard-
// coded" for a specific version of Stellaris silicon. Many compilers will
// then detect the "hard-coded" conditionals, and appropriately optimize the
// code blocks, eliminating any "unreachable" code. This would result in
// a smaller Driverlib, thus producing a smaller final application size, but
// at the cost of limiting the Driverlib binary to a specific Stellaris
// silicon revision.
//
//*****************************************************************************
#ifndef CLASS_IS_SANDSTORM
#define CLASS_IS_SANDSTORM \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
#endif
#ifndef CLASS_IS_FURY
#define CLASS_IS_FURY \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
#endif
#ifndef CLASS_IS_DUSTDEVIL
#define CLASS_IS_DUSTDEVIL \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
#endif
#ifndef CLASS_IS_TEMPEST
#define CLASS_IS_TEMPEST \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
#endif
#ifndef CLASS_IS_FIRESTORM
#define CLASS_IS_FIRESTORM \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
#endif
#ifndef CLASS_IS_BLIZZARD
#define CLASS_IS_BLIZZARD \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD))
#endif
#ifndef REVISION_IS_A0
#define REVISION_IS_A0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_A1
#define REVISION_IS_A1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_A2
#define REVISION_IS_A2 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
#endif
#ifndef REVISION_IS_B0
#define REVISION_IS_B0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_B1
#define REVISION_IS_B1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
#endif
#ifndef REVISION_IS_C0
#define REVISION_IS_C0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_C1
#define REVISION_IS_C1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
#endif
#ifndef REVISION_IS_C2
#define REVISION_IS_C2 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
#endif
#ifndef REVISION_IS_C3
#define REVISION_IS_C3 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
#endif
#ifndef REVISION_IS_C5
#define REVISION_IS_C5 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5))
#endif
//*****************************************************************************
//
// Deprecated silicon class and revision detection macros.
//
//*****************************************************************************
#ifndef DEPRECATED
#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
#define DEVICE_IS_FURY CLASS_IS_FURY
#define DEVICE_IS_REVA2 REVISION_IS_A2
#define DEVICE_IS_REVC1 REVISION_IS_C1
#define DEVICE_IS_REVC2 REVISION_IS_C2
#endif
#endif // __HW_TYPES_H__

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//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// The following are defines for the UART register offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // UART Data
#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
#define UART_O_FR 0x00000018 // UART Flag
#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
// Divisor
#define UART_O_LCRH 0x0000002C // UART Line Control
#define UART_O_CTL 0x00000030 // UART Control
#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
#define UART_O_IM 0x00000038 // UART Interrupt Mask
#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
#define UART_O_ICR 0x00000044 // UART Interrupt Clear
#define UART_O_DMACTL 0x00000048 // UART DMA Control
#define UART_O_LCTL 0x00000090 // UART LIN Control
#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
#define UART_O_LTIM 0x00000098 // UART LIN Timer
#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
#define UART_O_CC 0x00000FC8 // UART Clock Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DR register.
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // UART Overrun Error
#define UART_DR_BE 0x00000400 // UART Break Error
#define UART_DR_PE 0x00000200 // UART Parity Error
#define UART_DR_FE 0x00000100 // UART Framing Error
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
#define UART_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RSR register.
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // UART Overrun Error
#define UART_RSR_BE 0x00000004 // UART Break Error
#define UART_RSR_PE 0x00000002 // UART Parity Error
#define UART_RSR_FE 0x00000001 // UART Framing Error
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ECR register.
//
//*****************************************************************************
#define UART_ECR_DATA_M 0x000000FF // Error Clear
#define UART_ECR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FR register.
//
//*****************************************************************************
#define UART_FR_RI 0x00000100 // Ring Indicator
#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
#define UART_FR_DCD 0x00000004 // Data Carrier Detect
#define UART_FR_DSR 0x00000002 // Data Set Ready
#define UART_FR_CTS 0x00000001 // Clear To Send
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ILPR register.
//
//*****************************************************************************
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
#define UART_ILPR_ILPDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IBRD register.
//
//*****************************************************************************
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
#define UART_IBRD_DIVINT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FBRD register.
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
#define UART_FBRD_DIVFRAC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCRH register.
//
//*****************************************************************************
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
#define UART_LCRH_BRK 0x00000001 // UART Send Break
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CTL register.
//
//*****************************************************************************
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
#define UART_CTL_RTS 0x00000800 // Request to Send
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
#define UART_CTL_RXE 0x00000200 // UART Receive Enable
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
#define UART_CTL_HSE 0x00000020 // High-Speed Enable
#define UART_CTL_EOT 0x00000010 // End of Transmission
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IFLS register.
//
//*****************************************************************************
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
// Level Select
#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
// Level Select
#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IM register.
//
//*****************************************************************************
#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
// Mask
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
// Mask
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
// Mask
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
// Interrupt Mask
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Mask
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
// Interrupt Mask
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
// Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RIS register.
//
//*****************************************************************************
#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
// Status
#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
// Status
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
// Interrupt Status
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
// Status
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
// Status
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
// Status
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
// Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
// Status
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
// Status
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
// Interrupt Status
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
// Raw Interrupt Status
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
// Interrupt Status
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_MIS register.
//
//*****************************************************************************
#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
// Status
#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
// Status
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
// Interrupt Status
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
// Status
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
// Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
// Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
// Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
// Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
// Status
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
// Status
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
// Interrupt Status
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
// Masked Interrupt Status
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
// Interrupt Status
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ICR register.
//
//*****************************************************************************
#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
// Interrupt Clear
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Clear
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
// Interrupt Clear
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
// Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DMACTL register.
//
//*****************************************************************************
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCTL register.
//
//*****************************************************************************
#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
// (default)
#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LSS register.
//
//*****************************************************************************
#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
#define UART_LSS_TSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LTIM register.
//
//*****************************************************************************
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
#define UART_LTIM_TIMER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITADDR
// register.
//
//*****************************************************************************
#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
#define UART_9BITADDR_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITAMASK
// register.
//
//*****************************************************************************
#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
#define UART_9BITAMASK_MASK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_PP register.
//
//*****************************************************************************
#define UART_PP_NB 0x00000002 // 9-Bit Support
#define UART_PP_SC 0x00000001 // Smart Card Support
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CC register.
//
//*****************************************************************************
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the UART register offsets.
//
//*****************************************************************************
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
#define UART_O_PeriphID4 0x00000FD0
#define UART_O_PeriphID5 0x00000FD4
#define UART_O_PeriphID6 0x00000FD8
#define UART_O_PeriphID7 0x00000FDC
#define UART_O_PeriphID0 0x00000FE0
#define UART_O_PeriphID1 0x00000FE4
#define UART_O_PeriphID2 0x00000FE8
#define UART_O_PeriphID3 0x00000FEC
#define UART_O_PCellID0 0x00000FF0
#define UART_O_PCellID1 0x00000FF4
#define UART_O_PCellID2 0x00000FF8
#define UART_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_DR
// register.
//
//*****************************************************************************
#define UART_DR_DATA_MASK 0x000000FF // UART data
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_IBRD
// register.
//
//*****************************************************************************
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_FBRD
// register.
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_LCR_H
// register.
//
//*****************************************************************************
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
#define UART_LCR_H_WLEN 0x00000060 // Word length
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
#define UART_LCR_H_PEN 0x00000002 // Parity Enable
#define UART_LCR_H_BRK 0x00000001 // Send Break
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_IFLS
// register.
//
//*****************************************************************************
#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_ICR
// register.
//
//*****************************************************************************
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
UART_RSR_FE)
//*****************************************************************************
//
// The following are deprecated defines for the Reset Values for UART
// Registers.
//
//*****************************************************************************
#define UART_RV_CTL 0x00000300
#define UART_RV_PCellID1 0x000000F0
#define UART_RV_PCellID3 0x000000B1
#define UART_RV_FR 0x00000090
#define UART_RV_PeriphID2 0x00000018
#define UART_RV_IFLS 0x00000012
#define UART_RV_PeriphID0 0x00000011
#define UART_RV_PCellID0 0x0000000D
#define UART_RV_PCellID2 0x00000005
#define UART_RV_PeriphID3 0x00000001
#define UART_RV_PeriphID4 0x00000000
#define UART_RV_LCR_H 0x00000000
#define UART_RV_PeriphID6 0x00000000
#define UART_RV_DR 0x00000000
#define UART_RV_RSR 0x00000000
#define UART_RV_ECR 0x00000000
#define UART_RV_PeriphID5 0x00000000
#define UART_RV_RIS 0x00000000
#define UART_RV_FBRD 0x00000000
#define UART_RV_IM 0x00000000
#define UART_RV_MIS 0x00000000
#define UART_RV_ICR 0x00000000
#define UART_RV_PeriphID1 0x00000000
#define UART_RV_PeriphID7 0x00000000
#define UART_RV_IBRD 0x00000000
#endif
#endif // __HW_UART_H__

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//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following are defines for the Watchdog Timer register offsets.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Watchdog Load
#define WDT_O_VALUE 0x00000004 // Watchdog Value
#define WDT_O_CTL 0x00000008 // Watchdog Control
#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
#define WDT_O_TEST 0x00000418 // Watchdog Test
#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOAD register.
//
//*****************************************************************************
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
#define WDT_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_VALUE register.
//
//*****************************************************************************
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
#define WDT_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_CTL register.
//
//*****************************************************************************
#define WDT_CTL_WRC 0x80000000 // Write Complete
#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_ICR register.
//
//*****************************************************************************
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
#define WDT_ICR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_RIS register.
//
//*****************************************************************************
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_MIS register.
//
//*****************************************************************************
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
#define WDT_LOCK_LOCKED 0x00000001 // Locked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
// WDT_MIS registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Watchdog Timer register
// offsets.
//
//*****************************************************************************
#define WDT_O_PeriphID4 0x00000FD0
#define WDT_O_PeriphID5 0x00000FD4
#define WDT_O_PeriphID6 0x00000FD8
#define WDT_O_PeriphID7 0x00000FDC
#define WDT_O_PeriphID0 0x00000FE0
#define WDT_O_PeriphID1 0x00000FE4
#define WDT_O_PeriphID2 0x00000FE8
#define WDT_O_PeriphID3 0x00000FEC
#define WDT_O_PCellID0 0x00000FF0
#define WDT_O_PCellID1 0x00000FF4
#define WDT_O_PCellID2 0x00000FF8
#define WDT_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the WDT_O_TEST
// register.
//
//*****************************************************************************
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the WDT
// registers.
//
//*****************************************************************************
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
#define WDT_RV_PCellID1 0x000000F0
#define WDT_RV_PCellID3 0x000000B1
#define WDT_RV_PeriphID1 0x00000018
#define WDT_RV_PeriphID2 0x00000018
#define WDT_RV_PCellID0 0x0000000D
#define WDT_RV_PCellID2 0x00000005
#define WDT_RV_PeriphID0 0x00000005
#define WDT_RV_PeriphID3 0x00000001
#define WDT_RV_PeriphID5 0x00000000
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
#define WDT_RV_CTL 0x00000000 // Control register
#define WDT_RV_PeriphID4 0x00000000
#define WDT_RV_PeriphID6 0x00000000
#define WDT_RV_PeriphID7 0x00000000
#define WDT_RV_LOCK 0x00000000 // Lock register
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
#endif
#endif // __HW_WATCHDOG_H__

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//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
#define ADC_CTL_CH8 0x00000008 // Input channel 8
#define ADC_CTL_CH9 0x00000009 // Input channel 9
#define ADC_CTL_CH10 0x0000000A // Input channel 10
#define ADC_CTL_CH11 0x0000000B // Input channel 11
#define ADC_CTL_CH12 0x0000000C // Input channel 12
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
#define ADC_CTL_CH16 0x00000100 // Input channel 16
#define ADC_CTL_CH17 0x00000101 // Input channel 17
#define ADC_CTL_CH18 0x00000102 // Input channel 18
#define ADC_CTL_CH19 0x00000103 // Input channel 19
#define ADC_CTL_CH20 0x00000104 // Input channel 20
#define ADC_CTL_CH21 0x00000105 // Input channel 21
#define ADC_CTL_CH22 0x00000106 // Input channel 22
#define ADC_CTL_CH23 0x00000107 // Input channel 23
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
//*****************************************************************************
//
// Values that can be passed to ADCComparatorConfigure as part of the
// ulConfig parameter.
//
//*****************************************************************************
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
#define ADC_COMP_TRIG_LOW_ALWAYS \
0x00001000 // Trigger Low Always
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
#define ADC_COMP_TRIG_LOW_HALWAYS \
0x00001200 // Trigger Low Always (Hysteresis)
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
#define ADC_COMP_TRIG_MID_ALWAYS \
0x00001400 // Trigger Mid Always
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
#define ADC_COMP_TRIG_HIGH_ALWAYS \
0x00001C00 // Trigger High Always
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
#define ADC_COMP_TRIG_HIGH_HALWAYS \
0x00001E00 // Trigger High Always (Hysteresis)
#define ADC_COMP_TRIG_HIGH_HONCE \
0x00001F00 // Trigger High Once (Hysteresis)
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
#define ADC_COMP_INT_LOW_ALWAYS \
0x00000010 // Interrupt Low Always
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
#define ADC_COMP_INT_LOW_HALWAYS \
0x00000012 // Interrupt Low Always
// (Hysteresis)
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
#define ADC_COMP_INT_MID_ALWAYS \
0x00000014 // Interrupt Mid Always
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
#define ADC_COMP_INT_HIGH_ALWAYS \
0x0000001C // Interrupt High Always
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
#define ADC_COMP_INT_HIGH_HALWAYS \
0x0000001E // Interrupt High Always
// (Hysteresis)
#define ADC_COMP_INT_HIGH_HONCE \
0x0000001F // Interrupt High Once (Hysteresis)
//*****************************************************************************
//
// Values that can be used to modify the sequence number passed to
// ADCProcessorTrigger in order to get cross-module synchronous processor
// triggers.
//
//*****************************************************************************
#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
//*****************************************************************************
//
// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and
// returned from ADCPhaseDelayGet.
//
//*****************************************************************************
#define ADC_PHASE_0 0x00000000 // 0 degrees
#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
#define ADC_PHASE_45 0x00000002 // 45 degrees
#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
#define ADC_PHASE_90 0x00000004 // 90 degrees
#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
#define ADC_PHASE_135 0x00000006 // 135 degrees
#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
#define ADC_PHASE_180 0x00000008 // 180 degrees
#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
#define ADC_PHASE_225 0x0000000A // 225 degrees
#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
#define ADC_PHASE_270 0x0000000C // 270 degrees
#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
#define ADC_PHASE_315 0x0000000E // 315 degrees
#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
//*****************************************************************************
//
// Values that can be passed to ADCReferenceSet as the ulRef parameter.
//
//*****************************************************************************
#define ADC_REF_INT 0x00000000 // Internal reference
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
#define ADC_REF_EXT_1V 0x00000003 // External 1V reference
//*****************************************************************************
//
// Values that can be passed to ADCResolutionSet as the ulResolution parameter.
//
//*****************************************************************************
#define ADC_RES_10BIT_S 0x00000000 // 10-bit resolution
#define ADC_RES_12BIT_S 0x00000010 // 12-bit resolution
//*****************************************************************************
//
// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(),
// ADCIntClearEx() and ADCIntStatusEx().
//
//*****************************************************************************
#define ADC_INT_SS0 0x00000001
#define ADC_INT_SS1 0x00000002
#define ADC_INT_SS2 0x00000004
#define ADC_INT_SS3 0x00000008
#define ADC_INT_DMA_SS0 0x00000100
#define ADC_INT_DMA_SS1 0x00000200
#define ADC_INT_DMA_SS2 0x00000400
#define ADC_INT_DMA_SS3 0x00000800
#define ADC_INT_DCON_SS0 0x00010000
#define ADC_INT_DCON_SS1 0x00020000
#define ADC_INT_DCON_SS2 0x00040000
#define ADC_INT_DCON_SS3 0x00080000
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
extern unsigned long ADCIntStatus(unsigned long ulBase,
unsigned long ulSequenceNum,
tBoolean bMasked);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCSequenceEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulTrigger,
unsigned long ulPriority);
extern void ADCSequenceStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern long ADCSequenceOverflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceOverflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceUnderflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceUnderflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer);
extern void ADCProcessorTrigger(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor);
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer,
unsigned long ulCount);
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
unsigned long ulFactor);
extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
unsigned long ulLowRef,
unsigned long ulHighRef);
extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
tBoolean bTrigger, tBoolean bInterrupt);
extern void ADCComparatorIntDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCComparatorIntEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
extern void ADCComparatorIntClear(unsigned long ulBase,
unsigned long ulStatus);
extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
extern unsigned long ADCReferenceGet(unsigned long ulBase);
extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution);
extern unsigned long ADCResolutionGet(unsigned long ulBase);
extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
// the values may be selected and combined together with values from the other
// groups via a logical OR.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#ifndef DEPRECATED
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#endif
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__

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//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern unsigned long CPUcpsid(void);
extern unsigned long CPUcpsie(void);
extern unsigned long CPUprimask(void);
extern void CPUwfi(void);
extern unsigned long CPUbasepriGet(void);
extern void CPUbasepriSet(unsigned long ulNewBasepri);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CPU_H__

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//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

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//*****************************************************************************
//
// fpu.h - Prototypes for the floatint point manipulation routines.
//
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FPU_H__
#define __FPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_HALF_IEEE 0x00000000
#define FPU_HALF_ALTERNATE 0x04000000
//*****************************************************************************
//
// Values that can be passed to FPUNaNModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_NAN_PROPAGATE 0x00000000
#define FPU_NAN_DEFAULT 0x02000000
//*****************************************************************************
//
// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
//*****************************************************************************
//
// Values that can be passed to FPURoundingModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_ROUND_NEAREST 0x00000000
#define FPU_ROUND_POS_INF 0x00400000
#define FPU_ROUND_NEG_INF 0x00800000
#define FPU_ROUND_ZERO 0x00c00000
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void FPUEnable(void);
extern void FPUDisable(void);
extern void FPUStackingEnable(void);
extern void FPULazyStackingEnable(void);
extern void FPUStackingDisable(void);
extern void FPUHalfPrecisionModeSet(unsigned long ulMode);
extern void FPUNaNModeSet(unsigned long ulMode);
extern void FPUFlushToZeroModeSet(unsigned long ulMode);
extern void FPURoundingModeSet(unsigned long ulMode);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FPU_H__

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfnIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinConfigure(unsigned long ulPinConfig);
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
//****************************************************************************
//
// The definitions for GPIOPinConfigure previously resided in this file but
// have been moved to pin_map.h and made part-specific (in other words, only
// those definitions that are valid based on the selected part, as defined by
// PART_<partnum>, will be made available). For backwards compatibility,
// pin_map.h is included here so that the expected definitions will still be
// available (though part-specific now, so some that were previously available
// but inappropriate for the given part will not be available).
//
//*****************************************************************************
#ifndef DEPRECATED
#include "pin_map.h"
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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//*****************************************************************************
//
// hibernate.h - API definition for the Hibernation module.
//
// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HIBERNATE_H__
#define __HIBERNATE_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macros needed for selecting the clock source for HibernateClockSelect()
//
//*****************************************************************************
#define HIBERNATE_CLOCK_SEL_RAW 0x00000004
#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000
//*****************************************************************************
//
// Macros need to configure wake events for HibernateWakeSet()
//
//*****************************************************************************
#define HIBERNATE_WAKE_PIN 0x00000010
#define HIBERNATE_WAKE_RTC 0x00000008
#define HIBERNATE_WAKE_LOW_BAT 0x00000200
//*****************************************************************************
//
// Macros needed to configure low battery detect for HibernateLowBatSet()
//
//*****************************************************************************
#define HIBERNATE_LOW_BAT_DETECT 0x00000020
#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
#define HIBERNATE_LOW_BAT_1_9V 0x00000000
#define HIBERNATE_LOW_BAT_2_1V 0x00002000
#define HIBERNATE_LOW_BAT_2_3V 0x00004000
#define HIBERNATE_LOW_BAT_2_5V 0x00006000
//*****************************************************************************
//
// Macros defining interrupt source bits for the interrupt functions.
//
//*****************************************************************************
#define HIBERNATE_INT_WR_COMPLETE 0x00000010
#define HIBERNATE_INT_PIN_WAKE 0x00000008
#define HIBERNATE_INT_LOW_BAT 0x00000004
#define HIBERNATE_INT_RTC_MATCH_0 0x00000001
#define HIBERNATE_INT_RTC_MATCH_1 0x00000002
//*****************************************************************************
//
// Macros defining oscillator configuration options for the
// HibernateClockConfig() function.
//
//*****************************************************************************
#define HIBERNATE_OSC_LOWDRIVE 0x00040000
#define HIBERNATE_OSC_HIGHDRIVE 0x00060000
#define HIBERNATE_OSC_DISABLE 0x00010000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HibernateGPIORetentionEnable(void);
extern void HibernateGPIORetentionDisable(void);
extern tBoolean HibernateGPIORetentionGet(void);
extern void HibernateEnableExpClk(unsigned long ulHibClk);
extern void HibernateDisable(void);
extern void HibernateClockSelect(unsigned long ulClockInput);
extern void HibernateRTCEnable(void);
extern void HibernateRTCDisable(void);
extern void HibernateWakeSet(unsigned long ulWakeFlags);
extern unsigned long HibernateWakeGet(void);
extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
extern unsigned long HibernateLowBatGet(void);
extern void HibernateRTCSet(unsigned long ulRTCValue);
extern unsigned long HibernateRTCGet(void);
extern void HibernateRTCMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch0Get(void);
extern void HibernateRTCMatch1Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch1Get(void);
extern void HibernateRTCTrimSet(unsigned long ulTrim);
extern unsigned long HibernateRTCTrimGet(void);
extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateRequest(void);
extern void HibernateIntEnable(unsigned long ulIntFlags);
extern void HibernateIntDisable(unsigned long ulIntFlags);
extern void HibernateIntRegister(void (*pfnHandler)(void));
extern void HibernateIntUnregister(void);
extern unsigned long HibernateIntStatus(tBoolean bMasked);
extern void HibernateIntClear(unsigned long ulIntFlags);
extern unsigned long HibernateIsActive(void);
extern void HibernateRTCSSMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCSSMatch0Get(void);
extern unsigned long HibernateRTCSSGet(void);
extern void HibernateClockConfig(unsigned long ulConfig);
extern void HibernateBatCheckStart(void);
extern unsigned long HibernateBatCheckDone(void);
//*****************************************************************************
//
// Several Hibernate module APIs have been renamed, with the original function
// name being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define HibernateEnable(a) \
HibernateEnableExpClk(a, SysCtlClockGet())
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __HIBERNATE_H__

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//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START \
0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT \
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_QUICK_COMMAND \
0x00000027
#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
0x00000011
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Master interrupts.
//
//*****************************************************************************
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt.
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt.
//*****************************************************************************
//
// I2C Slave interrupts.
//
//*****************************************************************************
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterIntEnableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CMasterIntDisableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase,
tBoolean bMasked);
extern void I2CMasterIntClearEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue);
extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable);
extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK);
extern unsigned long I2CMasterLineStateGet(unsigned long ulBase);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum,
unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2CSlaveIntDisableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase,
tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
//*****************************************************************************
//
// Several I2C APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define I2CMasterInit(a, b) \
I2CMasterInitExpClk(a, SysCtlClockGet(), b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__

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//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware.
//
//*****************************************************************************
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean IntMasterEnable(void);
extern tBoolean IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
extern unsigned long IntIsEnabled(unsigned long ulInterrupt);
extern void IntPendSet(unsigned long ulInterrupt);
extern void IntPendClear(unsigned long ulInterrupt);
extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
extern unsigned long IntPriorityMaskGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

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//*****************************************************************************
//
// pin_map.h - Mapping of peripherals to pins for all parts.
//
// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PIN_MAP_H__
#define __PIN_MAP_H__
//*****************************************************************************
//
// LM4F120H5QR Port/Pin Mapping Definitions
//
//*****************************************************************************
#ifdef PART_LM4F120H5QR
#define GPIO_PA0_U0RX 0x00000001
#define GPIO_PA1_U0TX 0x00000401
#define GPIO_PA2_SSI0CLK 0x00000802
#define GPIO_PA3_SSI0FSS 0x00000C02
#define GPIO_PA4_SSI0RX 0x00001002
#define GPIO_PA5_SSI0TX 0x00001402
#define GPIO_PA6_I2C1SCL 0x00001803
#define GPIO_PA7_I2C1SDA 0x00001C03
#define GPIO_PB0_U1RX 0x00010001
#define GPIO_PB0_T2CCP0 0x00010007
#define GPIO_PB1_U1TX 0x00010401
#define GPIO_PB1_T2CCP1 0x00010407
#define GPIO_PB2_I2C0SCL 0x00010803
#define GPIO_PB2_T3CCP0 0x00010807
#define GPIO_PB3_I2C0SDA 0x00010C03
#define GPIO_PB3_T3CCP1 0x00010C07
#define GPIO_PB4_SSI2CLK 0x00011002
#define GPIO_PB4_CAN0RX 0x00011008
#define GPIO_PB4_T1CCP0 0x00011007
#define GPIO_PB5_SSI2FSS 0x00011402
#define GPIO_PB5_CAN0TX 0x00011408
#define GPIO_PB5_T1CCP1 0x00011407
#define GPIO_PB6_SSI2RX 0x00011802
#define GPIO_PB6_T0CCP0 0x00011807
#define GPIO_PB7_SSI2TX 0x00011C02
#define GPIO_PB7_T0CCP1 0x00011C07
#define GPIO_PC0_TCK 0x00020001
#define GPIO_PC0_SWCLK 0x00020001
#define GPIO_PC0_T4CCP0 0x00020007
#define GPIO_PC1_TMS 0x00020401
#define GPIO_PC1_SWDIO 0x00020401
#define GPIO_PC1_T4CCP1 0x00020407
#define GPIO_PC2_TDI 0x00020801
#define GPIO_PC2_T5CCP0 0x00020807
#define GPIO_PC3_SWO 0x00020C01
#define GPIO_PC3_TDO 0x00020C01
#define GPIO_PC3_T5CCP1 0x00020C07
#define GPIO_PC4_U4RX 0x00021001
#define GPIO_PC4_U1RX 0x00021002
#define GPIO_PC4_WT0CCP0 0x00021007
#define GPIO_PC4_U1RTS 0x00021008
#define GPIO_PC5_U4TX 0x00021401
#define GPIO_PC5_U1TX 0x00021402
#define GPIO_PC5_WT0CCP1 0x00021407
#define GPIO_PC5_U1CTS 0x00021408
#define GPIO_PC6_U3RX 0x00021801
#define GPIO_PC6_WT1CCP0 0x00021807
#define GPIO_PC7_U3TX 0x00021C01
#define GPIO_PC7_WT1CCP1 0x00021C07
#define GPIO_PD0_SSI3CLK 0x00030001
#define GPIO_PD0_SSI1CLK 0x00030002
#define GPIO_PD0_I2C3SCL 0x00030003
#define GPIO_PD0_WT2CCP0 0x00030007
#define GPIO_PD1_SSI3FSS 0x00030401
#define GPIO_PD1_SSI1FSS 0x00030402
#define GPIO_PD1_I2C3SDA 0x00030403
#define GPIO_PD1_WT2CCP1 0x00030407
#define GPIO_PD2_SSI3RX 0x00030801
#define GPIO_PD2_SSI1RX 0x00030802
#define GPIO_PD2_WT3CCP0 0x00030807
#define GPIO_PD3_SSI3TX 0x00030C01
#define GPIO_PD3_SSI1TX 0x00030C02
#define GPIO_PD3_WT3CCP1 0x00030C07
#define GPIO_PD4_U6RX 0x00031001
#define GPIO_PD4_WT4CCP0 0x00031007
#define GPIO_PD5_U6TX 0x00031401
#define GPIO_PD5_WT4CCP1 0x00031407
#define GPIO_PD6_U2RX 0x00031801
#define GPIO_PD6_WT5CCP0 0x00031807
#define GPIO_PD7_U2TX 0x00031C01
#define GPIO_PD7_WT5CCP1 0x00031C07
#define GPIO_PD7_NMI 0x00031C08
#define GPIO_PE0_U7RX 0x00040001
#define GPIO_PE1_U7TX 0x00040401
#define GPIO_PE4_U5RX 0x00041001
#define GPIO_PE4_I2C2SCL 0x00041003
#define GPIO_PE4_CAN0RX 0x00041008
#define GPIO_PE5_U5TX 0x00041401
#define GPIO_PE5_I2C2SDA 0x00041403
#define GPIO_PE5_CAN0TX 0x00041408
#define GPIO_PF0_U1RTS 0x00050001
#define GPIO_PF0_SSI1RX 0x00050002
#define GPIO_PF0_CAN0RX 0x00050003
#define GPIO_PF0_T0CCP0 0x00050007
#define GPIO_PF0_NMI 0x00050008
#define GPIO_PF0_C0O 0x00050009
#define GPIO_PF0_TRD2 0x0005000E
#define GPIO_PF1_U1CTS 0x00050401
#define GPIO_PF1_SSI1TX 0x00050402
#define GPIO_PF1_T0CCP1 0x00050407
#define GPIO_PF1_C1O 0x00050409
#define GPIO_PF1_TRD1 0x0005040E
#define GPIO_PF2_T1CCP0 0x00050807
#define GPIO_PF2_SSI1CLK 0x00050802
#define GPIO_PF2_TRD0 0x0005080E
#define GPIO_PF3_CAN0TX 0x00050C03
#define GPIO_PF3_T1CCP1 0x00050C07
#define GPIO_PF3_SSI1FSS 0x00050C02
#define GPIO_PF3_TRCLK 0x00050C0E
#define GPIO_PF4_T2CCP0 0x00051007
#endif // PART_LM4F120H5QR
//*****************************************************************************
//
// Pin Mapping Functions
//
// This section describes the code that is responsible for handling the
// mapping of peripheral functions to their physical location on the pins of
// a device.
//
//*****************************************************************************
//*****************************************************************************
//
// Definitions to support mapping GPIO Ports and Pins to their function.
//
//*****************************************************************************
//*****************************************************************************
//
// Configures the specified ADC pin to function as an ADC pin.
//
// \param ulName is one of the valid names for the ADC pins.
//
// This function takes on of the valid names for an ADC pin and configures
// the pin for its ADC functionality depending on the part that is defined.
//
// The valid names for the pins are as follows: \b ADC0, \b ADC1, \b ADC2,
// \b ADC3, \b ADC4, \b ADC5, \b ADC6, or \b ADC7.
//
// \sa GPIOPinTypeADC() in order to configure multiple ADC pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeADC(ulName) GPIOPinTypeADC(ulName##_PORT, ulName##_PIN)
//*****************************************************************************
//
// Configures the specified CAN pin to function as a CAN pin.
//
// \param ulName is one of the valid names for the CAN pins.
//
// This function takes one of the valid names for a CAN pin and configures
// the pin for its CAN functionality depending on the part that is defined.
//
// The valid names for the pins are as follows: \b CAN0RX, \b CAN0TX,
// \b CAN1RX, \b CAN1TX, \b CAN2RX, or \b CAN2TX.
//
// \sa GPIOPinTypeCAN() in order to configure multiple CAN pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeCAN(ulName) GPIOPinTypeCAN(ulName##_PORT, ulName##_PIN)
//*****************************************************************************
//
// Configures the specified comparator pin to function as a comparator pin.
//
// \param ulName is one of the valid names for the Comparator pins.
//
// This function takes one of the valid names for a comparator pin and
// configures the pin for its comparator functionality depending on the part
// that is defined.
//
// The valid names for the pins are as follows: \b C0_MINUS, \b C0_PLUS,
// \b C1_MINUS, \b C1_PLUS, \b C2_MINUS, or \b C2_PLUS.
//
// \sa GPIOPinTypeComparator() in order to configure multiple comparator pins
// at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeComparator(ulName) \
GPIOPinTypeComparator(ulName##_PORT, \
ulName##_PIN)
//*****************************************************************************
//
// Configures the specified I2C pin to function as an I2C pin.
//
// \param ulName is one of the valid names for the I2C pins.
//
// This function takes one of the valid names for an I2C pin and configures
// the pin for its I2C functionality depending on the part that is defined.
//
// The valid names for the pins are as follows: \b I2C0SCL, \b I2C0SDA,
// \b I2C1SCL, or \b I2C1SDA.
//
// \sa GPIOPinTypeI2C() in order to configure multiple I2C pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeI2C(ulName) GPIOPinTypeI2C(ulName##_PORT, ulName##_PIN)
//*****************************************************************************
//
// Configures the specified Ethernet LED to function as an Ethernet LED pin.
//
// \param ulName is one of the valid names for the Ethernet LED pins.
//
// This function takes one of the valid names for an Ethernet LED pin and
// configures the pin for its Ethernet LED functionality depending on the part
// that is defined.
//
// The valid names for the pins are as follows: \b LED0 or \b LED1.
//
// sa GPIOPinTypeEthernetLED() in order to configure multiple Ethernet LED
// pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeEthernetLED(ulName) \
GPIOPinTypeEthernetLED(ulName##_PORT, \
ulName##_PIN)
//*****************************************************************************
//
// Configures the specified PWM pin to function as a PWM pin.
//
// \param ulName is one of the valid names for the PWM pins.
//
// This function takes one of the valid names for a PWM pin and configures
// the pin for its PWM functionality depending on the part that is defined.
//
// The valid names for the pins are as follows: \b PWM0, \b PWM1, \b PWM2,
// \b PWM3, \b PWM4, \b PWM5, or \b FAULT.
//
// \sa GPIOPinTypePWM() in order to configure multiple PWM pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypePWM(ulName) GPIOPinTypePWM(ulName##_PORT, ulName##_PIN)
//*****************************************************************************
//
// Configures the specified QEI pin to function as a QEI pin.
//
// \param ulName is one of the valid names for the QEI pins.
//
// This function takes one of the valid names for a QEI pin and configures
// the pin for its QEI functionality depending on the part that is defined.
//
// The valid names for the pins are as follows: \b PHA0, \b PHB0, \b IDX0,
// \b PHA1, \b PHB1, or \b IDX1.
//
// \sa GPIOPinTypeQEI() in order to configure multiple QEI pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeQEI(ulName) GPIOPinTypeQEI(ulName##_PORT, ulName##_PIN)
//*****************************************************************************
//
// Configures the specified SSI pin to function as an SSI pin.
//
// \param ulName is one of the valid names for the SSI pins.
//
// This function takes one of the valid names for an SSI pin and configures
// the pin for its SSI functionality depending on the part that is defined.
//
// The valid names for the pins are as follows: \b SSI0CLK, \b SSI0FSS,
// \b SSI0RX, \b SSI0TX, \b SSI1CLK, \b SSI1FSS, \b SSI1RX, or \b SSI1TX.
//
// \sa GPIOPinTypeSSI() in order to configure multiple SSI pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeSSI(ulName) GPIOPinTypeSSI(ulName##_PORT, ulName##_PIN)
//*****************************************************************************
//
// Configures the specified Timer pin to function as a Timer pin.
//
// \param ulName is one of the valid names for the Timer pins.
//
// This function takes one of the valid names for a Timer pin and configures
// the pin for its Timer functionality depending on the part that is defined.
//
// The valid names for the pins are as follows: \b CCP0, \b CCP1, \b CCP2,
// \b CCP3, \b CCP4, \b CCP5, \b CCP6, or \b CCP7.
//
// \sa GPIOPinTypeTimer() in order to configure multiple CCP pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeTimer(ulName) GPIOPinTypeTimer(ulName##_PORT, ulName##_PIN)
//*****************************************************************************
//
// Configures the specified UART pin to function as a UART pin.
//
// \param ulName is one of the valid names for the UART pins.
//
// This function takes one of the valid names for a UART pin and configures
// the pin for its UART functionality depending on the part that is defined.
//
// The valid names for the pins are as follows: \b U0RX, \b U0TX, \b U1RX,
// \b U1TX, \b U2RX, or \b U2TX.
//
// \sa GPIOPinTypeUART() in order to configure multiple UART pins at once.
//
// \return None.
//
//*****************************************************************************
#define PinTypeUART(ulName) GPIOPinTypeUART(ulName##_PORT, ulName##_PIN)
//*****************************************************************************
//
//! Configures the specified USB digital pin to function as a USB pin.
//!
//! \param ulName is one of the valid names for a USB digital pin.
//!
//! This function takes one of the valid names for a USB digital pin and
//! configures the pin for its USB functionality depending on the part that is
//! defined.
//!
//! The valid names for the pins are as follows: \b EPEN or \b PFAULT.
//!
//! \sa GPIOPinTypeUSBDigital() in order to configure multiple USB pins at
//! once.
//!
//! \return None.
//
//*****************************************************************************
#define PinTypeUSBDigital(ulName) \
GPIOPinTypeUSBDigital(ulName##_PORT, \
ulName##_PIN)
//*****************************************************************************
//
//! Enables the peripheral port used by the given pin.
//!
//! \param ulName is one of the valid names for a pin.
//!
//! This function takes one of the valid names for a pin function and
//! enables the peripheral port for that pin depending on the part that is
//! defined.
//!
//! Any valid pin name can be used.
//!
//! \sa SysCtlPeripheralEnable() in order to enable a single port when
//! multiple pins are on the same port.
//!
//! \return None.
//
//*****************************************************************************
#define PeripheralEnable(ulName) \
SysCtlPeripheralEnable(ulName##_PERIPH)
#endif // __PIN_MAP_H__

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//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PWM_H__
#define __PWM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ulConfig
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
#define PWM_GEN_MODE_FAULT_LATCHED \
0x00040000 // Fault is latched
#define PWM_GEN_MODE_FAULT_UNLATCHED \
0x00000000 // Fault is not latched
#define PWM_GEN_MODE_FAULT_MINPER \
0x00020000 // Enable min fault period
#define PWM_GEN_MODE_FAULT_NO_MINPER \
0x00000000 // Disable min fault period
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
#define PWM_GEN_MODE_FAULT_LEGACY \
0x00000000 // Disable extended fault support
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
// immediately
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
0x0000A800 // Deadband updates locally
// synchronized
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
0x0000FC00 // Deadband updates globally
// synchronized
#define PWM_GEN_MODE_GEN_NO_SYNC \
0x00000000 // Generator mode updates occur
// immediately
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
0x00000280 // Generator mode updates locally
// synchronized
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
0x000003C0 // Generator mode updates globally
// synchronized
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
#ifndef DEPRECATED
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
#endif
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_0.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_0 0
#define PWM_FAULT_FAULT0 0x00000001
#define PWM_FAULT_FAULT1 0x00000002
#define PWM_FAULT_FAULT2 0x00000004
#define PWM_FAULT_FAULT3 0x00000008
#define PWM_FAULT_ACMP0 0x00010000
#define PWM_FAULT_ACMP1 0x00020000
#define PWM_FAULT_ACMP2 0x00040000
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_1.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_1 1
#define PWM_FAULT_DCMP0 0x00000001
#define PWM_FAULT_DCMP1 0x00000002
#define PWM_FAULT_DCMP2 0x00000004
#define PWM_FAULT_DCMP3 0x00000008
#define PWM_FAULT_DCMP4 0x00000010
#define PWM_FAULT_DCMP5 0x00000020
#define PWM_FAULT_DCMP6 0x00000040
#define PWM_FAULT_DCMP7 0x00000080
//*****************************************************************************
//
// Defines to identify the sense of each of the external FAULTn signals
//
//*****************************************************************************
#define PWM_FAULT0_SENSE_HIGH 0x00000000
#define PWM_FAULT0_SENSE_LOW 0x00000001
#define PWM_FAULT1_SENSE_HIGH 0x00000000
#define PWM_FAULT1_SENSE_LOW 0x00000002
#define PWM_FAULT2_SENSE_HIGH 0x00000000
#define PWM_FAULT2_SENSE_LOW 0x00000004
#define PWM_FAULT3_SENSE_HIGH 0x00000000
#define PWM_FAULT3_SENSE_LOW 0x00000008
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulConfig);
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulPeriod);
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
unsigned long ulGen);
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
unsigned long ulWidth);
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
unsigned long ulPWMOut);
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
unsigned short usRise, unsigned short usFall);
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bEnable);
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bInvert);
extern void PWMOutputFaultLevel(unsigned long ulBase,
unsigned long ulPWMOutBits,
tBoolean bDriveHigh);
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bFaultSuppress);
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
void (*pfnIntHandler)(void));
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
extern void PWMFaultIntRegister(unsigned long ulBase,
void (*pfnIntHandler)(void));
extern void PWMFaultIntUnregister(unsigned long ulBase);
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
tBoolean bMasked);
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulInts);
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMFaultIntClear(unsigned long ulBase);
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void PWMFaultIntClearExt(unsigned long ulBase,
unsigned long ulFaultInts);
extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulMinFaultPeriod,
unsigned long ulFaultSenses);
extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulGroup,
unsigned long ulFaultTriggers);
extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
unsigned long ulGen,
unsigned long ulGroup);
extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
unsigned long ulGen,
unsigned long ulGroup);
extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulGroup,
unsigned long ulFaultTriggers);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PWM_H__

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This project will build the Stellaris Peripheral Driver Library.
-------------------------------------------------------------------------------
Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
Software License Agreement
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This is part of revision 9453 of the Stellaris Peripheral Driver Library.

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//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half full or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or more
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfigSetExpClk.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
//
//*****************************************************************************
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values that can be passed to SSIClockSourceSet() or returned from
// SSIClockSourceGet().
//
//*****************************************************************************
#define SSI_CLOCK_SYSTEM 0x00000000
#define SSI_CLOCK_PIOSC 0x00000005
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SSIDataGetNonBlocking(unsigned long ulBase,
unsigned long *pulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern tBoolean SSIBusy(unsigned long ulBase);
extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long SSIClockSourceGet(unsigned long ulBase);
//*****************************************************************************
//
// Several SSI APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define SSIConfig(a, b, c, d, e) \
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
#define SSIDataNonBlockingGet(a, b) \
SSIDataGetNonBlocking(a, b)
#define SSIDataNonBlockingPut(a, b) \
SSIDataPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__

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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#ifndef DEPRECATED
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#endif
#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
#ifndef DEPRECATED
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#endif
#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
#ifndef DEPRECATED
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#endif
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#endif
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#endif
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
#define SYSCTL_PERIPH_ETH 0x20105000 // Ethernet
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0
#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1
#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0
#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1
#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2
#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
#define SYSCTL_PERIPH2_EPI0 0xf0001000 // EPI0
#define SYSCTL_PERIPH2_ETH 0xf0002c00 // ETH
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A
#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B
#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C
#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D
#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E
#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F
#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G
#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H
#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module
#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0
#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
#define SYSCTL_PERIPH2_I2S0 0xf0002400 // I2S0
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0
#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1
#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0
#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0
#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1
#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2
#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0
#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1
#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA
#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0
#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0
#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1
#define SYSCTL_PERIPH2_HIBERNATE \
0xf0001400 // Hibernate
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
extern void SysCtlUSBPLLEnable(void);
extern void SysCtlUSBPLLDisable(void);
extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
unsigned long ulMClk);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

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//*****************************************************************************
//
// sysexc.h - Prototypes for the System Exception Module routines.
//
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSEXC_H__
#define __SYSEXC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and
// SysExcIntClear as the ulIntFlags parameter, and returned from
// SysExcIntStatus.
//
//*****************************************************************************
#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt
#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt
#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt
#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt
#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int
#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void SysExcIntRegister(void (*pfnHandler)(void));
extern void SysExcIntUnregister(void);
extern void SysExcIntEnable(unsigned long ulIntFlags);
extern void SysExcIntDisable(unsigned long ulIntFlags);
extern unsigned long SysExcIntStatus(tBoolean bMasked);
extern void SysExcIntClear(unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSEXC_H__

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//*****************************************************************************
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

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//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
// timer
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
// timer
#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Values that can be passed to TimerSynchronize as the ulTimers parameter.
//
//*****************************************************************************
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A
#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B
#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A
#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B
#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A
#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B
#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A
#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B
#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A
#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B
#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A
#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B
#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A
#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B
#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A
#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerControlWaitOnTrigger(unsigned long ulBase,
unsigned long ulTimer,
tBoolean bWait);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern void TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue);
extern unsigned long long TimerLoadGet64(unsigned long ulBase);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern unsigned long long TimerValueGet64(unsigned long ulBase);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue);
extern unsigned long long TimerMatchGet64(unsigned long ulBase);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerSynchronize(unsigned long ulBase, unsigned long ulTimers);
//*****************************************************************************
//
// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
// instead to return the timer to its reset state.
//
//*****************************************************************************
#ifndef DEPRECATED
extern void TimerQuiesce(unsigned long ulBase);
#endif
//*****************************************************************************
//
// These values for TimerConfigure have been deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
#define TIMER_CFG_32_BIT_OS 0x00000021 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_OS_UP 0x00000031 // 32-bit one-shot up-count timer
#define TIMER_CFG_32_BIT_PER 0x00000022 // 32-bit periodic timer
#define TIMER_CFG_32_BIT_PER_UP 0x00000032 // 32-bit periodic up-count timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
// UARTParityModeSet as the ulParity parameter, and are returned by
// UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
// returned by UARTFIFOLevelGet in the pulTxLevel.
//
//*****************************************************************************
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
// returned by UARTFIFOLevelGet in the pulRxLevel.
//
//*****************************************************************************
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
//
//*****************************************************************************
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values returned from UARTRxErrorGet().
//
//*****************************************************************************
#define UART_RXERROR_OVERRUN 0x00000008
#define UART_RXERROR_BREAK 0x00000004
#define UART_RXERROR_PARITY 0x00000002
#define UART_RXERROR_FRAMING 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTHandshakeOutputsSet() or returned from
// UARTHandshakeOutputGet().
//
//*****************************************************************************
#define UART_OUTPUT_RTS 0x00000800
#define UART_OUTPUT_DTR 0x00000400
//*****************************************************************************
//
// Values that can be returned from UARTHandshakeInputsGet().
//
//*****************************************************************************
#define UART_INPUT_RI 0x00000100
#define UART_INPUT_DCD 0x00000004
#define UART_INPUT_DSR 0x00000002
#define UART_INPUT_CTS 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTFlowControl() or returned from
// UARTFlowControlGet().
//
//*****************************************************************************
#define UART_FLOWCONTROL_TX 0x00008000
#define UART_FLOWCONTROL_RX 0x00004000
#define UART_FLOWCONTROL_NONE 0x00000000
//*****************************************************************************
//
// Values that can be passed to UARTTxIntModeSet() or returned from
// UARTTxIntModeGet().
//
//*****************************************************************************
#define UART_TXINT_MODE_FIFO 0x00000000
#define UART_TXINT_MODE_EOT 0x00000010
//*****************************************************************************
//
// Values that can be passed to UARTClockSourceSet() or returned from
// UARTClockSourceGet().
//
//*****************************************************************************
#define UART_CLOCK_SYSTEM 0x00000000
#define UART_CLOCK_PIOSC 0x00000005
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long ulBaud, unsigned long ulConfig);
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern void UARTFIFOEnable(unsigned long ulBase);
extern void UARTFIFODisable(unsigned long ulBase);
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
extern void UARTDisableSIR(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharGetNonBlocking(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern tBoolean UARTBusy(unsigned long ulBase);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
extern void UARTRxErrorClear(unsigned long ulBase);
extern void UARTSmartCardEnable(unsigned long ulBase);
extern void UARTSmartCardDisable(unsigned long ulBase);
extern void UARTModemControlSet(unsigned long ulBase,
unsigned long ulControl);
extern void UARTModemControlClear(unsigned long ulBase,
unsigned long ulControl);
extern unsigned long UARTModemControlGet(unsigned long ulBase);
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long UARTClockSourceGet(unsigned long ulBase);
extern void UART9BitEnable(unsigned long ulBase);
extern void UART9BitDisable(unsigned long ulBase);
extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
unsigned char ucMask);
extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr);
//*****************************************************************************
//
// Several UART APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define UARTConfigSet(a, b, c) \
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
#define UARTConfigGet(a, b, c) \
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
#define UARTCharNonBlockingGet(a) \
UARTCharGetNonBlocking(a)
#define UARTCharNonBlockingPut(a, b) \
UARTCharPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

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//*****************************************************************************
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The type of interrupt that can be generated by the watchdog.
//
//*****************************************************************************
#define WATCHDOG_INT_TYPE_INT 0x00000000
#define WATCHDOG_INT_TYPE_NMI 0x00000004
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogResetEnable(unsigned long ulBase);
extern void WatchdogResetDisable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__

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custody or control and provide to TI a written statement signed by your authorized
representative certifying such destruction. The following sections will survive any
expiration or termination of this Agreement: 2(h) (Termination), 3 (Licensed Materials
Ownership), 6 (Warranties and Limitations), 7 (Indemnification Disclaimer), 10 (Export
Control), 11 (Governing Law and Severability), 12 (PRC Provisions), and 13 (Entire
Agreement). The obligations set forth in Section 5 (Confidential Information) will
survive any expiration or termination of this Agreement for three (3) years after
such expiration or termination.
</p>
<p>3. <b>Licensed Materials Ownership.</b> The Licensed Materials are licensed, not sold to you, and can only be used in accordance
with the terms of this Agreement. Subject to the licenses granted to you pursuant
to this Agreement, TI and TI's licensors own and shall continue to own all right,
title, and interest in and to the Licensed Materials, including all copies thereof.
The parties agree that all fixes, modifications and improvements to the Licensed Materials
conceived of or made by TI that are based, either in whole or in part, on your feedback,
suggestions or recommendations are the exclusive property of TI and all right, title
and interest in and to such fixes, modifications or improvements to the Licensed Materials
will vest solely in TI. Moreover, you acknowledge and agree that when your independently
developed software or hardware components are combined, in whole or in part, with
the Licensed Materials, your right to use the Licensed Materials embodied in such
resulting combined work shall remain subject to the terms and conditions of this Agreement.
</p>
<p>4. <b>Intellectual Property Rights.</b>
</p>
<p>a. The Licensed Materials contain copyrighted material, trade secrets and other proprietary
information of TI and TI's licensors and are protected by copyright laws, international
copyright treaties, and trade secret laws, as well as other intellectual property
laws. To protect TI's and TI's licensors' rights in the Licensed Materials, you agree,
except as specifically permitted by statute by a provision that cannot be waived by
contract, not to "unlock", decompile, reverse engineer, disassemble or otherwise translate
any portions of the Licensed Materials to a human-perceivable form nor to permit any
person or entity to do so. You shall not remove, alter, cover, or obscure any confidentiality,
trade secret, proprietary, or copyright notices, trade-marks, proprietary, patent,
or other identifying marks or designs from any component of the Licensed Materials
and you shall reproduce and include in all copies of the Licensed Materials the copyright
notice(s) and proprietary legend(s) of TI and TI's licensors as they appear in the
Licensed Materials. TI reserves all rights not specifically granted under this Agreement.
</p>
<p>b. Third parties may claim to own patents, copyrights, or other intellectual property
rights that cover the implementation of certain Licensed Materials. Certain Licensed
Materials may also be based on industry recognized standards, including but not limited
to specifically the ISO MPEG and ITU standards, and software programs published by
industry recognized standards bodies and certain third parties claim to own patents,
copyrights, and other intellectual property rights that cover implementation of those
standards. You acknowledge and agree that this Agreement does not convey a license
to any such third party patents, copyrights, and other intellectual property rights
and that you are solely responsible for any patent, copyright, or other intellectual
property right claims that relate to your use and distribution of the Licensed Materials,
and your use and distribution of your products that include or incorporate the Licensed
Materials.
</p>
<p>5. <b>Confidential Information.</b> You acknowledge and agree that the Licensed Materials contain trade secrets and other
confidential information of TI and TI's licensors. You agree to use the Licensed Materials
solely within the scope of the licenses set forth herein, to maintain the Licensed
Materials in strict confidence, to use at least the same procedures and degree of
care that you use to prevent disclosure of your own confidential information of like
importance but in no instance less than reasonable care, and to prevent disclosure
of the Licensed Materials to any third party, except as may be necessary and required
in connection with your rights and obligations hereunder. You agree to obtain executed
confidentiality agreements with your employees and contractors having access to the
Licensed Materials and to diligently take steps to enforce such agreements in this
respect. TI agrees that the employment agreements used in the normal course of your
business shall satisfy the requirements of this section. TI may disclose your contact
information to TI's applicable licensors.
</p>
<p>6. <b>Warranties and Limitations.</b> YOU ACKNOWLEDGE AND AGREE THAT THE LICENSED MATERIALS MAY NOT BE INTENDED FOR PRODUCTION
APPLICATIONS AND MAY CONTAIN IRREGULARITIES AND DEFECTS NOT FOUND IN PRODUCTION SOFTWARE.
FURTHERMORE, YOU ACKNOWLEDGE AND AGREE THAT THE LICENSED MATERIALS HAVE NOT BEEN TESTED
OR CERTIFIED BY ANY GOVERNMENT AGENCY OR INDUSTRY REGULATORY ORGANIZATION OR ANY OTHER
THIRD PARTY ORGANIZATION. YOU AGREE THAT PRIOR TO USING, INCORPORATING OR DISTRIBUTING
THE LICENSED MATERIALS IN OR WITH ANY COMMERCIAL PRODUCT THAT YOU WILL THOROUGHLY
TEST THE PRODUCT AND THE FUNCTIONALITY OF THE LICENSED MATERIALS IN OR WITH THAT PRODUCT
AND BE SOLELY RESPONSIBLE FOR ANY PROBLEMS OR FAILURES.
</p>
<p>THE LICENSED MATERIALS AND ANY REALTED DOCUMENTATION ARE PROVIDED "AS IS" AND WITH
ALL FAULTS. TI MAKES NO WARRANTY OR REPRESENTATION, WHETHER EXPRESS, IMPLIED OR STATUTORY,
REGARDING THE LICENSED MATERIALS, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY
OR COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. TI DISCLAIMS ANY WARRANTY
OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY
PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. YOU AGREE
TO USE YOUR INDEPENDENT JUDGMENT IN DEVELOPING YOUR PRODUCTS. NOTHING CONTAINED IN
THIS AGREEMENT WILL BE CONSTRUED AS A WARRANTY OR REPRESENTATION BY TI TO MAINTAIN
PRODUCTION OF ANY TI SEMICONDUCTOR DEVICE OR OTHER HARDWARE OR SOFTWARE WITH WHICH
THE LICENSED MATERIALS MAY BE USED.
</p>
<p>IN NO EVENT SHALL TI, OR ANY APPLICABLE LICENSOR, BE LIABLE FOR ANY SPECIAL, INDIRECT,
INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED, ON ANY THEORY OF LIABILITY,
IN CONNECTION WITH OR ARISING OUT OF THIS AGREEMENT OR THE USE OF THE LICENSED MATERIALS,
REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, OUTSIDE
COMPUTER TIME, LABOR COSTS, LOSS OF DATA, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS
OF SAVINGS, OR LOSS OF USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S AGGREGATE
LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF YOUR USE OF THE LICENSED MATERIALS
EXCEED FIVE HUNDRED U.S. DOLLARS (US$500). THE EXISTENCE OF MORE THAN ONE CLAIM WILL
NOT ENLARGE OR EXTEND THESE LIMITS.
</p>
<p>Because some jurisdictions do not allow the exclusion or limitation of incidental
or consequential damages or limitation on how long an implied warranty lasts, the
above limitations or exclusions may not apply to you.
</p>
<p>7. <b>Indemnification Disclaimer.</b> YOU ACKNOWLEDGE AND AGREE THAT TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR
INDEMNIFY YOU AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED
ON YOUR MANUFACTURE, USE, OR DISTRIBUTION OF THE LICENSED MATERIALS OR YOUR MANUFACTURE,
USE, OFFER FOR SALE, SALE, IMPORTATION OR DISTRIBUTION OF YOUR PRODUCTS THAT INCLUDE
OR INCORPORATE THE LICENSED MATERIALS.
</p>
<p>You will defend and indemnify TI in the event of claim, liability or costs (including
reasonable attorney's fees related to Your use or any sub-licensee's use of the Licensed
Materials) relating in any way to Your violation of the terms of the License Grants
set forth in Section 2, or any other violation of other terms and conditions of this
Agreement.
</p>
<p>8. <b>No Technical Support.</b> TI and TI's licensors are under no obligation to install, maintain or support the
Licensed Materials.
</p>
<p>9. <b>Notices.</b> All notices to TI hereunder shall be delivered to Texas Instruments Incorporated,
AEC Software Operations, 12203 Southwest Freeway, Mail Station 701, Stafford, Texas
77477, Attention: Administrator, AEC Software Operations, with a copy to Texas Instruments
Incorporated, 12203 Southwest Freeway, Mail Station 725, Stafford, Texas 77477, Attention:
Legal Department. All notices shall be deemed served when received by TI.
</p>
<p>10. <b>Export Control.</b> You hereby acknowledge that the Licensed Materials are subject to export control under
the U.S. Commerce Department's Export Administration Regulations ("EAR"). You further
hereby acknowledge and agree that unless prior authorization is obtained from the
U.S. Commerce Department, neither you nor your customers will export, re-export, or
release, directly or indirectly, any technology, software, or software source code
(as defined in Part 772 of the EAR), received from TI, or export, directly or indirectly,
any direct product of such technology, software, or software source code (as defined
in Part 734 of the EAR), to any destination or country to which the export, re-export,
or release of the technology, software, or software source code, or direct product
is prohibited by the EAR. You agree that none of the Licensed Materials may be downloaded
or otherwise exported or reexported (i) into (or to a national or resident of) Cuba,
Iran, North Korea, Sudan and Syria or any other country the U.S. has embargoed goods;
or (ii) to anyone on the U.S. Treasury Department's List of Specially Designated Nationals
or the U.S. Commerce Department's Denied Persons List or Entity List. You represent
and warrant that you are not located in, under the control of, or a national or resident
of any such country or on any such list and you will not use or transfer the Licensed
Materials for use in any sensitive nuclear, chemical or biological weapons, or missile
technology end-uses unless authorized by the U.S. Government by regulation or specific
license or for a military end-use in, or by any military entity of Albania, Armenia,
Azerbaijan, Belarus, Cambodia, China, Georgia, Iran, Iraq, Kazakhstan, Kyrgyzstan,
Laos, Libya, Macau, Moldova, Mongolia, Russia, Tajikistan, Turkmenistan, Ukraine,
Uzbekistan, and Vietnam. Any software export classification made by TI shall be for
TI's internal use only and shall not be construed as a representation or warranty
regarding the proper export classification for such software or whether an export
license or other documentation is required for the exportation of such software.
</p>
<p>11. <b>Governing Law and Severability.</b> This Agreement will be governed by and interpreted in accordance with the laws of
the State of Texas, without reference to conflict of laws principles. If for any reason
a court of competent jurisdiction finds any provision of the Agreement to be unenforceable,
that provision will be enforced to the maximum extent possible to effectuate the intent
of the parties, and the remainder of the Agreement shall continue in full force and
effect. This Agreement shall not be governed by the United Nations Convention on Contracts
for the International Sale of Goods, or by the Uniform Computer Information Transactions
Act (UCITA), as it may be enacted in the State of Texas. The parties agree that non-exclusive
jurisdiction for any dispute arising out of or relating to this Agreement lies within
the courts located in the State of Texas. Notwithstanding the foregoing, any judgment
may be enforced in any United States or foreign court, and either party may seek injunctive
relief in any United States or foreign court.
</p>
<p>12. <b>PRC Provisions.</b> If you are located in the People's Republic of China ("PRC") or if the Licensed Materials
will be sent to the PRC, the following provisions shall apply and shall supersede
any other provisions in this Agreement concerning the same subject matter as the following
provisions:
</p>
<p>a. <em>Registration Requirements.</em> You shall be solely responsible for performing all acts and obtaining all approvals
that may be required in connection with this Agreement by the government of the PRC,
including but not limited to registering pursuant to, and otherwise complying with,
the PRC Measures on the Administration of Software Products, Management Regulations
on Technology Import-Export, and Technology Import and Export Contract Registration
Management Rules. Upon receipt of such approvals from the government authorities,
you shall forward evidence of all such approvals to TI for its records. In the event
that you fail to obtain any such approval or registration, you shall be solely responsible
for any and all losses, damages or costs resulting therefrom, and shall indemnify
TI for all such losses, damages or costs.
</p>
<p>b. <em>Governing Language.</em> This Agreement is written and executed in the English language. If a translation of
this Agreement is required for any purpose, including but not limited to registration
of the Agreement pursuant to any governmental laws, regulations or rules, you shall
be solely responsible for creating such translation. Any translation of this Agreement
into a language other than English is intended solely in order to comply with such
laws or for reference purposes, and the English language version shall be authoritative
and controlling.
</p>
<p>c. <em>Export Control.</em>
</p>
<p>(i). <em>Diversions of Technology.</em> You hereby agree that unless prior authorization is obtained from the U.S. Department
of Commerce, neither you nor your subsidiaries or affiliates shall knowingly export,
re-export, or release, directly or indirectly, any technology, software, or software
source code (as defined in Part 772 of the Export Administration Regulations of the
U.S. Department of Commerce ("EAR")), received from TI or any of its affiliated companies,
or export, directly or indirectly, any direct product of such technology, software,
or software source code (as defined in Part 734 of the EAR), to any destination or
country to which the export, re-export, or release of the technology, software, software
source code, or direct product is prohibited by the EAR.
</p>
<p>(ii). <em>Assurance of Compliance.</em> You understand and acknowledge that products, technology (regardless of the form in
which it is provided), software or software source code, received from TI or any of
its affiliates under this Agreement may be under export control of the United States
or other countries. You shall comply with the United States and other applicable non-U.S.
laws and regulations governing the export, re-export and release of any products,
technology, software, or software source code received under this Agreement from TI
or its affiliates. You shall not undertake any action that is prohibited by the EAR.
Without limiting the generality of the foregoing, you specifically agree that you
shall not transfer or release products, technology, software, or software source code
of TI or its affiliates to, or for use by, military end users or for use in military,
missile, nuclear, biological, or chemical weapons end uses.
</p>
<p>(iii). <em>Licenses.</em> Each party shall secure at its own expense, such licenses and export and import documents
as are necessary for each respective party to fulfill its obligations under this Agreement.
If such licenses or government approvals cannot be obtained, TI may terminate this
Agreement, or shall otherwise be excused from the performance of any obligations it
may have under this Agreement for which the licenses or government approvals are required.
</p>
<p>13. <b>Entire Agreement.</b> This is the entire Agreement between you and TI, and absent a signed and effective
software license agreement related to the subject matter of this Agreement, this Agreement
supersedes any prior agreement between the parties related to the subject matter of
this Agreement. Notwithstanding the foregoing, any signed and effective software license
agreement relating to the subject matter hereof will supersede the terms of this Agreement.
No amendment or modification of this Agreement will be effective unless in writing
and signed by a duly authorized representative of TI. You hereby warrant and represent
that you have obtained all authorizations and other applicable consents required empowering
you to enter into this Agreement.
</p>
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