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Commit Graph

78 Commits

Author SHA1 Message Date
Bas Stottelaar
fb61443bbd cpu/*: remove unused assert.h include 2020-10-22 11:13:09 +02:00
Bas Stottelaar
ab6188cea3 cpu/*: add missing include of assert.h 2020-10-22 11:13:08 +02:00
8df645cfe9
Merge pull request #15011 from benpicco/picolobc_feature
picolibc: model as a feature
2020-10-14 17:02:04 +02:00
Benjamin Valentin
45270dada0 cpu/fe310: blacklist picolibc on CI
The RISC-V toolchain in riotdocker has issues with picolibc and
will still include newlib headers.

This leads to conflicts like

```
In file included from [01m[Knanostubs.c:22[m[K:
[01m[K/usr/local/picolibc/riscv-none-embed/include/stdio.h:270:23:[m[K [01;31m[Kerror: [m[Kconflicting types for '[01m[K__FILE[m[K'
 typedef struct __file [01;31m[K__FILE[m[K;
                       [01;31m[K^~~~~~[m[K
In file included from [01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/reent.h:93[m[K,
                 from [01m[Knanostubs.c:20[m[K:
[01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/sys/reent.h:287:26:[m[K [01;36m[Knote: [m[Kprevious declaration of '[01m[K__FILE[m[K' was here
 typedef struct __sFILE   [01;36m[K__FILE[m[K;
                          [01;36m[K^~~~~~[m[K
```

The problem does not occur when installing both the toolchain and picolibc
directly from the Debian / Ubuntu repositories, but CI uses an older Ubuntu
version that does not have those packages yet, so it builds them manually.

Blacklist RISC-V until CI has been updated.
2020-10-14 16:32:01 +02:00
60f39ddba8
cpu/fe310: fix typo 'transfert' -> 'transfer' 2020-10-02 07:55:36 +02:00
Marian Buschsieweke
94eab47b26
cpu/fe310: Add architecture_arch.h 2020-09-29 12:34:00 +02:00
Benjamin Valentin
2647f5f3c2 cpu/fe310: run RTT at 1 Hz if RTC is selected
The RTC on the fe310 is emulated using the RTT.
This only works if the RTT frequency is 1 Hz, so default to that
value in case `periph_rtc` is selected.
2020-09-27 22:45:04 +02:00
a1473431da
Merge pull request #14878 from benpicco/cpu/fe310/rtc_mktime
cpu/fe310: RTC: use rtc_mktime()
2020-09-25 21:19:04 +02:00
Benjamin Valentin
d092c12a66 cpu/fe310: RTC: use rtc_mktime()
Use RTC helper functions instead of libc functions.
This gives us y2038 safety by the extended epoch and saves
a good chunk of memory:

picolibc mktime():

   text	   data	    bss	    dec	    hex	filename
  15048	    520	   2504	  18072	   4698	tests/periph_rtc/bin/hifive1/tests_periph_rtc.elf

rtc_mktime():

   text	   data	    bss	    dec	    hex	filename
   7632	     40	   2452	  10124	   278c	tests/periph_rtc/bin/hifive1/tests_periph_rtc.elf
2020-09-25 18:22:10 +02:00
Benjamin Valentin
cff8e862b8 picolibc: model as a feature 2020-09-15 22:11:21 +02:00
cdbb3e025a
cpu/fe310: boards/hifive1*: use IS_ACTIVE where possible 2020-09-09 14:14:39 +02:00
ace160a2a3
boards/hifive1: use MHZ utility macro for clock frequency 2020-09-09 14:14:39 +02:00
49e11626d3
cpu/fe310: ensure all clock modes are built 2020-09-09 14:14:39 +02:00
36ecb40dd9
Merge pull request #14919 from bergzand/pr/fe310/unify_ld
fe310: Unify linker scripts
2020-09-01 18:03:46 +02:00
32399901f0
fe310: Unify linker scripts
Similar to the cortex-m common linker scripts, the RISC-V linker scripts
can be unified easily, requiring only the memory addresses and lengths.
This simplifies adding new RISC-V CPU's later
2020-09-01 14:39:55 +02:00
53ac29aca4
Merge pull request #14887 from bergzand/pr/fe310/plic_periph
fe310: Add custom PLIC driver as peripheral
2020-08-31 21:25:03 +02:00
498646aa17
fe310: Remove vendor plic driver 2020-08-31 16:26:43 +02:00
bef82edf43
fe310: Adapt peripherals to use the plic driver 2020-08-31 16:26:43 +02:00
1d999a1335
fe310: Make header guard unique for plic vendor header
Otherwise it conflicts with the other plic.h header
2020-08-31 16:26:43 +02:00
3180a11b51
fe310: Add PLIC peripheral driver 2020-08-31 16:26:42 +02:00
889ea15936
fe310: Use read-modify-store instruction on GPIO
The rv32imac supports the A (atomic) extensions containing
read-modify-store operations. This commit modifies the GPIO code to use
these for all bitwise operations. The atomic operations are emitted with
relaxed ordering as they do not require multiprocessor synchronization.

This decreases the duration of the gpio operations from 59 ns to 50 ns
per call. depending a bit on the type of operation.
2020-08-29 09:24:02 +02:00
1e5dc928ad
fe310: Split sched_run call from handle_trap
This is a small optimization to the RISC-V trap handler. By splitting
the call to sched_run from the trap_handle call, loading the previous
thread ptr can be delayed until after it is determined that a schedule
run is required. This shaves of a few cycles during regular interrupts
that do not trigger the scheduler.
2020-08-28 14:17:58 +02:00
4289b09a33
fe310: Skip most context save on null thread 2020-08-28 14:17:56 +02:00
acf948a296
fe310: Only retrieve mepc and mtval on exception 2020-08-28 14:17:33 +02:00
503806cbb3
fe310: Only save caller-saved registers on regular trap
This commit reworks the trap entry to only save the callee-saved
registers when a context switch is required. the caller-saved registers
are always stored and restored to adhere to the RISC-V ABI. This saves
considerable cycles on interrupts.
2020-08-28 14:17:01 +02:00
343f183f05
fe310: Merge intr.S into irq_arch 2020-08-26 20:17:21 +02:00
32297a9818
fe310: Remove timer initialization from IRQ code
The RISC-V timer should only be touched by periph/timer and must not be
initialized and enabled by the IRQ code. The current code can cause an
unhandled interrupt when the timer is not used and the mtime register
hits UINT64_MAX.
2020-08-26 10:33:22 +02:00
Keith Packard
531050ada2 picolibc: Enable TLS support [v4]
Allocate and initialize a thread-local block for each thread at the
top of the stack.

Set the tls base when switching to a new thread.

Add tdata/tbss linker instructions to cortex_m and risc-v scripts.

Signed-off-by: Keith Packard <keithp@keithp.com>

---

v2:
	Squash fixes

v3:
	Replace tabs with spaces

v4:
	Add tbss to fe310 linker script
2020-08-24 08:26:16 -07:00
Keith Packard
a0d3436486 cpu/fe310: Add PICOLIBC support [v3]
Disable the newlib-nano stubs code when picolibc is in use

Signed-off-by: Keith Packard <keithp@keithp.com>

---
v2:
	Squash fixes in
v3:
	call stdio_init in _PICOLIBC_ mode to initialize uart
v3:
	Remove call to stdio_init from nanostubs_init, always
	call from cpu_init.
2020-08-24 08:24:54 -07:00
Keith Packard
76f6362292 cpu/fe310: Don't register __libc_fini_array with atexit
Picolibc makes atexit state per-thread instead of global, so we can't
register destructors with atexit in a non-thread context as we won't
have any TLS space initialized.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-08-23 13:13:28 -07:00
Marian Buschsieweke
346fb432ed
cpu/fe310: Don't access sched_active_*
Replaced accesses to sched_active_* with API calls in C files
2020-08-17 12:16:07 +02:00
Francisco Molina
442b11d0ee
cpu/fe310: add unified rtt configuration 2020-08-12 14:46:59 +02:00
7acf81552a
boards/hifive1* cpu/fe310: improve clock customization 2020-08-06 15:59:34 +02:00
Marian Buschsieweke
cf482c5d46
build system: Add libstdcpp feature and doc
- Add libstdcpp feature to indicate a platform is providing a libstdc++
  implementation ready for use
- The existing cpp feature now only indicates a working C++ toolchain without
  libstdc++. (E.g. still useful for the Arduino compatibility layer.)
- Added libstdcpp as required feature were needed
- Added some documentation on C++ on RIOT
2020-07-15 11:45:22 +02:00
Benjamin Valentin
0ddca68de9 cpu/fe310: use common names for heap markers
Other archs use `_sheap` and `_eheap` to mark the start and end of
the heap.

fe310 uses `_heap_start` and `_heap_end`, so platform independent
code that wants to make use of this will needlessly fail.

For compatibility with common code, name them the same on fe310.
2020-07-07 17:25:00 +02:00
3d9421571c
cpu/fe310: migrate to inlined irq API
Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
2020-06-26 10:48:56 +02:00
b36b2ee748
cpu/fe310: add Kconfig configuration 2020-06-24 11:13:45 +02:00
ee3fc27e96
cpu/fe310: implement driver for watchdog 2020-04-07 14:37:55 +02:00
Sören Tempel
bd2f5fe110 fe310: fix power management configuration 2020-01-30 10:43:01 +01:00
3869397ed3
cpu/fe310: move dependencies to Makefile.dep 2020-01-28 13:20:52 +01:00
Sören Tempel
5ef5ab7e4b Add CPU feature for stack smash protections 2020-01-22 15:59:02 +01:00
Francisco
f76f7c73ce
Merge pull request #12957 from aabadie/pr/cpu/fe310_spi
cpu/fe310: add spi peripheral driver
2020-01-14 10:54:47 +01:00
Tristan Bruns
532cdc64ff
cpu/fe310: implement SPI 2020-01-11 13:06:39 +01:00
298d573280
cpu/fe310: provide i2c driver 2020-01-11 13:06:10 +01:00
a953b74bc7
cpu/fe310: restore flash initialization in cpu_init 2020-01-10 16:51:10 +01:00
3f29eb9efb
cpu/fe310: use CLOCK_CORECLOCK macro to get cpu freq 2020-01-10 16:41:33 +01:00
fc911bf6c5
cpu/fe310: rework clock initialization 2020-01-10 16:41:33 +01:00
97e1c7ba7e
cpu/fe310: reorganize files and includes 2020-01-10 16:41:33 +01:00
4eba1427d2 cpu/fe310: uart_init(): drain RX fifo before enabling RX IRQ 2020-01-07 13:16:02 +01:00
e2f88abe63 cpu/fe310: periph_uart: only call rx_cb if set 2020-01-07 13:14:08 +01:00