According to the schematics user button should be on `PD5` not `PC5`
(so `GPIO_PIN(3, 5)`).
Due to the super high values resistors being used for the external
pullup it seems if you use a internal pullup it doesn't work.
The Sub-GHz Antenna of the Openmote-B is always connected to the AT86RF215.
It is the 2.4 GHz radial that can be switched between the CC2538 and the AT86RF215.
This changes the name of the defines accordingly.
- Added the file to `riot.doxyfile`
- Shortened the header to display properly
- Added `[TOC]` to let doxygen create a table of contents
- Added manual anchors to the headers for consistency with other doc files
- Use @code and @endcode for code blocks (using fenced blocks doesn't parse
with the Doxygen version used by the CI)
- Changed a numbered list containing code blocks to regular text, as the code
blocks as list items are not parsed correctly
- Enforce 80 chars per line limit
- Fixed some typos
- Removed trailing whitespace
- Added markdown syntax for code highlight in two cases
- Reduced the TODO section heading from level 1 to level 2
==> No content changes
lpc23xx has 2k of battery RAM that is retained in Deep Power Down mode.
To not overwrite that data it must only be initialized on Power On Reset.
However, RSIR looks the same when waking up from Deep Power Down as it does
on the power-on case.
So use 4 bytes of the backup RAM to keep a signature that is only valid if
memory was retained (no power-on Reset).
A small change to the linker script is required so two sections can be
placed into flash.
The application is mainly to compile-test non-blocking UART
functionality, but some functional testing is also possible.
With non-blocking UART the total runtime of the program is 2100735 µs
on same54-xpro.
With blocking UART the total runtime is 2152407 µs.
The UART peripheral clock seems to be sporadically set to wrong value when the CPU clock is changed. In this case, the UART clock is not set to 115.200 kbps but to 96 kbps, so that the output in the console seems like garbage. This can also cause automatic tests to fail. Therefore, the CPU clock is only changed if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ defines a different default CPU clock than the one already used at boot time.
The common ADC API dictates that a sample call must return -1 on an
incorrect resolution. The sam0 ADC implementation instead threw an
assertion failure.
