19970: sys/shell/gnrc_netif: fix ifconfig set language issue r=yarrick a=krzysztof-cabaj
### Contribution description
This PR fix some language issues in the output of `ifconfig set`.
### Testing procedure
Compile any program with `gnrc_netif` module, for example `examples/gcoap`.
Compare last line of presented outputs.
Output of `ifconfig help` without this PR.
```
All up, running the shell now
> ifconfig help
ifconfig help
usage: ifconfig help
usage: ifconfig <if_id> [up|down]
usage: ifconfig <if_id> set <key> <value>
Sets an hardware specific specific value
```
Output of `ifconfig help` with this PR.
```
All up, running the shell now
> ifconfig help
ifconfig help
usage: ifconfig
usage: ifconfig help
usage: ifconfig <if_id> [up|down]
usage: ifconfig <if_id> set <key> <value>
Sets a hardware specific value
```
### Issues/PRs references
None
Co-authored-by: krzysztof-cabaj <kcabaj@gmail.com>
To support lwIP better (dont require gnrc_ipv6)
Also don't require IPv6 for printing link type
With this sc_gnrc_netif can compile and work when using lwIP
(with l2util module added):
```
> ifconfig
Iface ET1 HWaddr: 24:0A:C4:E6:0E:9C Channel: 6 Link: up
L2-PDU:1500 Source address length: 6
Link type: wireless
inet6 addr: fe80::260a:c4ff:fee6:e9c scope: link
inet6 addr: 2001:db8::260a:c4ff:fee6:e9c scope: global
Iface ET0 HWaddr: 24:0A:C4:E6:0E:9F Link: up
L2-PDU:1500 Source address length: 6
Link type: wired
inet6 addr: fe80::260a:c4ff:fee6:e9f scope: link
inet6 addr: 2001:db8::260a:c4ff:fee6:e9f scope: global
>
```
Still works in gnrc_networking example:
```
> ifconfig
Iface 8 HWaddr: 24:0A:C4:E6:0E:9F Link: up
L2-PDU:1500 MTU:1500 HL:64 RTR
RTR_ADV
Source address length: 6
Link type: wired
inet6 addr: fe80::260a:c4ff:fee6:e9f scope: link VAL
inet6 group: ff02::2
inet6 group: ff02::1
inet6 group: ff02::1:ffe6:e9f
inet6 group: ff02::1a
```
19954: sys/psa_crypto: Ed25519 (EdDSA) support r=miri64 a=mguetschow
### Contribution description
- implement [`psa_sign_message()`](https://armmbed.github.io/mbed-crypto/html/api/ops/sign.html#c.psa_sign_message) and [`psa_verify_message()`](https://armmbed.github.io/mbed-crypto/html/api/ops/sign.html#c.psa_verify_message) for the two already supported [`PSA_ALG_ECDSA`](https://armmbed.github.io/mbed-crypto/html/api/ops/sign.html#c.PSA_ALG_ECDSA) algorithms, together with the CryptoCell and `micro-ecc` backends (*not* for the SE backend)
- add support for [`PSA_ALG_PURE_EDDSA`](https://armmbed.github.io/mbed-crypto/html/api/ops/sign.html#c.PSA_ALG_PURE_EDDSA), together with the CryptoCell hardware and `c25519` software backend (*not* for the SE backend)
- wipe private key data from stack for both ECDSA and EdDSA algorithms using `explicit_bzero()` (opinions from experienced Riot maintainers about usage of `goto` to avoid duplicating that function call before every `return`?)
### Testing procedure
- `examples/psa_crypto` has been updated to include EdDSA
- successfully tested configurations:
- `nrf52840dk` with cryptocell (hardware) and `c25519` (software) backend
- `native` with software backend
### Issues/PRs references
Thanks `@Einhornhool` for the PSA Crypto framework implementation #18547 which is great to work with!
Co-authored-by: Mikolai Gütschow <mikolai.guetschow@tu-dresden.de>
19941: drivers/lcd: add MCU-driven low-level parallel interface r=benpicco a=gschorcht
### Contribution description
The PR extends the LCD driver by a low-level interface for MCU-driven implementations of the MCU 8080 16-/8-bit parallel interface, allowing the MCU to use special peripherals for the interface, such as the FMC for STM32 MCUs, which is significantly faster than the integrated GPIO-driven parallel interface implementation of the LCD driver.
### Testing procedure
~Once PR #19938 and PR #19939 are merged, a PRs for these board can be pushed that allow to test this PR.~
Use either PR #19943 or PR #19944 on top of this PR to test, e.g. with PR #19943:
```
BOARD=stm32f723e-disco make -j8 -C tests/drivers/st77xx flash
```
### Issues/PRs references
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
19962: cpu/esp32: fix RISC-V ISA for ESP32-C3 with GCC 12.2 r=maribu a=gschorcht
### Contribution description
This PR fixes the RISC-V ISA spec in compiler and linker flags for ESP32-C3 and GCC 12.2.
Earlier versions of the specs and tools subsumed `zicsr` and `zifencei` into the `I` extension which is no longer the case. Therefore, the RISC-V ISA spec in compiler and linker flags had to be changed from `-march=rv32imc` to `-march=rv32imc_zicsr_zifencei`.
As a consequence floating-point arithmetics and I/O were no longer working with `-march=rv32imc` with GCC 12.2 since `riscv32-esp-elf/lib/libm_nano.a` was linked instead of `riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libm_nano.a` because `riscv32-esp-elf/lib/rv32imc/ilp32/libm_nano.a` is not existing in the toolchain.
### Testing procedure
Add a
```c
#include <math.h>
...
printf("sin(x): %f\n", sin(1.0f));
```
in the `main` function of any application. Without this PR the application should crash while it should work with this PR.
### Issues/PRs references
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
19959: pkg/driver_cryptocell_310: Fix Makefile r=benpicco a=mguetschow
### Contribution description
- make sure to download/extract during prepare, instead of build
- this fixes the issue of missing include dependencies for other pkgs at build time
### Testing procedure
- for an app Makefile, include both `c25519` and `driver_cryptocell_310`
- on `master`, `make all` fails with a missing include path from the `driver_cryptocell_310` package
- with this change, it works
### Issues/PRs references
- isolated from #19954 as suggested by `@miri64`
Co-authored-by: Mikolai Gütschow <mikolai.guetschow@tu-dresden.de>
19760: cpu/sam0_common/periph: add low-level SDMMC peripheral driver for SDHC r=benpicco a=gschorcht
### Contribution description
This PR implements the low-level SDIO/SDMMC peripheral driver for SAM0 SDHC according to the definition in #19539.
### Testing procedure
```
BOARD=same54-xpro make -C tests/drivers/sdmmc
```
```
BOARD=same54-xpro make -C tests/sys/vfs_default
```
### Issues/PRs references
~Depends on PR #19539~
Depends on PR #19899
19946: posix_sockets.c: Fix 2 byte int compilation errors r=benpicco a=mrdeep1
19956: cpu/esp32: fix heap definition for ESP32-S2 and ESP32-S3 r=benpicco a=gschorcht
### Contribution description
For ESP32-S2 and ESP32-S3 the symbol `_heap_end` must not be used as `_eheap` for the newlibc `malloc` and function `sbrk`.
`_heap_end` is used by the ESP-IDF heap implementation `esp-idf-heap` and points to the highest possible address (0x40000000) that could be used for the heap in ESP-IDF. It doesn't point to the top address of the unused SRAM area that can be used in newlibc `malloc` and function `sbrk`. Instead, the origin and the length of `dram0_0_seg` must be used to calculate the end of the heap `_eheap`.
The problem only occurs for the newlibc `malloc` when the `sbrk` function is used but not for the ESP-IDF heap implementation `esp_idf_heap`.
### Testing procedure
Use any ESP32-S2 or ESP32-S3 board and flash `tests/sys/malloc`, e.g.
```
CFLAGS='-DCHUNK_SIZE=16384' USEMODULE='stdio_uart' BOARD=esp32s3-pros3 make -j8 -C tests/sys/malloc flash
```
Without the PR the `nm` command will give the wrong address
```
nm -s tests/sys/malloc/bin/esp32s3-pros3/tests_malloc.elf | grep _eheap
40000000 A _eheap
```
The test will stuck, i.e. the allocation of memory stops when the top of unused SRAM is reached and the board restarts when the watchdog timer expires. With the PR it should work as expected
```
Help: Press s to start test, r to print it is ready
START
main(): This is RIOT! (Version: 2023.10-devel-309-g4669e)
calloc(zu, zu) = 0x10000000
CHUNK_SIZE: 16384
NUMBER_OF_TESTS: 3
Allocated 16384 Bytes at 0x3fc8c4b0, total 16384
...
Allocated 16384 Bytes at 0x3fcec6f0, total 409792
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x7 (TG0WDT_SYS_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
Saved PC:0x403763e3
```
With this PR the `nm` command should give a address in unused SRAM address space
```
nm -s tests/sys/malloc/bin/esp32s3-pros3/tests_malloc.elf | grep _eheap
3fcca000 A _eheap
```
and the test should pass.
### Issues/PRs references
19957: cpu/esp32: fix Octal SPI RAM for ESP32-S3 r=benpicco a=gschorcht
### Contribution description
This PR fixes Octal SPI RAM handling for ESP32-S3.
Functions that are used during the initialization of the Octal SPI RAM must reside in IRAM instead of Flash. Otherwise, the system stucks during boot once the Octal SPI RAM is enabled. The reason is that the Flash is not available during the initialization of the Octal SPI RAM and the functions that are called during that initialization can't be accessed in Flash. As a result the call of such a function leads to code that is messed up and the system crashes.
The PR also includes the documentation fixe for the `esp32s3-box`. It also includes a small documentation fix regarding the SPI RAM for the `esp32s3-pros3` board.
### Testing procedure
Use a board that has Octal SPI RAM and flash `tests/sys/malloc`, e.g.:
```
CFLAGS='-DCHUNK_SIZE=16384' USEMODULE='stdio_uart esp_spi_ram esp_log_startup' \
BOARD=esp32s3-box make -C tests/sys/malloc
```
Without the PR, the system stuck during boot once the information for the Octal SPI RAM is print
```
ESP-ROM:esp32s3-20210327
...
I (133) boot: Loaded app from partition at offset 0x10000
I (134) boot: Disabling RNG early entropy source...
vendor id : 0x0d (AP)
dev id : 0x02 (generation 3)
density : 0x03 (64 Mbit)
good-die : 0x01 (Pass)
Latency : 0x01 (Fixed)
VCC : 0x01 (3V)
SRF : 0x01 (Fast Refresh)
BurstType : 0x01 (Hybrid Wrap)
BurstLen : 0x01 (32 Byte)
Readlatency : 0x02 (10 cycles@Fixed)
DriveStrength: 0x00 (1/1)
```
and the board restarts when the watchdog timer expires.
With this PR, the system starts as expected.
```
ESP-ROM:esp32s3-20210327
...
I (132) boot: Loaded app from partition at offset 0x10000
I (133) boot: Disabling RNG early entropy source...
vendor id : 0x0d (AP)
dev id : 0x02 (generation 3)
density : 0x03 (64 Mbit)
good-die : 0x01 (Pass)
Latency : 0x01 (Fixed)
VCC : 0x01 (3V)
SRF : 0x01 (Fast Refresh)
BurstType : 0x01 (Hybrid Wrap)
BurstLen : 0x01 (32 Byte)
Readlatency : 0x02 (10 cycles@Fixed)
DriveStrength: 0x00 (1/1)
Found 64MBit SPI RAM device
SPI RAM mode: sram 40m
PSRAM initialized, cache is in normal (1-core) mode.
Pro cpu up.
Single core mode
SPI SRAM memory test OK
Initializing. RAM available for dynamic allocation:
At 3FC8C150 len 00053EB0 (335 KiB): D/IRAM
At 3FCE0000 len 0000EE34 (59 KiB): STACK/DRAM
At 3FCF0000 len 00008000 (32 KiB): DRAM
Starting ESP32x with ID: f412fafd0f8c
ESP-IDF SDK Version v4.4.1
Current clocks in Hz: CPU=80000000 APB=80000000 XTAL=40000000 SLOW=150000
PRO cpu is up (single core mode, only PRO cpu is used)
PRO cpu starts user code
Adding pool of 8192K of external SPI memory to heap allocator
Used clocks in Hz: CPU=80000000 APB=80000000 XTAL=40000000 FAST=8000000 SLOW=150000
XTAL calibration value: 3643448
Heap free: 8754851 bytes
Board configuration:
UART_DEV(0) txd=43 rxd=44
LED pins=[ ]
BUTTONS pins=[ 0 ]
Starting RIOT kernel on PRO cpu
Help: Press s to start test, r to print it is ready
```
### Issues/PRs references
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Jon Shallow <supjps-libcoap@jpshallow.com>
For ESP32-S2 and ESP32-S3 the symbol `_heap_end` must not be used as `_eheap` for dynamic memory allocation, because it points to the highest possible address that could be used for the heap, but not to the top address of the unused SRAM area. Instead, the origin and length of `dram0_0_seg` must be used to calculate the end of the heap.
