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cpu/esp32: fix RISC-V ISA for ESP32-C3 with GCC 12.2

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This commit is contained in:
Gunar Schorcht 2023-10-02 01:44:12 +02:00
parent 1ac169351b
commit 9a49dcd479
1 changed files with 2 additions and 1 deletions
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3
cpu/esp32/Makefile.include
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@ -241,7 +241,8 @@ CFLAGS += -D_CONST=const
# TODO no relaxation yet
ifneq (,$(filter riscv%,$(TARGET_ARCH)))
CFLAGS += -mno-relax -march=rv32imc -mabi=ilp32 -DRISCV_NO_RELAX
CFLAGS += -mno-relax -march=rv32imc_zicsr_zifencei -mabi=ilp32 -DRISCV_NO_RELAX
LINKFLAGS += -mno-relax -march=rv32imc_zicsr_zifencei -mabi=ilp32
GCC_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | \
$(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 \
-misa-spec=2.2 -E - > /dev/null 2>&1 && \