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Commit Graph

176 Commits

Author SHA1 Message Date
Francisco Molina
d075e55bb4 cpu/cortexm_common: replace irq_restore by __set_PRIMASK for stm32l152re
- The __NOP() that was added in #8518 is now remooved.
- When DBG_STANDBY, DBG_STOP or DBG_SLEEP are set in DBG_CR a hardfault
  occurs on wakeup from sleep. This was first diagnosed in #8518. When
  enabled, a hardfault occured when returning from a branch to irq_restore()
  we avoid the call by inlining the function call. See #11830 for more
  details.
2019-08-05 10:40:28 +02:00
francisco
4acceefa65 cortexm_common/Makefile.include: set RIOTBOOT_HRD_LEN for cortex-m
- Since the Vector table must be naturally aligned to the next power
  of two of the amount of supported ISR, and the table will be
  placed after riotboot_hdr, we must ensure RIOTBOOT_HRD_LEN has the
  same alignment.
2019-06-18 15:11:05 +02:00
Gaëtan Harter
bbb6dec054
Merge pull request #11630 from fjmolinas/pr_kinetis_ld
kinetis/ldscript: handle _rom_offset
2019-06-05 16:12:25 +02:00
francisco
43182bd8f7 cortexm_common/ldscript: use cortexm_rom_offset.ld 2019-06-04 18:05:35 +02:00
francisco
1e5a485539 cortexm_common/ldscript: add common script for rom_offset calculation 2019-06-04 18:05:35 +02:00
Benjamin Valentin
1c3f96495d ldscripts: move .noinit section behind .bss section
If the .noinit section starts at the beginning of the RAM,
a bootloader that is unaware of it will clear it.
Instead, move it behind the .bss section, hoping that a bootloader
will always use less .bss memory than RIOT proper.
2019-05-16 23:11:45 +02:00
bf000a1fa5
Merge pull request #11514 from kaspar030/fix_c11_atomic_definitions
core: fix c11 atomic definitions (fix gcc9 compilation)
2019-05-15 12:29:23 +02:00
Benjamin Valentin
29bf6c712b cortexm_common: add .noinit section
Make it possible to specify a section of RAM that is not touched by
the init routing so data can be kept across resets.

This should behave the same as on atmega & lpc2387.
2019-05-14 12:10:27 +02:00
68a4099c1c cpu/cortexm: fix pointer calculation
gcc9 started realizing that _sram is basically an uint8_t[1] and thus
HARDFAULT_HANDLER_REQUIRED_STACK_SPACE cannot be added to it without
exceeding the one-sized array.

This commit casts _sram to (uintptr_t) where that happens.
2019-05-13 17:38:10 +02:00
Oleg Artamonov
a5ce6deb02 cpu/cortexm_common: function to check address validity 2019-05-13 09:35:34 +02:00
emmanuelsearch
61c793aa4c cpu/cortexm_common: Add image_baseaddr support for Cortex-M23 2019-03-26 11:46:00 +01:00
3163b8d6e2
nrf52: use cortexm.ld script when applicable
The common linker script is not used when the nordic_softdevice_ble is
included
2019-03-13 11:57:44 +01:00
Dylan Laduranty
6d3fda7260 cpu/cortexm: add cortex-m23 support 2019-01-21 17:04:20 +01:00
7226daf33e
Merge pull request #10558 from dylad/pr/update_arm_cmsis
cpu/cortexm_common: Update ARM CMSIS to V5.4.0
2019-01-16 16:49:14 +01:00
Emmanuel Baccelli
209d90bc00
Merge pull request #10215 from kYc0o/pr/riotboot_multislot
riotboot: add multislot support
2019-01-15 19:04:28 +01:00
Dylan Laduranty
fdcac731eb cpu/cortexm_common: Update ARM CMSIS to V5.4.0
Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
2019-01-15 17:35:40 +01:00
Vincent Dupont
06f0c14460 cortexm_common: enable FPU on cortex-m4f 2019-01-03 15:24:20 +01:00
Francisco Acosta
e8660b2012 cpu/cortex_common: add support for multislot
A second slot is defined with a calculated size, from the
remaining flash after the bootloader and the first slot.
Both slots are defined as equal size, but it can be overriden.
2019-01-02 17:56:11 +01:00
7a6849ca17 cpu/cortexm_common: add riotboot and slot support
RIOTBOOT_SLOT_LEN is calculated as an hexadecimal value and
handles ROM_LEN defined as kilobytes like '512K'

This enables support for all the cortex-m0+/3/4/7 arch,
so most boards embedding these are potentially supported.
One needs just to ensure that the CPU can be initialised
at least twice.

Co-authored-by: Gaëtan Harter <gaetan.harter@fu-berlin.de>
2018-12-18 19:31:35 +01:00
9cfdf6e379 cpu/cortexm_common: introduce cpu_jump_to_image()
This new function allows to jump to another execution
environment (VTOR) located at a certain (aligned) address.
It's used to boot firmwares at another location than
`CPU_FLASH_BASE`.

The user needs to ensure that the CPU using this feature
is able to be initialised at least twice while jumping
to the RIOT `reset_handler_default` function, since it
initialises the CPU again (calls cpu_init()).

Co-authored-by: Kaspar Schleiser <kaspar@schleiser.de>
2018-12-18 19:31:35 +01:00
PeterKietzmann
0be350e352 sys/puf_sram: CPU specific attributes for variables 2018-11-20 08:34:53 +01:00
smlng
59e299635b cppcheck: add/correct reason for cppcheck-suppress
Adding and correcting description/rational on why certain cppcheck
warnings or errors are intentionally suppressed.
2018-09-25 12:03:58 +02:00
Pekka Nikander
6aa0a48558 cpu/cortexm_common/cortexm_init: Allow piecewise calling
Refactor cortexm_init to allow bits and pieces of
   it to be called separately, while retaining the
   current API, too.  Needed for non-standard
   Cortex-M initialisation, such as with nRF52
   SoftDevice.
2018-08-28 14:07:50 +03:00
Martine Lenders
b305ee4b41 cortexm_common: Mark llvm and gnu as supported toolchains 2018-08-16 16:41:58 +02:00
Gaëtan Harter
7dad2e7096
cortexm_common/ldscript: allow defining FW_ROM_SIZE
Allow defining a specific rom length to use for linking the firmware,
_fw_rom_length, instead of the default configuration to use the whole rom from
_rom_offset to the end.

 * Add cortexm_common/Makefile.include FW_ROM_SIZE configuration
 * Add an assertion that _fw_rom_length still respects _rom_length
2018-08-11 11:34:01 +02:00
Gaëtan Harter
c84539fdb3
cortexm_common: allow defining ROM_OFFFSET in a compilation rule
Define _rom_offset with a conditional evaluated at execution time to allow
setting it in compilation rules and generate in the same make instance different
elf files with different configurations.
2018-08-11 11:33:55 +02:00
Gaëtan Harter
9103dcaeda
cortexm_common: refactor the definition test
The variables should all always be defined.
2018-08-11 11:33:52 +02:00
Gaëtan Harter
83a617261a
cortexm_common/ldscript: add _fw_rom_length variable
It will help testing if it is taken into account and for defining for outside
after.
2018-08-11 11:33:47 +02:00
Gaëtan Harter
d9db258411
cortexm_common/ldscript: re-use _rom_offset variable name
Inspired by kaspar030 version to removing the new _boot_offset variable.

cbf324a66d/cpu/cortexm_common/ldscripts/cortexm.ld
2018-08-11 11:33:39 +02:00
PeterKietzmann
20397c5b15 cortexm_common: add SRAM based PRNG seeder 2018-07-04 17:55:16 +02:00
938677cc83 cpu*: fix doxygen grouping 2018-06-11 19:12:02 +02:00
smlng
34ade00db9 cpu/cortex_common: fix indention in vector table 2018-05-24 11:26:46 +02:00
Joakim Nohlgård
77449aa592
Merge pull request #9103 from gebart/pr/cortexm-vectors-const
cortexm: const ISR vectors
2018-05-11 21:35:12 +02:00
Joakim Nohlgård
4532c348b4 cortexm_common: Adjust ldscript memory segment attributes 2018-05-09 06:44:12 +02:00
Joakim Nohlgård
b8d6bcdb07 cortexm_common: specify load segment instead of load address for .data 2018-05-09 00:41:27 +02:00
Joakim Nohlgård
f073fdb34f cortexm_common: Mark base ISR vector as const 2018-05-09 00:32:28 +02:00
c9c7cd4951 cpu: cortexm_common: use thread_yield_higher() in cortexm_isr_end() 2018-04-13 10:12:39 +02:00
Girts Folkmanis
b9744f698f cortexm_common: don't try to set MEMFAULTENA on ARMv6-M
Before this change, if one tried to build a Cortex-M0+ target that had
an MPU, compilation would fail due to missing
'SCB_SHCSR_MEMFAULTENA_Msk' in SCB structure. Cortex-M0+ is a ARMv6-M
arch (unlike most other targets that have MPU support). ARMv6-M has more
limited support for fault conditions, see ARMv6-M Architecture Reference
Manual, D3.6.2.
2018-03-12 19:57:29 -07:00
Francisco Acosta
ac9328381c cpu/cortexm_common: add NOP after WFI to avoid hardfault on stm32l152 2018-02-12 15:10:34 +01:00
99d484f336 cpu/cortexm_common: select bitarithm_lsb() by available instructions 2018-01-16 23:35:14 +01:00
32c10ae2c9 core, cpu: rename thread_start_threading() -> cpu_switch_context_exit() 2017-11-16 14:40:16 +01:00
86665b71bf cpu: adapt to COREIF_NG removal 2017-11-16 14:40:16 +01:00
f6d7e54228
Merge pull request #7739 from kYc0o/factorise_sam0_ldscripts
ld: refactor sam0 ldscripts
2017-11-13 11:36:25 +01:00
Joakim Nohlgård
e3d5a70e0c cpu/cortexm: Remove leftover _estack declarations
These are leftovers from before the Cortex-M common ISR vectors were
split into vectors_cortexm.c
2017-11-10 15:38:14 +01:00
kYc0o
d25fd647e7 cpu/cortexm_common/ldscripts: add common linker script for cortexm family 2017-11-07 15:05:43 +01:00
kYc0o
4d681ac862 cpu/cortexm_common/Makefile.include: define linker length vars if set 2017-11-07 15:05:43 +01:00
268e763d63 make: move mcuboot related stuff to makefiles/mcuboot.mk 2017-11-07 12:28:41 +01:00
3ec8126c84 cpu: cortexm: provide periph_pm for all cortexm 2017-11-06 12:01:19 +01:00
a20745b6c5 cpu: make use of Makefile.periph 2017-11-06 12:01:19 +01:00
7c9f6a4763
Merge pull request #7907 from gebart/pr/cortexm-fix-hardfault-print
cortexm_common: Correct offset for hardfault stack
2017-11-02 15:59:36 +01:00