Unify cpu_init for all Kinetis CPUs to reduce code duplication.
Updated the MCG driver implementation to make the configuration easier.
Most clock settings are initialized by kinetis_mcg_init() called from
cpu_init. Board specific external clock source initialization
(FRDM-K64F, PhyNode) needs to be performed in board_init instead of
in cpu_init.
The use of symbolic links leads to trouble in certain environments
(e.g. vagrant under Win). This PR gets rid of symlinks and uses
variables in the Makefiles to map to the correct linkerscripts
instead.
The CPU has multiple issues and several parts of the platform code
does not even compile cleanly for this CPU in the current state.
This removes support for parts MK60DN256ZVLL10, MK60DN512ZVLL10
(note the Z) CPUs with this part number were used in Mulle v0.60 which
only has been used in some in-house projects at Eistec and LTU.
This is a rewrite of the Kinetis GPIO driver which follows the
refactored API in [1]. Pins are specified using the GPIO_PIN(PORT_x, y)
macro, e.g. GPIO_PIN(PORT_E, 25) for the PTE25 pin.
The interrupt pin handling is now implemented as a linked list, this
is more memory efficient, but with a minor variation in interrupt
latency depending on in what order the pins were initialized at
runtime.
Because the linked list entries are taken from a shared pool, there is
also the possibility of running out of available configuration slots,
define the preprocessor macro GPIO_INT_POOL_SIZE in periph_conf.h if
you need more than 16 pins configured for interrupts in the same
application.
[1]: https://github.com/RIOT-OS/RIOT/pull/3095
e4218: SIM/FLEXBUS: SIM_SCGC7[FLEXBUS] bit should be cleared when the
FlexBus is not being used.
Errata type: Errata
Description:
The SIM_SCGC7[FLEXBUS] bit is set by default. This means that the
FlexBus will be enabled and come up in global chip select mode. With
some code sequence and register value combinations the core could
attempt to prefetch from the FlexBus even though it might not actually
use the value it prefetched. In the case where the FlexBus is
unconfigured, this can result in a hung bus cycle on the FlexBus.
Workaround:
- If the FlexBus is not being used, disabled the clock to the FlexBus
during chip initialization by clearing the SIM_SCGC7[FLEXBUS] bit.
- If the FlexBus will be used, then enable at least one chip select as
early in the chip initialization process as possible.
- Merged the two kinetis_common ldscripts into a single script.
- Updated cpus to use the new script
- Updated K60 to merge sram_l and sram_u into one segment
