The `ldr r1, =sched_active_thread` instruction couldn't be assembled with
LTO, as the no immediate offset could be found to construct the address of
`sched_active_thread`. This commit instructs the assembler to generate a
literate pool which can be used to construct the address. While this issue
was only triggered during LTO, it theoretically could also pop up without LTO
due to unrelated changes. Thus, it is a good idea to create the literate pool
even without LTO enabled.
- removed coretx-m[0|3|4]
- moved their content to cortexm_common
- adjusted cortex Makefiles to this new name
- adjusted cortex Makefiles new structure
- fixes to cortexm-common
- Added ARM CMSIS headers to cortexm_common
- thread_exit fixes to cortexm-common
- cortexm-common adjusted documentation
- cortexm_common added eINT dINT defines for now
