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ef5897775d
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cpu/stm32l4wb: add missing define for PLL HSI source
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2020-11-10 09:34:07 +01:00 |
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18b5f417d1
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cpu/stm32l4: implement MCO configuration
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2020-11-05 13:34:45 +01:00 |
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d1724d6718
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cpu/stm32l4: correctly handle clock freq > 80MHz
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2020-10-20 11:37:46 +02:00 |
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00ea7ffa55
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cpu/stm32l4wb: cleanup clock initialization
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2020-10-20 11:37:46 +02:00 |
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d7d5d9d651
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boards/stm32l4: extend clock configuration
- add PLLQ default value
- better tune default PLLM value depending on HSE value
- ensure CLOCK_PLL_SRC is always defined
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2020-10-20 11:37:45 +02:00 |
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b11d65ab70
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cpu/stm32l4: enable PLLQ as 48MHz source if possible
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2020-10-20 11:37:45 +02:00 |
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4e235b8e76
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cpu/stm32l4wb: fix APBx bitfields for divider factor 2
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2020-09-09 15:59:38 +02:00 |
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9dd20c0ccb
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cpu: boards: stm32l4/wb: use IS_USED for clock where possible
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2020-09-08 18:42:42 +02:00 |
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0745cc4a99
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cpu: boards: smt32l4: rework clock configuration
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2020-09-08 18:42:41 +02:00 |
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63a79ae6e4
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cpu/stm32: move stmclk in its own module, remove useless ifdefs
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2020-05-22 21:21:08 +02:00 |
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