2 Commits

Author	SHA1	Message	Date
Marian Buschsieweke	8b1c43afb0	cpu/gd32v: Allow configuration of SWJ_CFG ... Expose the compile time configuration knob `CONFIG_AFIO_PCF0_SWJ_CFG` to allow freeing some/all JTAG pins and use them as GPIOs. As default, PB4 is remapped from NJTRST to be usable as regular GPIO. This still allows using the JTAG interface for debugging/flashing, but makes an GPIO exposed by some boards available.	2024-01-19 23:17:35 +01:00
Koen Zandberg	3d470b0c12	cpu/gd32v: Initial include of the GD32VF103 device ... This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>	2021-08-24 14:30:23 +02:00