8 Commits

Author	SHA1	Message	Date
hugues	d069c6e787	cpu/stm32/periph/pwm: CCMR1 was defined a second time instead of CCMR2	2020-07-10 13:47:45 +02:00
hugues	a5da5953b2	cpu/stm32/periph/pwm: multiple devices PWM_RIGHT mode bugfix	2020-07-10 13:47:09 +02:00
hugues	16e454ccaf	cpu/stm32/periph/pwm: some bugfixes...	2020-07-09 23:49:00 +02:00
hugues	11e847c9af	cpu/stm32: fix off-by-one error in clock frequency assert	2020-07-08 14:17:14 +02:00
Benjamin Valentin	06cdd30fcb	cpu/stm32: use TIMER_CHANNEL_NUMOF for consistency	2020-06-24 12:58:38 +02:00
Alexandre Abadie	2dc0ec00a1	cpu/stm32: adapt timer driver to common CMSIS timer structure	2020-05-29 18:22:00 +02:00
Alexandre Abadie	b6d2231d6d	cpu/stm32: adapt Doxygen documentation	2020-05-20 13:39:11 +02:00
Alexandre Abadie	5c810d8535	cpu/stm32: introduce unique directory for stm32 cpus	2020-05-20 13:39:10 +02:00