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139 lines
3.9 KiB
C
139 lines
3.9 KiB
C
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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* 2015 Engineering-Spirit
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* 2016 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_periph_pwm
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* @{
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*
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* @file
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* @brief Low-level PWM driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Aurelien Gonce <aurelien.gonce@altran.fr>
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*
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* @}
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*/
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#include "cpu.h"
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#include "assert.h"
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#include "periph/pwm.h"
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#include "periph/gpio.h"
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#define CCMR_LEFT (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | \
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TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2)
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#define CCMR_RIGHT (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | \
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TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2M_0 | \
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TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
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static inline TIM_TypeDef *dev(pwm_t pwm)
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{
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return pwm_config[pwm].dev;
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}
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uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
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{
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uint32_t timer_clk = periph_timer_clk(pwm_config[pwm].bus);
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/* verify parameters */
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assert((pwm < PWM_NUMOF) && ((freq * res) <= timer_clk));
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/* power on the used timer */
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periph_clk_en(pwm_config[pwm].bus, pwm_config[pwm].rcc_mask);
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/* reset configuration and CC channels */
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dev(pwm)->CR1 = 0;
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dev(pwm)->CR2 = 0;
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for (unsigned i = 0; i < TIMER_CHANNEL_NUMOF; ++i) {
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TIM_CHAN(pwm, i) = 0;
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}
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/* configure the used pins */
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unsigned i = 0;
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while ((i < TIMER_CHANNEL_NUMOF) && (pwm_config[pwm].chan[i].pin != GPIO_UNDEF)) {
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gpio_init(pwm_config[pwm].chan[i].pin, GPIO_OUT);
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gpio_init_af(pwm_config[pwm].chan[i].pin, pwm_config[pwm].af);
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i++;
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}
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/* configure the PWM frequency and resolution by setting the auto-reload
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* and prescaler registers */
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dev(pwm)->PSC = (timer_clk / (res * freq)) - 1;
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dev(pwm)->ARR = res - 1;
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/* set PWM mode */
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switch (mode) {
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case PWM_LEFT:
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dev(pwm)->CCMR1 = CCMR_LEFT;
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dev(pwm)->CCMR2 = CCMR_LEFT;
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break;
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case PWM_RIGHT:
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dev(pwm)->CCMR1 = CCMR_RIGHT;
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dev(pwm)->CCMR2 = CCMR_RIGHT;
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break;
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case PWM_CENTER:
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dev(pwm)->CCMR1 = 0;
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dev(pwm)->CCMR2 = 0;
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dev(pwm)->CR1 |= (TIM_CR1_CMS_0 | TIM_CR1_CMS_1);
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break;
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}
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/* enable PWM outputs and start PWM generation */
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#ifdef TIM_BDTR_MOE
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dev(pwm)->BDTR = TIM_BDTR_MOE;
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#endif
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dev(pwm)->CCER = (TIM_CCER_CC1E | TIM_CCER_CC2E |
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TIM_CCER_CC3E | TIM_CCER_CC4E);
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dev(pwm)->CR1 |= TIM_CR1_CEN;
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/* return the actual used PWM frequency */
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return (timer_clk / (res * (dev(pwm)->PSC + 1)));
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}
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uint8_t pwm_channels(pwm_t pwm)
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{
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assert(pwm < PWM_NUMOF);
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unsigned i = 0;
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while ((i < TIMER_CHANNEL_NUMOF) && (pwm_config[pwm].chan[i].pin != GPIO_UNDEF)) {
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i++;
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}
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return (uint8_t)i;
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}
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void pwm_set(pwm_t pwm, uint8_t channel, uint16_t value)
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{
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assert((pwm < PWM_NUMOF) &&
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(channel < TIMER_CHANNEL_NUMOF) &&
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(pwm_config[pwm].chan[channel].pin != GPIO_UNDEF));
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/* norm value to maximum possible value */
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if (value > dev(pwm)->ARR) {
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value = (uint16_t)dev(pwm)->ARR;
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}
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/* set new value */
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TIM_CHAN(pwm, pwm_config[pwm].chan[channel].cc_chan) = value;
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}
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void pwm_poweron(pwm_t pwm)
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{
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assert(pwm < PWM_NUMOF);
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periph_clk_en(pwm_config[pwm].bus, pwm_config[pwm].rcc_mask);
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dev(pwm)->CR1 |= TIM_CR1_CEN;
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}
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void pwm_poweroff(pwm_t pwm)
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{
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assert(pwm < PWM_NUMOF);
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dev(pwm)->CR1 &= ~TIM_CR1_CEN;
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periph_clk_dis(pwm_config[pwm].bus, pwm_config[pwm].rcc_mask);
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}
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