This patch implements the basic support the last of the FLEXCOMM modes,
Serial Peripheral Interface, in a simple blocking mode with busy wait,
which is enough to test all the SPI functionality end-to-end.
Tested reading and writing registers on a SPI peripheral, and checked
with the oscilloscope that the frequencies were as expected.
Results from `tests/periph_spi`:
```
> init 0 0 2 -1 0
SPI_DEV(0) initialized: mode: 0, clk: 2, cs_port: -1, cs_pin: 0
> bench
1 - write 1000 times 1 byte: 16002 16009
2 - write 1000 times 2 byte: 18001 18008
3 - write 1000 times 100 byte: 802000 802007
4 - write 1000 times 1 byte to register: 24003 24010
5 - write 1000 times 2 byte to register: 26001 26008
6 - write 1000 times 100 byte to register: 810001 810008
7 - read 1000 times 2 byte: 23003 23009
8 - read 1000 times 100 byte: 807002 807009
9 - read 1000 times 2 byte from register: 32002 32009
10 - read 1000 times 100 byte from register: 816002 816009
11 - transfer 1000 times 2 byte: 23003 23009
12 - transfer 1000 times 100 byte: 807003 807010
13 - transfer 1000 times 2 byte to register: 32003 32009
14 - transfer 1000 times 100 byte to register:816002 816009
15 - acquire/release 1000 times: 7222 7228
-- - SUM: 5059250 5059351
```
This initial I2C support allows to use the I2C bus in controller mode to
interact with multiple peripherals in blocking mode. The CPU will
perform a busy wait when transferring data over I2C.
This patch implements the real time clock module for the QN908X cpus.
This module is very straightforward with only the one notable drawback
that it doesn't have a match register like the CTIMER block to implement
the alarm function. Instead, this driver can only use the interrupt
generated ever 1 second to implement the alarm match comparison in
software.
The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB,
Bluetooth Low Energy and in some variants NFC. This patch implements the
first steps for having support for this CPU.
While the QN908x can be considered the successor of similar chips from
NXP like the KW41Z when looking at the feature set, the internal
architecture, boot image format and CPU peripherals don't match those
in the Kinetis line. Therefore, this patch creates a new directory for
just the QN908x chip under cpu/qn908x.
The minimal set of peripherals are implemented in this patch to allow
the device to boot and enable a GPIO: the gpio and wdt peripheral
modules only.
The wdt driver is required to boot and disable the wdt. On reset, the
wdt is disabled by the chip, however the QN908x bootloader stored in
the internal ROM enables the wdt and sets a timer to reboot after 10
seconds, therefore it is needed to disable the wdt in RIOT OS soon
after booting. This patch sets it up such that when no periph_wdt module
is used the Watchdog is disabled, but if the periph_wdt is used it must
be configured (initialized) within the first 10 seconds.
Tests performed:
Defined a custom board for this CPU and compiled a simple application
that blinks some LEDs. Manually tested with periph_wdt and with
periph_wdt_cb as well.
