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Commit Graph

17 Commits

Author SHA1 Message Date
Teufelchen1
0e839654e8 cpu/riscv: Add PMP driver 2023-06-28 11:55:34 +02:00
Karl Fessel
baf07e881e cpu/fe310: add CPU_CORE information 2021-09-22 15:51:54 +02:00
Benjamin Valentin
a9c83017ee cpu/riscv_common: only select PLIC for fe310
Not every RISC-V implements that interrupt controller, gd32v uses
CLIC instead.
2021-08-25 10:49:47 +02:00
Benjamin Valentin
d47a880915 cpu: add periph_rtt_overflow feature
The RTT overflow callback is not available on all RTT implementations.
This means it is either a no-op or `rtt_set_overflow_cb()` is a no-op
or it will overwrite the alarm set with `rtt_set_alarm()`.

This adds a feature to indicate that proper overflow reporting is available.
2021-04-30 11:58:00 +02:00
Marian Buschsieweke
b9cb75fedf
drivers/periph/rtt: add periph_rtt_set_counter feature
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
2021-03-04 18:05:06 +01:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
Francisco Molina
63a2a6ce1b
treewide: model newlib as a FEATURE 2021-01-27 09:24:25 +01:00
Benjamin Valentin
45270dada0 cpu/fe310: blacklist picolibc on CI
The RISC-V toolchain in riotdocker has issues with picolibc and
will still include newlib headers.

This leads to conflicts like

```
In file included from [01m[Knanostubs.c:22[m[K:
[01m[K/usr/local/picolibc/riscv-none-embed/include/stdio.h:270:23:[m[K [01;31m[Kerror: [m[Kconflicting types for '[01m[K__FILE[m[K'
 typedef struct __file [01;31m[K__FILE[m[K;
                       [01;31m[K^~~~~~[m[K
In file included from [01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/reent.h:93[m[K,
                 from [01m[Knanostubs.c:20[m[K:
[01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/sys/reent.h:287:26:[m[K [01;36m[Knote: [m[Kprevious declaration of '[01m[K__FILE[m[K' was here
 typedef struct __sFILE   [01;36m[K__FILE[m[K;
                          [01;36m[K^~~~~~[m[K
```

The problem does not occur when installing both the toolchain and picolibc
directly from the Debian / Ubuntu repositories, but CI uses an older Ubuntu
version that does not have those packages yet, so it builds them manually.

Blacklist RISC-V until CI has been updated.
2020-10-14 16:32:01 +02:00
Benjamin Valentin
cff8e862b8 picolibc: model as a feature 2020-09-15 22:11:21 +02:00
3180a11b51
fe310: Add PLIC peripheral driver 2020-08-31 16:26:42 +02:00
Marian Buschsieweke
cf482c5d46
build system: Add libstdcpp feature and doc
- Add libstdcpp feature to indicate a platform is providing a libstdc++
  implementation ready for use
- The existing cpp feature now only indicates a working C++ toolchain without
  libstdc++. (E.g. still useful for the Arduino compatibility layer.)
- Added libstdcpp as required feature were needed
- Added some documentation on C++ on RIOT
2020-07-15 11:45:22 +02:00
ee3fc27e96
cpu/fe310: implement driver for watchdog 2020-04-07 14:37:55 +02:00
Sören Tempel
5ef5ab7e4b Add CPU feature for stack smash protections 2020-01-22 15:59:02 +01:00
a3706c1f02 cpu/fe310: add cpp feature 2019-12-05 18:27:12 +01:00
5e301219df
cpu/fe310: provide gpio feature at cpu level 2019-12-05 15:25:26 +01:00
Sebastian Meiling
ea0b5ff0dd cpu: add missing arch features to fe310
Adds arch_32bit and arch_riscv to cpu/fe310 to allow for feature
requirements and blacklisting.
2019-10-14 17:40:23 +02:00
kenrabold
7d1d5e77d8 cpu/fe310: add RISC-V cpu FE310
New CPU FE310 from SiFive based on RISC-V architecture

build: add makefile for RISC-V builds

Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00