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Commit Graph

24 Commits

Author SHA1 Message Date
Sebastiaan de Schaetzen
e3c9b0c4ca cortexm: initialise fpu early 2021-04-29 13:19:47 +02:00
Bas Stottelaar
0f8cecb50b cpu/cortexm_common: add support for Cortex-M33 2020-10-06 17:11:26 +02:00
fc1d642113
cpu/cortexm_init: add specific case for stm32g0 svcall irq 2020-07-21 12:45:25 +02:00
1f0a3a6bae
cpu/cortexm_common: add special case for SVC interrupt configuration
by default stm32f0/l0/l1 families simply call the interrupt enum SVC_IRQn
2020-07-16 17:35:48 +02:00
Leandro Lanzieri
4d65bc8e0a
cpu: Rename CPU_ARCH to CPU_CORE 2020-06-16 12:05:40 +02:00
Pekka Nikander
4534e9b773
cpu/cortexm_common: add irq sub-priorities
This commit enables Cortex-M CPU interrupt sub-priorities
and allows the PendSV interrupt to have a priority different
from the default one.  Together these two preprocessor
defines can be used to have PendSV always run as the last interrupt
before returning from the interrupt stack back to the user space.

Running PendSV as the last interrupt before returning to the
user space is recommended by ARM, as it increases efficiency.
Furthermore, that change enhances stability a lot with the
new nRF52 SoftDevice support, currently being worked in
PR #9473.

This commit merely enables sub-priorities and a separate
PendSV priority to be used without changing the default
RIOT behaviour.
2020-04-03 17:49:31 +02:00
84bf543d78 cpu/cortexm_common: fix typos 2019-11-23 22:39:36 +01:00
Francois Berder
4a31f94cfc many typo fixes
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
2019-11-23 22:39:07 +01:00
Oleg Artamonov
a5ce6deb02 cpu/cortexm_common: function to check address validity 2019-05-13 09:35:34 +02:00
Dylan Laduranty
6d3fda7260 cpu/cortexm: add cortex-m23 support 2019-01-21 17:04:20 +01:00
Pekka Nikander
6aa0a48558 cpu/cortexm_common/cortexm_init: Allow piecewise calling
Refactor cortexm_init to allow bits and pieces of
   it to be called separately, while retaining the
   current API, too.  Needed for non-standard
   Cortex-M initialisation, such as with nRF52
   SoftDevice.
2018-08-28 14:07:50 +03:00
Hauke Petersen
fd981dff22 cpu/cortexm: set VTOR for selected M0+ CPUs 2017-06-02 11:53:59 +02:00
Hauke Petersen
10a7486246 cpu/cortex_common: added support for Cortex-M7 2017-05-08 09:16:11 +02:00
Vincent Dupont
f656a31e58 cpu/cortexm_common: use linker variable to initialize SCB->VTOR 2017-03-17 18:07:22 +01:00
d8f0eaf127 cpu: cortexm: fix signed<->unsigned compare 2017-01-25 10:10:47 +01:00
Joakim Nohlgård
8c82d9952b cortexm_common: Fix -Wsign-compare warning in cortexm_init 2017-01-16 08:55:08 +01:00
DipSwitch
b6140f15f3 cpu/cortex-m: Enable STKALIGN to make the Cortex-M keep the stack 8 byte aligned on 4 byte aligned stack pointers 2016-04-07 00:27:26 +02:00
Martine Lenders
01248f0599 Merge pull request #4944 from gebart/pr/cortexm-irqn-unsigned-int
cpu/cortexm_common: use int for counter in startup IRQn loop
2016-03-04 05:40:51 +01:00
Joakim Nohlgård
3da2c2d1c1 cpu/cortexm_common: use int for counter in startup IRQn loop 2016-03-02 10:58:59 +01:00
Hauke Petersen
eb79646ab1 cpu/cortexm_common: added sleep_until_event 2016-03-01 23:22:03 +01:00
Oleg Hahm
f24e810de5 cpu cortexm_common: fix pedantic compiler warnings 2015-12-07 20:28:52 +01:00
d359c86c60 cpu: cortexm_common: set pendSV to default priority 2015-07-28 20:02:45 +02:00
Joakim Gebart
32c213d0b0 cpu/cortexm_common: Fix signedness warning 2015-07-14 08:11:14 +02:00
Hauke Petersen
78d65a4dec cpu/cortexm_common: centralized init and defines
- added a centralized core implementation for all cortex CPUs
- moved default stack size defines to cpu.h in cortexm_common
- moved uart0 bufsize define to cpu.h in cortexm_common
- moved typed of panic_t to cpu.h in cortexm_common
2015-05-29 16:42:05 +02:00