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64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cortexm_common
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* @{
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*
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* @file
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* @brief Cortex-M specific configuration and initialization options
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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/**
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* @name Pattern to write into the co-processor Access Control Register to
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* allow full FPU access
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*/
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#define FULL_FPU_ACCESS (0x00f00000)
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void cortexm_init(void)
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{
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/* initialize the FPU on Cortex-M4F CPUs */
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#ifdef CPU_ARCH_CORTEX_M4F
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/* give full access to the FPU */
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SCB->CPACR |= (uint32_t)FULL_FPU_ACCESS;
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#endif
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/* configure the vector table location to internal flash */
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#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
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defined(CPU_ARCH_CORTEX_M4F)
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SCB->VTOR = CPU_FLASH_BASE;
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#endif
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/* initialize the interrupt priorities */
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/* set pendSV interrupt to same priority as the rest */
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NVIC_SetPriority(PendSV_IRQn, CPU_DEFAULT_IRQ_PRIO);
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/* set SVC interrupt to same priority as the rest */
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NVIC_SetPriority(SVCall_IRQn, CPU_DEFAULT_IRQ_PRIO);
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/* initialize all vendor specific interrupts with the same value */
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for (unsigned i = 0; i < CPU_IRQ_NUMOF; i++) {
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NVIC_SetPriority((IRQn_Type) i, CPU_DEFAULT_IRQ_PRIO);
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}
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/* enable wake up on events for __WFE CPU sleep */
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SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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/* for Cortex-M3 r1p0 and up the STKALIGN option was added, but not automatically
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* enabled until revision r2p0. For 64bit function arguments to work properly this
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* needs to be enabled.
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*/
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#ifdef SCB_CCR_STKALIGN_Msk
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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#endif
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}
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