- Since flash access is shared with CPU2 we resize ROM_LEN
according to CPU2 secure flash memmory area.
- Add assert to prevent unauthorized reads from CPU2 secure
flash area
- cpu/stm32f1: Removed previous code in gpio_init() to provide PB4 on the
Nucleo-F103RB only
- cpu/stm32_common: Introduced STM32F1_DISABLE_JTAG which, if defined in
board.h, exposes the JTAG only pins as GPIOs. This keeps the SWD pins, so that
SWD debugging remains possible
Fix the condition to return -ENOPNOTSUPP when i2c repeated read attempted.
Currently the error occures even if a read after write is attempted.
This is the standard way to i2c_read_reg which should be supported.
The -EOPNOTSUPP requires the previous R/W state to be reading.
This means a `I2C_SR2_TRA` must be checked to be 0.
There is no hardware limitation for custom boards based on STM32 to uses
SPI bus with signals coming from different PORT and alternate functions.
This patch allow alternate's function definition per pin basis, thus enable
the support of SPI bus signals routed on differents PORT.
Signed-off-by: Yannick Gicquel <ygicquel@gmail.com>
A naive implementation may set a RTC alarm in 30s by calling
struct tm now;
rtc_get_time(&now);
now.tm_sec += 30;
rtc_set_alarm(&now, _cb, NULL);
This works for RTC implementations that use a RTT internally and call
mktime() to convert the struct tm to a unix timestamp, as mktime() will
normalize the struct in the process.
Call rtc_tm_normalize() when the RTC uses separate registers for time / date
components to ensure it is normalized.
This also modifies tests/periph_rtc to exercise this case.
- Removed stdio_init() from newlib's _init(), as this is too late in the boot
process to allow DEBUG()ing during periph_init()
- Added stdio_init() to the various cpu_init() routines of the ARM CPUs just
before periph_init()
once hardware flow control is enabled, rts should only be initialized
after the uart is enabled by setting the UE flag. This is stated in the
stm32f4 errata.
in uart_poweroff the peripheral should be disabled through the register
instead of just disabling the peripheral clock. In uart_poweron the
peripheral should be enabled after enabling the clock.
Not explicitely disabling the peripheral causes some bad signals on the
uart line sometimes.
