1
0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Commit Graph

16 Commits

Author SHA1 Message Date
krzysztof-cabaj
2f0a78640f cpu/esp8266: fix issue found by static tests 2024-04-11 19:19:58 +02:00
krzysztof-cabaj
569b4b5294 cpu/esp8266: fix doxygen unbalanced grouping 2024-04-11 19:04:06 +02:00
Benjamin Valentin
75bf0e33e0 cpu/esp8266: allow arbitrary SPI clocks 2024-02-21 23:15:21 +01:00
Benjamin Valentin
8bcfe7b7b6 cpu/esp8266: ESP8266 needs 5 cycles per busy loop 2024-01-10 22:43:31 +01:00
c9207e81a3
cpu/esp8266: include cpu_conf.h in periph_cpu.h 2021-12-15 13:14:19 +01:00
iosabi
52107b2416 esp8266: Support UART1 and other UART0 pins.
The esp8266 CPU has actually two hardware UART peripherals. UART0 is
used by the boot ROM for flashing and serial output during boot,
typically at a baudrate of 74880 bps until the bootloader or application
sets the more standard 115200 baudrate. This UART0 device has two
possible pins for TXD, GPIO1 and GPIO2, which are both set to TXD by the
boot ROM. esp8266 modules will typically have GPIO1 labeled as the TX
pin, but it is possible to use GPIO2 for that purpose even while
flashing the device with esptool.py.

The second device, UART1, also has two options for TXD, GPIO2 and GPIO7,
and only one option for RXD, GPIO8. However, GPIO7 and GPIO8 are used
by the flash internally so those options are not very useful unless
maybe while running from IRAM with the flash disabled, for example for
a debugger over UART1.

This patch allows boards to override UART{0,1}_{R,T}XD in their
periph_conf.h to configure the uart selection. Defining UART1_TX will
make the UART_DEV(1) device available.

Tested with:

```CFLAGS='-DUART1_TXD=GPIO2' make -C tests/periph_uart BOARD=esp8266-esp-12x flash term```

* Connected one USB-UART to the standard GPIO1 and GPIO3 for flashing
  and console. After flashing we see the manual test output at 115200
  bps

* Connected a second USB-UART with RX to GPIO2 running at 74880.

Then run on the first console:
```
> init 1 74880
> send 1 hello
```

The word "hello" appears on the second UART connection.

Note that GPIO2 is used during boot for UART0's TX until the application
or bootloader set it to a regular GPIO, so some boot ROM messages at
74880 bps are visible. After running `init 1 74880` it is set to UART1's
TX.
2021-05-02 12:27:27 +00:00
Gunar Schorcht
6cd9896ac0 cpu/esp: move BACKUP* attributes to esp_common 2020-04-03 18:07:12 +02:00
Gunar Schorcht
464e3a8741 cpu/esp8266: add RTT implementation 2020-03-19 13:59:58 +01:00
Gunar Schorcht
0292f8b6a3 cpu/esp*: move periph/hwrng to cpu/esp_common 2020-02-21 09:09:34 +01:00
MrKevinWeiss
d218b77ff7 cpu/esp8266: Suppress cpu specific i2c_speed_t in doxygen 2019-11-18 11:43:45 +01:00
MrKevinWeiss
02bd107722 cpu/esp8266: Suppress cpu specific gpio_flank_t in doxygen
The enumeration takes both the cpu and the driver, it should only show the driver enum
2019-11-18 11:43:12 +01:00
Gunar Schorcht
ddc91df4ca cpu/esp8266: changes for RTOS SDK 2019-11-14 13:58:22 +01:00
Schorcht
0230d077d4 cpu/esp8266: doxygen problem fix 2019-01-09 16:03:00 +01:00
Gunar Schorcht
1865ee9359 cpu/esp8266: fix of adc_res_t
cpu/esp8266/include/periph_cpu.h overrides the default definition of adc_res_t from periph/adc with a definition which contains only one resolution. This gives compilation errorss if an application uses other resolutions. According to the documentation, adc_sample should return -1 if the resolution is not supported. All other CPUs override adc_res_t either to add new resolutions or to mark resolutions as unsupported. But they all allow to use them at the interface. Therefore, esp8266 uses now the default definition of adc_res_t and returns -1 if a solution is used in adc_sample that is not supported.
2018-11-30 17:56:33 +01:00
smlng
9468feeaaf cpu/esp8266: add missing PERIPH_TIMER_PROVIDES_SET 2018-09-07 22:14:32 +02:00
Schorcht
e4ca897661 cpu: add esp8266 2018-09-05 02:39:50 +02:00