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cpu/esp8266: allow arbitrary SPI clocks

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This commit is contained in:
Benjamin Valentin 2024-02-21 23:15:21 +01:00
parent 9504e07378
commit 75bf0e33e0
2 changed files with 18 additions and 21 deletions
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14
cpu/esp8266/include/periph_cpu.h
View File

@ -24,6 +24,7 @@
#include "eagle_soc.h"
#include "cpu_conf.h"
#include "macros/units.h"
#ifdef __cplusplus
extern "C" {
@ -264,6 +265,19 @@ typedef enum {
HSPI = 1, /**< HSPI interface controller */
} spi_ctrl_t;
/**
* @brief Override SPI clock speed values
* @{
*/
#define HAVE_SPI_CLK_T
typedef enum {
SPI_CLK_100KHZ = KHZ(100), /**< drive the SPI bus with 100KHz */
SPI_CLK_400KHZ = KHZ(400), /**< drive the SPI bus with 400KHz */
SPI_CLK_1MHZ = MHZ(1), /**< drive the SPI bus with 1MHz */
SPI_CLK_5MHZ = MHZ(5), /**< drive the SPI bus with 5MHz */
SPI_CLK_10MHZ = MHZ(10), /**< drive the SPI bus with 10MHz */
} spi_clk_t;
/**
* @brief SPI configuration structure type
*/

25
cpu/esp8266/periph/spi.c
View File

@ -262,28 +262,11 @@ void IRAM_ATTR spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t cl
* https://www.espressif.com/sites/default/files/documentation/esp8266-technical_reference_en.pdf
*/
uint32_t spi_clkdiv_pre;
uint32_t spi_clkcnt_N;
uint32_t spi_clkdiv_pre; /* 13 bit */
uint32_t spi_clkcnt_N; /* 6 bit */
switch (clk) {
case SPI_CLK_10MHZ: spi_clkdiv_pre = 2; /* predivides 80 MHz to 40 MHz */
spi_clkcnt_N = 4; /* 4 cycles results into 10 MHz */
break;
case SPI_CLK_5MHZ: spi_clkdiv_pre = 2; /* predivides 80 MHz to 40 MHz */
spi_clkcnt_N = 8; /* 8 cycles results into 5 MHz */
break;
case SPI_CLK_1MHZ: spi_clkdiv_pre = 2; /* predivides 80 MHz to 40 MHz */
spi_clkcnt_N = 40; /* 40 cycles results into 1 MHz */
break;
case SPI_CLK_400KHZ: spi_clkdiv_pre = 20; /* predivides 80 MHz to 4 MHz */
spi_clkcnt_N = 10; /* 10 cycles results into 400 kHz */
break;
case SPI_CLK_100KHZ: spi_clkdiv_pre = 20; /* predivides 80 MHz to 4 MHz */
spi_clkcnt_N = 40; /* 20 cycles results into 100 kHz */
break;
default: spi_clkdiv_pre = 20; /* predivides 80 MHz to 4 MHz */
spi_clkcnt_N = 40; /* 20 cycles results into 100 kHz */
}
spi_clkcnt_N = 2;
spi_clkdiv_pre = (MHZ(80)/spi_clkcnt_N) / clk;
/* register values are set to deviders-1 */
spi_clkdiv_pre--;