3 Commits

Author	SHA1	Message	Date
Karl Fessel	645cb04c4d	cpu/riscv,gd32v: add CPU_ARCH, CPU_CORE information ... adds CPU_ARCH to riscv_common preparing to handle it like cortex-m does adds CPU_CORE to gd32v	2021-09-22 14:39:44 +02:00
Benjamin Valentin	a9c83017ee	cpu/riscv_common: only select PLIC for fe310 ... Not every RISC-V implements that interrupt controller, gd32v uses CLIC instead.	2021-08-25 10:49:47 +02:00
Koen Zandberg	2692957c0e	riscv_common: Refactor common fe310 code to riscv_common	2021-02-05 09:32:19 +01:00