This patch allows boards to select a max ADC clock speed. This could be
handy if the board wants to clock the ADC differently according to the
board's front end analog circuitry or MCU model's ADC capabilities.
The register access to SMPR1/SMPR2 was incorrect in three aspects:
1. For channels < 10, SMPR1 was cleared but SMPR2 should have been
cleared
2. The code was not thread-safe
3. An unneeded write was issued. (The compiler won't combine the
in-place bitwise operations into a single read-modify-write
sequence on `volatile` memory.)
Fixes https://github.com/RIOT-OS/RIOT/issues/20261
The current implementation uses the core clock frequency to calculate
the needed prescalar to achieve a given ADC clock frequency. This is
incorrect. This patch fixes the calculation to use the correct source
clock (PCKLK2 ie APB2). It also changes the defined max clock rate to
use the frequency macro to improve readability.
