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cpu/{gd32v,stm32}/periph/adc: make ADC clock setable

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This patch allows boards to select a max ADC clock speed. This could be
handy if the board wants to clock the ADC differently according to the
board's front end analog circuitry or MCU model's ADC capabilities.
This commit is contained in:
Joshua DeWeese 2023-05-19 13:10:51 -04:00 committed by Joshua DeWeese
parent c2e1a8e85c
commit 4218fca673
4 changed files with 16 additions and 8 deletions
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6
cpu/gd32v/periph/adc.c
View File

@ -31,7 +31,9 @@
/**
* @brief Maximum allowed ADC clock speed
*/
#define MAX_ADC_SPEED MHZ(14)
#ifndef ADC_CLK_MAX
#define ADC_CLK_MAX MHZ(14)
#endif
/**
* @brief Allocate locks for all three available ADC devices
@ -122,7 +124,7 @@ int adc_init(adc_t line)
}
/* set clock prescaler to get the maximal possible ADC clock value */
for (clk_div = 2; clk_div < 8; clk_div += 2) {
if ((CLOCK_CORECLOCK / clk_div) <= MAX_ADC_SPEED) {
if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
break;
}
}

6
cpu/stm32/periph/adc_f1.c
View File

@ -28,7 +28,9 @@
/**
* @brief Maximum allowed ADC clock speed
*/
#define MAX_ADC_SPEED MHZ(14)
#ifndef ADC_CLK_MAX
#define ADC_CLK_MAX MHZ(14)
#endif
/**
* @brief Allocate locks for all three available ADC devices
@ -93,7 +95,7 @@ int adc_init(adc_t line)
}
/* set clock prescaler to get the maximal possible ADC clock value */
for (clk_div = 2; clk_div < 8; clk_div += 2) {
if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
break;
}
}

6
cpu/stm32/periph/adc_f2.c
View File

@ -29,7 +29,9 @@
/**
* @brief Maximum allowed ADC clock speed
*/
#define MAX_ADC_SPEED MHZ(12)
#ifndef ADC_CLK_MAX
#define ADC_CLK_MAX MHZ(12)
#endif
/**
* @brief Default VBAT undefined value
@ -86,7 +88,7 @@ int adc_init(adc_t line)
}
/* set clock prescaler to get the maximal possible ADC clock value */
for (clk_div = 2; clk_div < 8; clk_div += 2) {
if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
break;
}
}

6
cpu/stm32/periph/adc_f4_f7.c
View File

@ -29,7 +29,9 @@
/**
* @brief Maximum allowed ADC clock speed
*/
#define MAX_ADC_SPEED MHZ(12)
#ifndef ADC_CLK_MAX
#define ADC_CLK_MAX MHZ(12)
#endif
/**
* @brief Maximum sampling time for each channel (480 cycles)
@ -95,7 +97,7 @@ int adc_init(adc_t line)
dev(line)->CR2 = ADC_CR2_ADON;
/* set clock prescaler to get the maximal possible ADC clock value */
for (clk_div = 2; clk_div < 8; clk_div += 2) {
if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
break;
}
}