diff --git a/cpu/gd32v/periph/adc.c b/cpu/gd32v/periph/adc.c
index 4dfdc98a5c..a1868bf72f 100644
--- a/cpu/gd32v/periph/adc.c
+++ b/cpu/gd32v/periph/adc.c
@@ -31,7 +31,9 @@
 /**
  * @brief   Maximum allowed ADC clock speed
  */
-#define MAX_ADC_SPEED           MHZ(14)
+#ifndef ADC_CLK_MAX
+#define ADC_CLK_MAX             MHZ(14)
+#endif
 
 /**
  * @brief   Allocate locks for all three available ADC devices
@@ -122,7 +124,7 @@ int adc_init(adc_t line)
     }
     /* set clock prescaler to get the maximal possible ADC clock value */
     for (clk_div = 2; clk_div < 8; clk_div += 2) {
-        if ((CLOCK_CORECLOCK / clk_div) <= MAX_ADC_SPEED) {
+        if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
             break;
         }
     }
diff --git a/cpu/stm32/periph/adc_f1.c b/cpu/stm32/periph/adc_f1.c
index bb1e1aa2b8..5753eeda90 100644
--- a/cpu/stm32/periph/adc_f1.c
+++ b/cpu/stm32/periph/adc_f1.c
@@ -28,7 +28,9 @@
 /**
  * @brief   Maximum allowed ADC clock speed
  */
-#define MAX_ADC_SPEED           MHZ(14)
+#ifndef ADC_CLK_MAX
+#define ADC_CLK_MAX             MHZ(14)
+#endif
 
 /**
  * @brief   Allocate locks for all three available ADC devices
@@ -93,7 +95,7 @@ int adc_init(adc_t line)
     }
     /* set clock prescaler to get the maximal possible ADC clock value */
     for (clk_div = 2; clk_div < 8; clk_div += 2) {
-        if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
+        if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
             break;
         }
     }
diff --git a/cpu/stm32/periph/adc_f2.c b/cpu/stm32/periph/adc_f2.c
index 8f75c5e3a9..dd8b6b1f5c 100644
--- a/cpu/stm32/periph/adc_f2.c
+++ b/cpu/stm32/periph/adc_f2.c
@@ -29,7 +29,9 @@
 /**
  * @brief   Maximum allowed ADC clock speed
  */
-#define MAX_ADC_SPEED           MHZ(12)
+#ifndef ADC_CLK_MAX
+#define ADC_CLK_MAX             MHZ(12)
+#endif
 
 /**
  * @brief   Default VBAT undefined value
@@ -86,7 +88,7 @@ int adc_init(adc_t line)
     }
     /* set clock prescaler to get the maximal possible ADC clock value */
     for (clk_div = 2; clk_div < 8; clk_div += 2) {
-        if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
+        if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
             break;
         }
     }
diff --git a/cpu/stm32/periph/adc_f4_f7.c b/cpu/stm32/periph/adc_f4_f7.c
index b52fc401c6..ef707b3b47 100644
--- a/cpu/stm32/periph/adc_f4_f7.c
+++ b/cpu/stm32/periph/adc_f4_f7.c
@@ -29,7 +29,9 @@
 /**
  * @brief   Maximum allowed ADC clock speed
  */
-#define MAX_ADC_SPEED           MHZ(12)
+#ifndef ADC_CLK_MAX
+#define ADC_CLK_MAX             MHZ(12)
+#endif
 
 /**
  * @brief   Maximum sampling time for each channel (480 cycles)
@@ -95,7 +97,7 @@ int adc_init(adc_t line)
     dev(line)->CR2 = ADC_CR2_ADON;
     /* set clock prescaler to get the maximal possible ADC clock value */
     for (clk_div = 2; clk_div < 8; clk_div += 2) {
-        if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
+        if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
             break;
         }
     }