Gunar Schorcht
dd0593a3c8
cpu/gd32v: fix clock setting
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Setting the `RCU_CTL` register just to the IRC8M bit also removes the IRC8M calibration and trim adjust value in this register. Therefore IRC8M calibration and trim adjust value have to be preserved and the IRC8M has to be set.
2023-01-08 10:42:01 +01:00
Benjamin Valentin
7abaae7bbd
treewide: fix typos
2022-09-15 12:12:23 +02:00
Marian Buschsieweke
bae91c1660
Merge pull request #17723 from benpicco/periph_timer_periodic-set_stopped
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drivers/periph/timer: add TIM_FLAG_SET_STOPPED flag
2022-05-03 12:06:37 +02:00
Benjamin Valentin
7ed69cc08a
cpu/gd32v: timer: implement TIM_FLAG_SET_STOPPED
2022-04-28 13:27:59 +02:00
Ollrogge
41f961a197
periph/flashpage: Add _in_address_space feature
2022-03-17 19:45:54 +01:00
Benjamin Valentin
55454e9301
cpu/gd32v: timer: add ; after DEBUG()
2021-12-08 18:30:24 +01:00
Benjamin Valentin
90a6d90df8
cpu/gd32v: uart: fix function parameter
2021-11-18 10:14:51 +01:00
Leandro Lanzieri
a015508e77
cpu/gd32v: model Kconfig
2021-10-01 11:26:15 +02:00
Karl Fessel
fe03c4c059
cpu/riscv,gd32: match Kconfig to Makefile changes
2021-09-22 15:50:28 +02:00
Karl Fessel
645cb04c4d
cpu/riscv,gd32v: add CPU_ARCH, CPU_CORE information
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adds CPU_ARCH to riscv_common preparing to handle it like cortex-m does
adds CPU_CORE to gd32v
2021-09-22 14:39:44 +02:00
Benjamin Valentin
a75ae3c938
cpu/riscv_common: move C lib selection to common place
2021-08-25 10:53:00 +02:00
Benjamin Valentin
e92a4b9628
cpu/gd32v: enable periph_timer_periodic
2021-08-25 10:48:48 +02:00
3d470b0c12
cpu/gd32v: Initial include of the GD32VF103 device
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This adds support for the gd32v class devices from Gigadevice. The
gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as
the stm32f1 devices
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-08-24 14:30:23 +02:00
