The lpc23xx MCU has up to three I2C interfaces.
This adds a driver for it.
The peripheral works in interrupt mode, each change of the state machine
will generate an interrupt.
The response to the states are laid out in the data sheet.
This replaces the old driver that was removed in c560e28eb6
From the data sheet:
> **Note:** Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the V DD(DCDC)(3V3) voltage was below 2.6 V or not.
So the value of BODR is undefined if POR is set.
Clear it to bring it to a defined state.
The function would always return `true` after early boot, so it
is not very useful for applications.
Now it will only (but always) return true when we woke from Deep Sleep
*after* early boot. This makes it behave the same ways as the function
of the same name on SAME54.
Rename the existing function to cpu_backup_ram_is_initialized() to better
match it's semantics.
On the MCB2388 plugging the power will result in both the POR and EXTR
bit being set.
Not sure if this is a property of the board, but it means RTC is also
reset after programming, so it behaves just like Backup RAM.
If we woke from Deep Sleep the POR bit will be cleared, so the RTC is not
reset.
RSIR is 0x1 (POR) if we woke from Deep Sleep.
This makes it hard to distinguish between real power-on and waking from
Deep Sleep, which is why the Backup RAM signature was introduced.
However, calling cpu_woke_from_backup() a second time will always return
true, as the signature will have been set up by early boot then.
Thus, clear the POR bit if the signature was already in place.
The result is:
RSIR == 0 -> woke from sleep
RSIR == 1 -> cold boot
Calling localtime() adds considerable overhead.
There are easier ways to set the date to 1970.
For tests/periph_rtc this results in this ROM change:
master:
text data bss dec hex
31328 240 98064 129632 1fa60
with this patch:
text data bss dec hex
20036 140 98168 118344 1ce48
For better compatibility copy most of cortexm_base.ld
and use the same section names.
Only interrupt stacks and the two additional (currently unused)
heap sections are different between the two now.
Both architectures are variants of the ARM architecture and use the same
toolchain.
There is no reason to have such wildly different defaults.
This results in some tests passing that would crash before:
- [x] `tests/pkg_libcose`
- [x] `tests/pkg_qdsa`
- [x] `tests/pkg_relic`
- [x] `tests/pkg_tweetnacl`
- [x] `tests/pthread_tls`
`THREAD_EXTRA_STACKSIZE_PRINTF_FLOAT` is not used anywhere in RIOT
anymore, so just drop it.
Setting up the .data and .bss section happens in arm7_init.c now.
The code was commented out anyway, so just remove it.
Also remove leftover variable declarations that were only used in
the dead code.
lpc23xx has 2k of battery RAM that is retained in Deep Power Down mode.
To not overwrite that data it must only be initialized on Power On Reset.
However, RSIR looks the same when waking up from Deep Power Down as it does
on the power-on case.
So use 4 bytes of the backup RAM to keep a signature that is only valid if
memory was retained (no power-on Reset).
A small change to the linker script is required so two sections can be
placed into flash.
The 10 bit DAC on the lpc23xx is very simple.
It only has one channel and can only be mapped to a single pin (P0.26).
After setting the pin mode to DAC no further configuration in needed.
puf_sram only relies on an uninitialized chunk of memory.
This means to enable it we just have to hook up puf_sram_init().
All memory after __bss_end should be uninitialized at startup, so
just use that.
Enable IDLE and Deep Powerdown mode.
IDLE is pretty straightforward - insteady of busy waiting, the CPU will
enter an idle state from which it will resume on any event.
Deep Power Down shuts off the entite system except for the battery backup
power domain.
That means the CPU will reset on resume and can be woken by e.g. RTC.
SLEEP and POWERDOWN disable the PLL and the PLL and Flash respectively.
This requires some proper wake-up handling.
Since this turned out to be a major time sink and those modes are never
currently never used in RIOT outside of tests, I left this as an exercise
for a future reader.
This converts the hard-coded UART driver to the new ways.
- allow the board to configure the RX & TX pins
- allow for more than one UART
- allow setting the baudrate
- implement poweron()/poweroff() functions
Currently the cpu/lpc2387 init code hard-codes a 16 MHz
external oscillator.
Instead, calculate the PLL multiplier based on the board define
and also allow to run without an external oscillator.
At the time of configuration, the pthread-reaper uses '164' bytes of
stack when 'idle' stack is only '160'. By having double it gives some
margin.
ps
pid | name | state Q | pri | stack ( used) | base addr | current
1 | idle | pending Q | 15 | 160 ( 128) | 0x4000007c | 0x4000009c
2 | main | running Q | 7 | 2560 ( 1232) | 0x4000011c | 0x4000095c
3 | pthread-reaper | bl rx _ | 0 | 320 ( 164) | 0x40000bac | 0x40000c48
| SUM | | | 3040 ( 1524)
A naive implementation may set a RTC alarm in 30s by calling
struct tm now;
rtc_get_time(&now);
now.tm_sec += 30;
rtc_set_alarm(&now, _cb, NULL);
This works for RTC implementations that use a RTT internally and call
mktime() to convert the struct tm to a unix timestamp, as mktime() will
normalize the struct in the process.
Call rtc_tm_normalize() when the RTC uses separate registers for time / date
components to ensure it is normalized.
This also modifies tests/periph_rtc to exercise this case.
- split up interrupt vector code from bootloader.c to vectors.c
- moved bootloader.c to arm7_init.c
- Use consistent naming:
- use lower case for everything but preprocessor stuff
- ISRs now named isr_foo()
Rational: the periph_common module is required by (most) other periph drivers
and also during startup of the CPU/MCU to run periph_init. The latter is only
required if other periph drivers are used, hence periph_common should be a
depency of periph_* modules and *not* of the CPU/MCU. This PR fixes that
by making periph_common a depency of periph_* and removing the explicit
include in the CPU/MCU implementation.
If the .noinit section starts at the beginning of the RAM,
a bootloader that is unaware of it will clear it.
Instead, move it behind the .bss section, hoping that a bootloader
will always use less .bss memory than RIOT proper.
