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2eb800cb8b
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cpu/fe310: use coreclk instead of cpu_freq
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2021-12-15 13:14:19 +01:00 |
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2692957c0e
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riscv_common: Refactor common fe310 code to riscv_common
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2021-02-05 09:32:19 +01:00 |
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ba518ede09
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cpu/fe310: Uncrustify code
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2021-01-15 12:02:55 +01:00 |
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bef82edf43
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fe310: Adapt peripherals to use the plic driver
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2020-08-31 16:26:43 +02:00 |
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3f29eb9efb
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cpu/fe310: use CLOCK_CORECLOCK macro to get cpu freq
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2020-01-10 16:41:33 +01:00 |
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4eba1427d2
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cpu/fe310: uart_init(): drain RX fifo before enabling RX IRQ
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2020-01-07 13:16:02 +01:00 |
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e2f88abe63
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cpu/fe310: periph_uart: only call rx_cb if set
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2020-01-07 13:14:08 +01:00 |
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e5c64c739a
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cpu/fe310: rework uart driver implem/config
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2019-12-20 15:22:09 +01:00 |
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smlng
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59e299635b
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cppcheck: add/correct reason for cppcheck-suppress
Adding and correcting description/rational on why certain cppcheck
warnings or errors are intentionally suppressed.
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2018-09-25 12:03:58 +02:00 |
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kenrabold
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7d1d5e77d8
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cpu/fe310: add RISC-V cpu FE310
New CPU FE310 from SiFive based on RISC-V architecture
build: add makefile for RISC-V builds
Makefile for builds using RISC-V tools
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2018-05-29 15:21:45 -07:00 |
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