- the timeout computation for the spurious IRQ test confused numerator
and denominator in a fraction
- the timeout offset between timer channels was hardcoded to 5000 from
when the timer was only tested with 1 MHz as frequency
- This resulted in slooooow test runs when running at slow
frequencies
- fix overflow handling in the spinning wait
- likely this would never overflow anyway assuming that
`timer_init()` resets the counter value, but let's not rely on
this and just fix the bug for good
If the feature periph_timer_query_freqs is provided, use the
corresponding function to iterate over all supported frequencies to
increase test coverage.
This test sporadically failed on multiple machines compiled with both
GNU and LLVM toolchains. To not waste more CI time by sporadically
failing unrelated CI runs, let's disable the test for now.
- Detect when the same timer is used by `ztimer` (pulled in as
dependency for a peripheral driver, e.g. `periph_adc` on STM32F3) and
the test application
- Try to provide a better default (e.g. `TIMER_DEV(1)` when
`ztimer_periph_timer` is in use, `TIMER_DEV(0)` otherwise)
The R-2R resistor ladder dac --> ADC test was disabled due to a bug in
the v0.1 version of the shield. Since this has been fixed in v0.2 and
v0.3 of the shield, it can be re-enabled.
The comment regarding the high accuracy of the resistor is dropped, as
v0.3 has been ordered with cost efficient resistors rather than with
accurate ones. As a result, the tolerance for error has been increased
to 10%. This quite a bit more lax than I have hoped for, but false
positives would be something to avoid.
- fix a copy-paste error (`TIMER_FREQ_UART_TEST` was used in the SPI
test, but that should be `TIMER_FREQ_SPI_TEST`)
- use 400 kHz as slow SPI frequency, as faster STM32 MCUs just cannot
divide the APB clock down to 100 kHz
- when detailed output is enabled, print the SPI clock in addition to
the SPI mode to ease figuring out what went wrong
- only have one `FAILURE` message for a too fast byte transfer per
check, rather than per transmitted byte, to reduce the noise
- work around a bug of `periph_timer` on STM32 by reducing the clock
speed of the timer for the SPI test
The test should execute only with `make test-with-config` and not with
`make test`, as boards without the shield cannot pass the test.
For some reason I accidentally added both variants, which makes no
sense. This drops the `make test` variant.
Finally, the `README.md` is updated to refer to `make test-with-config`
instead of `make test`.
This test application makes use of the RIOT Peripheral Selftest Shield,
which connects e.g. PWM to ADC or SPI MOSI to SPI MISO, UART TXD to RXD,
etc. This provides quick and fully automated self testing capabilities.
Please note that the simplicity and ease of use of the hardware comes
with a prices: There are whole classes of issues that cannot be detected
automatically. This test cannot replace other testing approaches
(such as manual testing or PHiLIP on the HiL), but only complement them.
20022: pkg/lwip: add support for slipdev r=benpicco a=benpicco
20025: tests/drivers/at: fix device table overflow r=benpicco a=krzysztof-cabaj
### Contribution description
This PR fix device table overflow in `tests/driver/at`, which could lead to device crash.
### Testing procedure
PR was tested on two nucleo boards with 2 and 3 UARTs (nucleo-l476rg and nucleo-l496zg).
Flash `tests/driver/at` with and without this PR.
Output with this PR:
```
> main(): This is RIOT! (Version: 2022.07-devel-5083-g2b9e8-tests-drivers-at)
AT command test app
> init 5 9600
Wrong UART device number - should by in range 0-2.
>
```
Output without this PR:
```
> main(): This is RIOT! (Version: 2022.07-devel-5083-g2b9e8)
AT command test app
> init 5 9600
8001afd
*** RIOT kernel panic:
FAILED ASSERTION.
*** halted.
Context before hardfault:
r0: 0x0000000a
r1: 0x00000000
. . .
```
### Issues/PRs references
None
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Co-authored-by: krzysztof-cabaj <kcabaj@gmail.com>
