Marian Buschsieweke
dd48ced151
cpu/*/atomic_utils_arch.h: Add volatile qualifier
2020-11-24 14:00:52 +01:00
792e031a95
Merge pull request #14331 from maribu/atomic_utils
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sys/atomic_utils: Functions for atomic access
2020-11-12 21:44:53 +01:00
Marian Buschsieweke
ce0982485d
cpu/fe310: Add atomic_utils_arch.h
2020-11-10 10:55:13 +01:00
Bas Stottelaar
fb61443bbd
cpu/*: remove unused assert.h include
2020-10-22 11:13:09 +02:00
Marian Buschsieweke
94eab47b26
cpu/fe310: Add architecture_arch.h
2020-09-29 12:34:00 +02:00
Benjamin Valentin
2647f5f3c2
cpu/fe310: run RTT at 1 Hz if RTC is selected
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The RTC on the fe310 is emulated using the RTT.
This only works if the RTT frequency is 1 Hz, so default to that
value in case `periph_rtc` is selected.
2020-09-27 22:45:04 +02:00
ace160a2a3
boards/hifive1: use MHZ utility macro for clock frequency
2020-09-09 14:14:39 +02:00
498646aa17
fe310: Remove vendor plic driver
2020-08-31 16:26:43 +02:00
1d999a1335
fe310: Make header guard unique for plic vendor header
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Otherwise it conflicts with the other plic.h header
2020-08-31 16:26:43 +02:00
3180a11b51
fe310: Add PLIC peripheral driver
2020-08-31 16:26:42 +02:00
Francisco Molina
442b11d0ee
cpu/fe310: add unified rtt configuration
2020-08-12 14:46:59 +02:00
3d9421571c
cpu/fe310: migrate to inlined irq API
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Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
2020-06-26 10:48:56 +02:00
ee3fc27e96
cpu/fe310: implement driver for watchdog
2020-04-07 14:37:55 +02:00
Sören Tempel
bd2f5fe110
fe310: fix power management configuration
2020-01-30 10:43:01 +01:00
Francisco
f76f7c73ce
Merge pull request #12957 from aabadie/pr/cpu/fe310_spi
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cpu/fe310: add spi peripheral driver
2020-01-14 10:54:47 +01:00
Tristan Bruns
532cdc64ff
cpu/fe310: implement SPI
2020-01-11 13:06:39 +01:00
298d573280
cpu/fe310: provide i2c driver
2020-01-11 13:06:10 +01:00
fc911bf6c5
cpu/fe310: rework clock initialization
2020-01-10 16:41:33 +01:00
97e1c7ba7e
cpu/fe310: reorganize files and includes
2020-01-10 16:41:33 +01:00
e5c64c739a
cpu/fe310: rework uart driver implem/config
2019-12-20 15:22:09 +01:00
b49cca2d0c
cpu/fe310: include thread.h in cpu.h
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This ensures the ARRAY_SIZE macro is implicitly available
2019-12-13 16:25:11 +01:00
Marian Buschsieweke
314184adb5
cpu: Platform specific C11 atomics compat headers
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Added headers to define platform specific sizes and types for the C11 atomics
compatibility module for C++.
2019-10-24 23:08:36 +02:00
Kevin "Tristate Tom" Weiss
4b7c5915ec
Merge pull request #10953 from gschorcht/sys/shell/heap_cmd/pr
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sys/shell: add heap command
2019-10-04 13:49:57 +02:00
kenrabold
1d6e37a7f7
cpu/fe310: interrupt handling cleanup
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Cleanup of FE310 interrupt handler code
Optimization of intr context frame
Reduce size of intr stack
Added unhandled trap output
Fix PR #12237
2019-09-27 13:32:43 -07:00
Gunar Schorcht
dfef2ce638
cpu/fe310: changes for common heap command
2019-09-05 09:20:55 +02:00
kenrabold
97d1dc0821
cpu/fe310: Add support for FE310_G002
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Added support for FE310_G002 CPU variant that is on new HiFive1B board
2019-07-19 13:25:17 -07:00
smlng
740eafe93b
cpu/fe310: add missing PERIPH_TIMER_PROVIDES_SET
2018-09-07 22:15:13 +02:00
kenrabold
db4d67c4fd
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY
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Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit
build: fixed missing syscall and cpuid failures
Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph
build: fixed whitespace error
build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY
doc: fixed doxygen warnings
Addressed Doxygen warnings in source file comments
doc: more doxygen fixes
doc: even more doxygen fixes
doc: more changes
build: fix pedantic and rdci_simple build failures
make: exclude lua
2018-05-29 16:27:53 -07:00
kenrabold
7d1d5e77d8
cpu/fe310: add RISC-V cpu FE310
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New CPU FE310 from SiFive based on RISC-V architecture
build: add makefile for RISC-V builds
Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00
