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Commit Graph

105 Commits

Author SHA1 Message Date
Jan Romann
4384795cb9
treewide: Remove excessive newlines 2021-08-13 19:50:38 +02:00
Benjamin Valentin
6d42c9fcfe cpu: make newlib_nano a DEFAULT_MODULE
This allows to disable nanospecs with

    DISABLE_MODULE += newlib_nano

if a full-features version of newlib is desired.
2021-05-04 12:12:36 +02:00
Benjamin Valentin
d47a880915 cpu: add periph_rtt_overflow feature
The RTT overflow callback is not available on all RTT implementations.
This means it is either a no-op or `rtt_set_overflow_cb()` is a no-op
or it will overwrite the alarm set with `rtt_set_alarm()`.

This adds a feature to indicate that proper overflow reporting is available.
2021-04-30 11:58:00 +02:00
Marian Buschsieweke
ab89234040
drivers/periph/rtt: add periph_rtt_set_counter feature
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
2021-03-08 14:16:46 +01:00
Marian Buschsieweke
b9cb75fedf
drivers/periph/rtt: add periph_rtt_set_counter feature
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
2021-03-04 18:05:06 +01:00
4dc7f33b2b
cpu/fe310: set newlib as default libc 2021-02-11 21:49:43 +01:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
ce97e9d8ce
Merge pull request #15859 from fjmolinas/pr_newlib_feature
treewide: model newlib as a FEATURE
2021-01-27 10:06:08 +01:00
Francisco Molina
63a2a6ce1b
treewide: model newlib as a FEATURE 2021-01-27 09:24:25 +01:00
128423edc6
cpu/fe310: Use newlib_syscalls_default stub implementations
This switches the fe310 to use the common newlib_syscalls_default
implementation.
2021-01-26 13:42:52 +01:00
b57b3d490d
cpu/fe310: Allow using immediates for ecall arguments
The mv instruction (which is usually implemented as `add rd, x0, r1`) is
changed to `add rd, x0, %input`. This can either be used as a load
immediate or as an move.

The code size grows by two bytes. This because GCC does not compress the
li instruction to the compressed version (even though this is possible).
2021-01-22 20:49:52 +01:00
896227ab08
cpu/fe310: Add used registers to clobbers 2021-01-22 20:49:17 +01:00
9979646b8b
cpu/fe310: Inline thread_yield_higher function 2021-01-19 11:03:21 +01:00
ba518ede09
cpu/fe310: Uncrustify code 2021-01-15 12:02:55 +01:00
5a203413a1
cpu/fe310: Remove software IRQ handling 2021-01-13 12:51:32 +01:00
1b2adb4821
cpu/fe310: Use ecall instruction for thread yield 2021-01-13 12:51:25 +01:00
73d3232f67
Merge pull request #15673 from maribu/fe310-malloc
cpu/fe310: use malloc_thread_safe
2020-12-21 13:29:02 +01:00
Marian Buschsieweke
b422ef9970
cpu/fe310: use malloc_thread_safe 2020-12-18 10:29:37 +01:00
dc77914ce8
cpu/fe310: add clock configuration header 2020-12-17 15:53:31 +01:00
aaca1331ca
cpu/fe310: move clock Kconfig to cpu 2020-12-17 15:53:31 +01:00
575189510d
Merge pull request #15465 from maribu/atomic-utils-volatile
sys/atomic_utils: Use volatile qualifier
2020-11-24 22:05:33 +01:00
Marian Buschsieweke
dd48ced151
cpu/*/atomic_utils_arch.h: Add volatile qualifier 2020-11-24 14:00:52 +01:00
Marian Buschsieweke
21bf7c0d01
cpu/fe310: Silence -Wcast-align 2020-11-18 09:58:52 +01:00
792e031a95
Merge pull request #14331 from maribu/atomic_utils
sys/atomic_utils: Functions for atomic access
2020-11-12 21:44:53 +01:00
Marian Buschsieweke
ce0982485d
cpu/fe310: Add atomic_utils_arch.h 2020-11-10 10:55:13 +01:00
Marian Buschsieweke
125c892c03
drivers/periph/timer: Use uint32_t for frequency
For all currently supported platforms `unsigned long` is 32 bit in width. But
better use `uint32_t` to be safe.
2020-10-30 22:02:12 +01:00
Bas Stottelaar
22243aec7a cpu/*: realign ENABLE_DEBUG 2020-10-23 00:46:26 +02:00
Bas Stottelaar
fb61443bbd cpu/*: remove unused assert.h include 2020-10-22 11:13:09 +02:00
Bas Stottelaar
ab6188cea3 cpu/*: add missing include of assert.h 2020-10-22 11:13:08 +02:00
8df645cfe9
Merge pull request #15011 from benpicco/picolobc_feature
picolibc: model as a feature
2020-10-14 17:02:04 +02:00
Benjamin Valentin
45270dada0 cpu/fe310: blacklist picolibc on CI
The RISC-V toolchain in riotdocker has issues with picolibc and
will still include newlib headers.

This leads to conflicts like

```
In file included from [01m[Knanostubs.c:22[m[K:
[01m[K/usr/local/picolibc/riscv-none-embed/include/stdio.h:270:23:[m[K [01;31m[Kerror: [m[Kconflicting types for '[01m[K__FILE[m[K'
 typedef struct __file [01;31m[K__FILE[m[K;
                       [01;31m[K^~~~~~[m[K
In file included from [01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/reent.h:93[m[K,
                 from [01m[Knanostubs.c:20[m[K:
[01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/sys/reent.h:287:26:[m[K [01;36m[Knote: [m[Kprevious declaration of '[01m[K__FILE[m[K' was here
 typedef struct __sFILE   [01;36m[K__FILE[m[K;
                          [01;36m[K^~~~~~[m[K
```

The problem does not occur when installing both the toolchain and picolibc
directly from the Debian / Ubuntu repositories, but CI uses an older Ubuntu
version that does not have those packages yet, so it builds them manually.

Blacklist RISC-V until CI has been updated.
2020-10-14 16:32:01 +02:00
60f39ddba8
cpu/fe310: fix typo 'transfert' -> 'transfer' 2020-10-02 07:55:36 +02:00
Marian Buschsieweke
94eab47b26
cpu/fe310: Add architecture_arch.h 2020-09-29 12:34:00 +02:00
Benjamin Valentin
2647f5f3c2 cpu/fe310: run RTT at 1 Hz if RTC is selected
The RTC on the fe310 is emulated using the RTT.
This only works if the RTT frequency is 1 Hz, so default to that
value in case `periph_rtc` is selected.
2020-09-27 22:45:04 +02:00
a1473431da
Merge pull request #14878 from benpicco/cpu/fe310/rtc_mktime
cpu/fe310: RTC: use rtc_mktime()
2020-09-25 21:19:04 +02:00
Benjamin Valentin
d092c12a66 cpu/fe310: RTC: use rtc_mktime()
Use RTC helper functions instead of libc functions.
This gives us y2038 safety by the extended epoch and saves
a good chunk of memory:

picolibc mktime():

   text	   data	    bss	    dec	    hex	filename
  15048	    520	   2504	  18072	   4698	tests/periph_rtc/bin/hifive1/tests_periph_rtc.elf

rtc_mktime():

   text	   data	    bss	    dec	    hex	filename
   7632	     40	   2452	  10124	   278c	tests/periph_rtc/bin/hifive1/tests_periph_rtc.elf
2020-09-25 18:22:10 +02:00
Benjamin Valentin
cff8e862b8 picolibc: model as a feature 2020-09-15 22:11:21 +02:00
cdbb3e025a
cpu/fe310: boards/hifive1*: use IS_ACTIVE where possible 2020-09-09 14:14:39 +02:00
ace160a2a3
boards/hifive1: use MHZ utility macro for clock frequency 2020-09-09 14:14:39 +02:00
49e11626d3
cpu/fe310: ensure all clock modes are built 2020-09-09 14:14:39 +02:00
36ecb40dd9
Merge pull request #14919 from bergzand/pr/fe310/unify_ld
fe310: Unify linker scripts
2020-09-01 18:03:46 +02:00
32399901f0
fe310: Unify linker scripts
Similar to the cortex-m common linker scripts, the RISC-V linker scripts
can be unified easily, requiring only the memory addresses and lengths.
This simplifies adding new RISC-V CPU's later
2020-09-01 14:39:55 +02:00
53ac29aca4
Merge pull request #14887 from bergzand/pr/fe310/plic_periph
fe310: Add custom PLIC driver as peripheral
2020-08-31 21:25:03 +02:00
498646aa17
fe310: Remove vendor plic driver 2020-08-31 16:26:43 +02:00
bef82edf43
fe310: Adapt peripherals to use the plic driver 2020-08-31 16:26:43 +02:00
1d999a1335
fe310: Make header guard unique for plic vendor header
Otherwise it conflicts with the other plic.h header
2020-08-31 16:26:43 +02:00
3180a11b51
fe310: Add PLIC peripheral driver 2020-08-31 16:26:42 +02:00
889ea15936
fe310: Use read-modify-store instruction on GPIO
The rv32imac supports the A (atomic) extensions containing
read-modify-store operations. This commit modifies the GPIO code to use
these for all bitwise operations. The atomic operations are emitted with
relaxed ordering as they do not require multiprocessor synchronization.

This decreases the duration of the gpio operations from 59 ns to 50 ns
per call. depending a bit on the type of operation.
2020-08-29 09:24:02 +02:00
1e5dc928ad
fe310: Split sched_run call from handle_trap
This is a small optimization to the RISC-V trap handler. By splitting
the call to sched_run from the trap_handle call, loading the previous
thread ptr can be delayed until after it is determined that a schedule
run is required. This shaves of a few cycles during regular interrupts
that do not trigger the scheduler.
2020-08-28 14:17:58 +02:00
4289b09a33
fe310: Skip most context save on null thread 2020-08-28 14:17:56 +02:00