The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTT
driver.
Unify the drivers and move them to sam0_common.
This removes doing `filter-out periph_hwrng, $(FEATURES_PROVIDED)`
after processing `cpu/$(CPU)/Makefile.features`.
The current solution is a HACK as `CPU_MODEL` is currently not available
at that moment but will be in the near future.
It will allow always including `cpu/$(CPU)/Makefile.features` after
`boards/$(BOARD)/Makefile.features`.
It is a part of moving `CPU/CPU_MODEL` definitions to `Makefile.features`.
UART devices are now configured using static array in header files instead of static variables in implementation to be able to define UART_NUMOF using the size of the array instead of a variable.
I2C devices are now configured using static array in header files instead of static variables in implementation to be able to define I2C_NUMOF using the size of the array instead of a variable.
DAC pins are now configured using static arrays in header files instead of static variables in implementation to be able to define DAC_NUMOF using the size of these arrays instead of a variable.
ADC pins are now configured using static arrays in header files instead of static variables in implementation to be able to define ADC_NUMOF using the size of these arrays instead of a variable.
Functions that are used by ADC and DAC peripherals are moved to a new submodule periph_adc_ctrl. This is necessary to compile separate submodules for ADC and DAC.
`top_of_stack` isn't aligned down to the previous 16 byte aligned address. Furthermore, `top_of_stack` as well as `XT_CP_SIZE` are used unaligned in `cpu/esp_common/vendor/xtensa/portasm.S` in the address computation for the coprocessor save area, .
Aligning pointer `p` down to the previous 16 byte aligned address results in a wrong address of the coprocessor save area during the initialization of the thread context. This leads to wrong values and wrong positions of these values in the coprocessor save area in inital thread context.
Since ESP8266 doesn't have a coprocessor, this bug affects only ESP32.
During the flash step esptool.py gives the following warning:
WARNING: Flash size arguments in megabits like '16m' are deprecated.
Please use the equivalent size '2MB'.
Megabit arguments may be removed in a future release.
esptool.py v2.7-dev
This patch replaces '16m' with '2MB' to enable future compatibility.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTC
driver.
Unify the drivers and move them to sam0_common.
Usually, the access to the IROM (flash) memory requires 32-bit word aligned reads. Attempts to access data in the IROM (flash) memory less than 32 bits in size triggers a LoadStoreError exception. With the exception handler from esp-open-rtos it becomes possible to access data in IROM (flash) with a size of less than 32 bits and thus to place .rodata sections in the IROM (flash).
Fix of #11354: Function '_write_r' of ESP32's newlibc does not write the output of function 'write(STDIO_FILENO, ...)' to the UART interface. To fix this problem, module 'newlib_syscalls_default' is now used by default. Function '_write_r' of module 'newlib_syscalls_default' uses 'stdio_write' which in turn uses 'uart_write' if module 'stdio_uart' is used which is now the default case for ESP32.
This commit cleans up magic number and defines bitfields.
Adds error codes for ADDR/DATA NACK and ARBLOSS
Adds error handling, it corrects when an error occurs
Protects from flags that could lockup the bus
