6 Commits

Author	SHA1	Message	Date
Teufelchen1	0e839654e8	cpu/riscv: Add PMP driver	2023-06-28 11:55:34 +02:00
Koen Zandberg	2692957c0e	riscv_common: Refactor common fe310 code to riscv_common	2021-02-05 09:32:19 +01:00
Alexandre Abadie	3d9421571c	cpu/fe310: migrate to inlined irq API ... Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>	2020-06-26 10:48:56 +02:00
Gunar Schorcht	dfef2ce638	cpu/fe310: changes for common heap command	2019-09-05 09:20:55 +02:00
kenrabold	db4d67c4fd	make: add hifive1 to BOARD_INSUFFICIENT_MEMORY ... Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua	2018-05-29 16:27:53 -07:00
kenrabold	7d1d5e77d8	cpu/fe310: add RISC-V cpu FE310 ... New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools	2018-05-29 15:21:45 -07:00