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7d1d5e77d8
New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
44 lines
863 B
C
44 lines
863 B
C
/*
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* Copyright (C) 2017 Ken Rabold
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup cpu_fe310
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* @ingroup cpu
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* @brief CPU specific implementations for the SiFive FE310 cpu
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* @{
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*
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* @file
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* @brief CPU specific configuration options
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*
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* @author Ken Rabold
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
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#define THREAD_EXTRA_STACKSIZE_PRINTF (256)
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#endif
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#ifndef THREAD_STACKSIZE_DEFAULT
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#define THREAD_STACKSIZE_DEFAULT (1024)
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#endif
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#ifndef THREAD_STACKSIZE_IDLE
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#define THREAD_STACKSIZE_IDLE (256)
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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