RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity

cpu/stm32: remove redundant conditional compile

Browse Source 
This patch removes a largely redundant block of conditional includes.

The removed includes are moved into the family specific headers so that
the more specific headers may override defaults defined in the shared
headers.
This commit is contained in:
Joshua DeWeese 2024-03-20 11:29:25 -04:00
parent 17ec57ee6d
commit fd105b7e77
9 changed files with 15 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
cpu/stm32/include/clk/c0/cfg_clock_default.h
View File

@ -19,6 +19,8 @@
#ifndef CLK_C0_CFG_CLOCK_DEFAULT_H
#define CLK_C0_CFG_CLOCK_DEFAULT_H
#include "cfg_clock_common_fx_gx_mp1_c0.h"
#ifdef __cplusplus
extern "C" {
#endif

11
cpu/stm32/include/clk/clk_conf.h
View File

@ -22,17 +22,6 @@
#include "kernel_defines.h"
#include "macros/units.h"
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32C0)
#include "cfg_clock_common_fx_gx_mp1_c0.h"
#else /* CPU_FAM_STM32L0 || CPU_FAM_STM32L1 || CPU_FAM_STM32L4 ||
* CPU_FAM_STM32L5 || CPU_FAM_STM32U5 || CPU_FAM_STM32WB */
#include "cfg_clock_common_lx_u5_wx.h"
#endif
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
#include "f0f1f3/cfg_clock_default.h"

2
cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h
View File

@ -26,6 +26,8 @@
#ifndef CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
#define CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
#include "cfg_clock_common_fx_gx_mp1_c0.h"
#ifdef __cplusplus
extern "C" {
#endif

2
cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h
View File

@ -19,6 +19,8 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_H
#include "cfg_clock_common_fx_gx_mp1_c0.h"
#if defined(CPU_FAM_STM32F2)
#include "f2f4f7/cfg_clock_default_120.h"
#elif defined(CPU_FAM_STM32F4)

2
cpu/stm32/include/clk/g0g4/cfg_clock_default.h
View File

@ -23,6 +23,8 @@
#ifndef CLK_G0G4_CFG_CLOCK_DEFAULT_H
#define CLK_G0G4_CFG_CLOCK_DEFAULT_H
#include "cfg_clock_common_fx_gx_mp1_c0.h"
#ifdef __cplusplus
extern "C" {
#endif

1
cpu/stm32/include/clk/l0l1/cfg_clock_default.h
View File

@ -19,6 +19,7 @@
#ifndef CLK_L0L1_CFG_CLOCK_DEFAULT_H
#define CLK_L0L1_CFG_CLOCK_DEFAULT_H
#include "cfg_clock_common_lx_u5_wx.h"
#include "periph_cpu.h"
#ifdef __cplusplus

2
cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h
View File

@ -21,6 +21,8 @@
#ifndef CLK_L4L5WX_CFG_CLOCK_DEFAULT_H
#define CLK_L4L5WX_CFG_CLOCK_DEFAULT_H
#include "cfg_clock_common_lx_u5_wx.h"
#ifdef __cplusplus
extern "C" {
#endif

2
cpu/stm32/include/clk/mp1/cfg_clock_default.h
View File

@ -19,6 +19,8 @@
#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_H
#define CLK_MP1_CFG_CLOCK_DEFAULT_H
#include "cfg_clock_common_fx_gx_mp1_c0.h"
/**
* @name MP1 clock PLL settings (208MHz)
* @{

2
cpu/stm32/include/clk/u5/cfg_clock_default.h
View File

@ -19,6 +19,8 @@
#ifndef CLK_U5_CFG_CLOCK_DEFAULT_H
#define CLK_U5_CFG_CLOCK_DEFAULT_H
#include "cfg_clock_common_lx_u5_wx.h"
#ifdef __cplusplus
extern "C" {
#endif