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Merge #19677 #19683

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19677: boards/nucleo-l432k: provide three periph_timer instances r=maribu a=maribu

### Contribution description

- `cpu/stm32/periph_timer`: Generalize to also work with timers that do not have 4 channels
- `boards/common/stm32`: Add timer config for three timers based on TIM2, TIM15, and TIM16 (the three general-purpose timers of the STM32L4)
- `boards/nucleo-l432kc`: Make use of the new timer config


19683: cpu/sam0_eth: clean up init() r=maribu a=benpicco





Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
This commit is contained in:
bors[bot] 2023-05-30 20:01:21 +00:00 committed by GitHub
commit f10426709c
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 100 additions and 13 deletions
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73
boards/common/stm32/include/cfg_timer_tim2_tim15_tim16.h Normal file
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@ -0,0 +1,73 @@
/*
* Copyright (C) 2023 Otto-von-Guericke-Universität Magdeburg
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Common configuration for STM32 Timer peripheral based on TIM2,
* TIM15, and TIM16
*
* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
*/
#ifndef CFG_TIMER_TIM2_TIM15_TIM16_H
#define CFG_TIMER_TIM2_TIM15_TIM16_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Please note: This likely needs some generalization for use in STM32 families
* other than L4. */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR1_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
},
{
.dev = TIM15,
.max = 0x0000ffff,
.rcc_mask = RCC_APB2ENR_TIM15EN,
.bus = APB2,
.irqn = TIM1_BRK_TIM15_IRQn,
.channel_numof = 2,
},
{
.dev = TIM16,
.max = 0x0000ffff,
.rcc_mask = RCC_APB2ENR_TIM16EN,
.bus = APB2,
.irqn = TIM1_UP_TIM16_IRQn,
.channel_numof = 1,
},
};
#define TIMER_0_ISR isr_tim2 /**< IRQ of timer at idx 0 */
#define TIMER_1_ISR isr_tim1_brk_tim15 /**< IRQ of timer at idx 1 */
#define TIMER_2_ISR isr_tim1_up_tim16 /**< IRQ of timer at idx 2 */
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CFG_TIMER_TIM2_TIM15_TIM16_H */
/** @} */

2
boards/nucleo-l432kc/include/periph_conf.h
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@ -30,7 +30,7 @@
#include "clk_conf.h"
#include "cfg_i2c1_pb6_pb7.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
#include "cfg_timer_tim2_tim15_tim16.h"
#ifdef __cplusplus
extern "C" {

11
cpu/sam0_common/periph/eth.c
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@ -159,7 +159,7 @@ static void _init_desc_buf(void)
GMAC->TBQB.reg = (uint32_t) tx_desc;
}
int sam0_read_phy(uint8_t phy, uint8_t addr)
unsigned sam0_read_phy(uint8_t phy, uint8_t addr)
{
GMAC->MAN.reg = GMAC_MAN_REGA(addr) | GMAC_MAN_PHYA(phy)
| GMAC_MAN_CLTTO | GMAC_MAN_WTN(0x2)
@ -353,9 +353,6 @@ int sam0_eth_init(void)
memset(rx_desc, 0, sizeof(rx_desc));
memset(tx_desc, 0, sizeof(tx_desc));
/* Enable PHY */
gpio_set(sam_gmac_config[0].rst_pin);
/* Initialize buffers descriptor */
_init_desc_buf();
/* Disable RX and TX */
@ -373,9 +370,9 @@ int sam0_eth_init(void)
/* Set TxBase-100-FD by default */
/* TODO: implement auto negotiation */
GMAC->NCFGR.reg |= (GMAC_NCFGR_SPD | GMAC_NCFGR_FD | GMAC_NCFGR_MTIHEN |
GMAC_NCFGR_RXCOEN | GMAC_NCFGR_MAXFS | GMAC_NCFGR_CAF |
GMAC_NCFGR_LFERD | GMAC_NCFGR_RFCS | GMAC_NCFGR_CLK(3));
GMAC->NCFGR.reg = GMAC_NCFGR_SPD | GMAC_NCFGR_FD | GMAC_NCFGR_MTIHEN
| GMAC_NCFGR_RXCOEN | GMAC_NCFGR_MAXFS | GMAC_NCFGR_CAF
| GMAC_NCFGR_LFERD | GMAC_NCFGR_RFCS | GMAC_NCFGR_CLK(3);
/* Enable all multicast addresses */
GMAC->HRB.reg = 0xffffffff;

4
cpu/stm32/include/periph/cpu_timer.h
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@ -30,7 +30,7 @@ extern "C" {
#endif
/**
* @brief All STM timers have 4 capture-compare channels
* @brief All STM timers have at most 4 capture-compare channels
*/
#define TIMER_CHANNEL_NUMOF (4U)
@ -53,6 +53,8 @@ typedef struct {
uint32_t rcc_mask; /**< corresponding bit in the RCC register */
uint8_t bus; /**< APBx bus the timer is clock from */
uint8_t irqn; /**< global IRQ channel */
uint8_t channel_numof; /**< number of channels, 0 is alias for
@ref TIMER_CHANNEL_NUMOF */
} timer_conf_t;
#ifdef __cplusplus

23
cpu/stm32/periph/timer.c
View File

@ -36,6 +36,21 @@ static inline TIM_TypeDef *dev(tim_t tim)
return timer_config[tim].dev;
}
/**
* @brief Get the number of channels of the timer device
*/
static unsigned channel_numof(tim_t tim)
{
if (timer_config[tim].channel_numof) {
return timer_config[tim].channel_numof;
}
/* backwards compatibility with older periph_conf.h files when all STM32
* had exactly 4 channels */
return TIMER_CHANNEL_NUMOF;
}
#ifdef MODULE_PERIPH_TIMER_PERIODIC
/**
@ -121,7 +136,7 @@ int timer_init(tim_t tim, uint32_t freq, timer_cb_t cb, void *arg)
int timer_set_absolute(tim_t tim, int channel, unsigned int value)
{
if (channel >= (int)TIMER_CHANNEL_NUMOF) {
if ((unsigned)channel >= channel_numof(tim)) {
return -1;
}
@ -150,7 +165,7 @@ int timer_set(tim_t tim, int channel, unsigned int timeout)
{
unsigned value = (dev(tim)->CNT + timeout) & timer_config[tim].max;
if (channel >= (int)TIMER_CHANNEL_NUMOF) {
if ((unsigned)channel >= channel_numof(tim)) {
return -1;
}
@ -188,7 +203,7 @@ int timer_set(tim_t tim, int channel, unsigned int timeout)
#ifdef MODULE_PERIPH_TIMER_PERIODIC
int timer_set_periodic(tim_t tim, int channel, unsigned int value, uint8_t flags)
{
if (channel >= (int)TIMER_CHANNEL_NUMOF) {
if ((unsigned)channel >= channel_numof(tim)) {
return -1;
}
@ -227,7 +242,7 @@ int timer_set_periodic(tim_t tim, int channel, unsigned int value, uint8_t flags
int timer_clear(tim_t tim, int channel)
{
if (channel >= (int)TIMER_CHANNEL_NUMOF) {
if ((unsigned)channel >= channel_numof(tim)) {
return -1;
}