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Merge pull request #3742 from haukepetersen/add_msp430_periph_uart

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cpu/msp430: added periph UART driver
This commit is contained in:
Hauke Petersen 2015-09-03 13:30:37 +02:00
commit eb49be3b8b
27 changed files with 945 additions and 595 deletions
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12
boards/chronos/include/board.h
View File

@ -47,6 +47,18 @@ extern "C" {
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
*
* This defines are for compatibility with the CPU implementation but they are
* not used for this board (as it has no UART interface accessible...)
* @{
*/
#define STDIO (0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
#define MSP430_INITIAL_CPU_SPEED 7372800uL
#define F_CPU MSP430_INITIAL_CPU_SPEED
#define F_RC_OSCILLATOR 32768

31
boards/chronos/include/periph_conf.h
View File

@ -25,6 +25,16 @@
extern "C" {
#endif
/**
* @brief Clock configuration
*
* @todo Move all clock configuration code here from the board.h
*/
#define CLOCK_CORECLOCK (12000000U)
#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
/** @} */
/**
* @brief Timer configuration
* @{
@ -35,6 +45,27 @@ extern "C" {
#define TIMER_ISR_CCX (TIMER0_A1_VECTOR)
/** @} */
/**
* @brief UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN (1U)
#define UART_DEV (USART_1)
#define UART_IE (SFR->IE2)
#define UART_IF (SFR->IFG2)
#define UART_IE_RX_BIT (1 << 4)
#define UART_IE_TX_BIT (1 << 5)
#define UART_ME (SFR->ME2)
#define UART_ME_BITS (0x30)
#define UART_PORT (PORT_3)
#define UART_RX_PIN (1 << 6)
#define UART_TX_PIN (1 << 7)
#define UART_RX_ISR (USART1RX_VECTOR)
#define UART_TX_ISR (USART1TX_VECTOR)
/** @} */
/**
* @brief Real Time Clock configuration
*/

57
boards/msb-430-common/board_init.c
View File

@ -23,6 +23,8 @@
#include "cpu.h"
#include "irq.h"
#include "board.h"
#include "msp430_stdio.h"
#include "periph_conf.h"
#include "kernel_internal.h"
#include "msp430.h"
#include "debug.h"
@ -31,35 +33,6 @@ static volatile uint32_t __msp430_cpu_speed = MSP430_INITIAL_CPU_SPEED;
void msp430_init_dco(void);
/*---------------------------------------------------------------------------*/
static uint8_t calc_umctl(uint16_t br)
{
/* from TI slaa049 */
register uint8_t CMOD = 256 * br - 256 * (br + 1) / 2;
register uint8_t c = 0;
register int i = 0;
register uint8_t a = CMOD;
a <<= 1;
do {
if (a & 0x80) { /* Overflow to integer? */
a = a - 128 + CMOD; /* Yes, subtract 1.000000 */
c |= 0x80;
}
else {
a += CMOD; /* No, add fraction */
}
if (i == 7) {
return c;
}
i++;
c >>= 1;
}
while (1);
}
static void msb_ports_init(void)
{
/* Port 1: Free port, for energy saving all outputs are set to zero. */
@ -79,9 +52,9 @@ static void msb_ports_init(void)
/* 0 - P2.6 [IN ] - SDC Protect */
/* 0 - P2.7 [IN ] - SDC Detect */
P3SEL = 0xC0; /* Port3 Pins 6 & 7 for USART */
P3OUT = 0x49; /* Port3 Output register: 01001001: 0x49 */
P3DIR = 0xAB; /* Port3 Direction: 10101011: 0xAB */
P3SEL = 0x00; /* Port3 Pins 6 & 7 for USART */
P3OUT = 0x00; /* Port3 Output register: 01001001: 0x49 */
P3DIR = 0xFF; /* Port3 Direction: 10101011: 0xAB */
/* 1 - P3.0 */
/* 1 - P3.1 */
/* 0 - P3.2 */
@ -134,21 +107,6 @@ void msp430_set_cpu_speed(uint32_t speed)
disableIRQ();
__msp430_cpu_speed = speed;
msp430_init_dco();
uint16_t br;
UCTL1 = SWRST | CHAR; /* 8-bit character */
UTCTL1 |= SSEL1 | URXSE; /* UCLK = MCLK */
/* activate */
U1ME |= UTXE1 | URXE1; /* Enable USART1 TXD/RXD */
br = (uint16_t)(__msp430_cpu_speed / 115200uL);
UBR01 = br; /* set baudrate */
UBR11 = br >> 8;
UMCTL1 = calc_umctl(br); /* set modulation */
ME2 |= (UTXE1 | URXE1);
UCTL1 &= ~SWRST;
IE2 |= URXIE1;
//clock_init();
enableIRQ();
}
@ -244,5 +202,8 @@ void board_init(void)
LED_RED_ON;
msp430_set_cpu_speed(7372800uL);
msp430_set_cpu_speed(CLOCK_CORECLOCK);
/* finally initialize the STDIO */
msp430_stdio_init();
}

85
boards/msb-430-common/uart1.c
View File

@ -1,85 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards
* @{
*/
/**
* @file
* @brief msb-430 common putchar implementation
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Kaspar Schleiser <kaspar@schleiser.de>
*/
#include <stdio.h>
#include "board.h"
#include "kernel.h"
#include "board_uart0.h"
#define UART1_TX TXBUF1
#define UART1_WAIT_TXDONE() while( (UTCTL1 & TXEPT) == 0 ) { _NOP(); }
int getchar(void)
{
#ifdef MODULE_UART0
return uart0_readc();
#else
return U1RXBUF;
#endif
}
int putchar(int c)
{
UART1_TX = c;
UART1_WAIT_TXDONE();
if (c == 10) {
UART1_WAIT_TXDONE();
}
return c;
}
void usart0irq(void);
/**
* \brief the interrupt function
*/
void __attribute__((interrupt(USART1RX_VECTOR))) usart0irq(void)
{
U1TCTL &= ~URXSE; /* Clear the URXS signal */
U1TCTL |= URXSE; /* Re-enable URXS - needed here?*/
/* Check status register for receive errors. */
if(U1RCTL & RXERR) {
if (U1RCTL & FE) {
puts("rx framing error");
}
if (U1RCTL & OE) {
puts("rx overrun error");
}
if (U1RCTL & PE) {
puts("rx parity error");
}
if (U1RCTL & BRK) {
puts("rx break error");
}
/* Clear error flags by forcing a dummy read. */
volatile int c = U1RXBUF;
(void) c;
}
#ifdef MODULE_UART0
else if (uart0_handler_pid != KERNEL_PID_UNDEF) {
volatile int c = U1RXBUF;
uart0_handle_incoming(c);
uart0_notify_thread();
}
#endif
}

9
boards/msb-430/include/board.h
View File

@ -52,6 +52,15 @@ extern "C" {
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{
*/
#define STDIO (0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/* MSB430 core */
#define MSP430_INITIAL_CPU_SPEED 2457600uL
#define F_CPU MSP430_INITIAL_CPU_SPEED

31
boards/msb-430/include/periph_conf.h
View File

@ -25,6 +25,16 @@
extern "C" {
#endif
/**
* @brief Clock configuration
*
* @todo Move all clock configuration code here from the board.h
*/
#define CLOCK_CORECLOCK (7372800U)
#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
/** @} */
/**
* @brief Timer configuration
* @{
@ -35,6 +45,27 @@ extern "C" {
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
/**
* @brief UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN (1U)
#define UART_DEV (USART_1)
#define UART_IE (SFR->IE2)
#define UART_IF (SFR->IFG2)
#define UART_IE_RX_BIT (1 << 4)
#define UART_IE_TX_BIT (1 << 5)
#define UART_ME (SFR->ME2)
#define UART_ME_BITS (0x30)
#define UART_PORT (PORT_3)
#define UART_RX_PIN (1 << 6)
#define UART_TX_PIN (1 << 7)
#define UART_RX_ISR (USART1RX_VECTOR)
#define UART_TX_ISR (USART1TX_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif

9
boards/msb-430h/include/board.h
View File

@ -46,6 +46,15 @@ extern "C" {
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{
*/
#define STDIO (0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
//MSB430 core
#define MSP430_INITIAL_CPU_SPEED 7372800uL
#define F_CPU MSP430_INITIAL_CPU_SPEED

31
boards/msb-430h/include/periph_conf.h
View File

@ -25,6 +25,16 @@
extern "C" {
#endif
/**
* @brief Clock configuration
*
* @todo Move all clock configuration code here from the board.h
*/
#define CLOCK_CORECLOCK (7372800U)
#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
/** @} */
/**
* @brief Timer configuration
* @{
@ -35,6 +45,27 @@ extern "C" {
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
/**
* @brief UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN (1U)
#define UART_DEV (USART_1)
#define UART_IE (SFR->IE2)
#define UART_IF (SFR->IFG2)
#define UART_IE_RX_BIT (1 << 4)
#define UART_IE_TX_BIT (1 << 5)
#define UART_ME (SFR->ME2)
#define UART_ME_BITS (0x30)
#define UART_PORT (PORT_3)
#define UART_RX_PIN (1 << 6)
#define UART_TX_PIN (1 << 7)
#define UART_RX_ISR (USART1RX_VECTOR)
#define UART_TX_ISR (USART1TX_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif

10
boards/telosb/board.c
View File

@ -9,6 +9,7 @@
#include "cpu.h"
#include "board.h"
#include "msp430_stdio.h"
void uart_init(void);
@ -25,9 +26,9 @@ static void telosb_ports_init(void)
P2DIR = 0xFF; /* Port2 Direction: 11111111 = 0xFF */
/* Port 3: UART and SPI */
P3SEL = 0xCE; /* Port3 Select: 11001110 = 0xCE */
P3SEL = 0x0E; /* Port3 Select: 11001110 = 0xCE */
P3OUT = 0x00; /* Port3 Output: 00000000 = 0x00 */
P3DIR = 0x4E; /* Port3 Direction: 01001110 = 0x4E */
P3DIR = 0xFE; /* Port3 Direction: 01001110 = 0x4E */
/* Port 4: CS */
P4SEL = 0x02; /* Port4 Select: 00000010 = 0x02 */
@ -119,11 +120,10 @@ void board_init(void)
WDTCTL = WDTPW + WDTHOLD;
telosb_ports_init();
msp430_init_dco();
/* initialize bsp modules */
uart_init();
/* initialize the STDIO */
msp430_stdio_init();
/* enable interrupts */
__bis_SR_register(GIE);

9
boards/telosb/include/board.h
View File

@ -52,6 +52,15 @@ extern "C" {
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{
*/
#define STDIO (0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/* TelosB core */
#define MSP430_INITIAL_CPU_SPEED 2457600uL
#define F_CPU MSP430_INITIAL_CPU_SPEED

31
boards/telosb/include/periph_conf.h
View File

@ -25,6 +25,16 @@
extern "C" {
#endif
/**
* @brief Clock configuration
*
* @todo Move all clock configuration code here from the board.h
*/
#define CLOCK_CORECLOCK (2457600U)
#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
/** @} */
/**
* @brief Timer configuration
* @{
@ -35,6 +45,27 @@ extern "C" {
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
/**
* @brief UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN (1U)
#define UART_DEV (USART_1)
#define UART_IE (SFR->IE2)
#define UART_IF (SFR->IFG2)
#define UART_IE_RX_BIT (1 << 4)
#define UART_IE_TX_BIT (1 << 5)
#define UART_ME (SFR->ME2)
#define UART_ME_BITS (0x30)
#define UART_PORT (PORT_3)
#define UART_RX_PIN (1 << 6)
#define UART_TX_PIN (1 << 7)
#define UART_RX_ISR (USART1RX_VECTOR)
#define UART_TX_ISR (USART1TX_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif

126
boards/telosb/uart.c
View File

@ -1,126 +0,0 @@
/*
* uart.c - Implementation for the TelosB UART
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <stdio.h>
#include <stdint.h>
#include "cpu.h"
#include "board.h"
#include "kernel.h"
#include "board_uart0.h"
#define UART1_TX U1TXBUF
#define UART1_WAIT_TXDONE() while ( (U1TCTL & TXEPT) == 0 ) { _NOP(); }
#define BAUDRATE (115200ul)
static uint8_t calc_umctl(uint16_t br)
{
/* from TI slaa049 */
register uint8_t CMOD = 256 * br - 256 * (br + 1) / 2;
register uint8_t c = 0;
register int i = 0;
register uint8_t a = CMOD;
a <<= 1;
do {
if (a & 0x80) { /* Overflow to integer? */
a = a - 128 + CMOD; /* Yes, subtract 1.000000 */
c |= 0x80;
}
else {
a += CMOD; /* No, add fraction */
}
if (i == 7) {
return c;
}
i++;
c >>= 1;
}
while (1);
}
void uart_init(void)
{
UCTL1 = SWRST; /* hold UART1 module in reset */
UCTL1 |= CHAR; /* 8-bit character */
/* 115200 baud, clocked from 4.8MHz SMCLK */
UTCTL1 |= SSEL1; /* UCLK = SCLK */
UBR01 = F_CPU / BAUDRATE;
UBR11 = (F_CPU / BAUDRATE) >> 8;
UMCTL1 = calc_umctl(F_CPU / BAUDRATE); /* set modulation */
ME2 |= UTXE1 + URXE1; /* enable UART1 TX/RX */
UCTL1 &= ~SWRST; /* clear UART1 reset bit */
IE2 |= URXIE1; /* enable rx interrupt */
IFG1 &= ~UTXIFG1;
}
int putchar(int c)
{
UART1_TX = c;
UART1_WAIT_TXDONE();
return c;
}
int getchar(void)
{
#ifdef MODULE_UART0
return uart0_readc();
#else
return U1RXBUF;
#endif
}
uint8_t uart_readByte(void)
{
return U1RXBUF;
}
void usart1irq(void);
/**
* \brief the interrupt function
*/
void __attribute__((interrupt(USART1RX_VECTOR))) usart1irq(void)
{
/* Check status register for receive errors. */
if (U1RCTL & RXERR) {
if (U1RCTL & FE) {
puts("rx framing error");
}
if (U1RCTL & OE) {
puts("rx overrun error");
}
if (U1RCTL & PE) {
puts("rx parity error");
}
if (U1RCTL & BRK) {
puts("rx break error");
}
/* Clear error flags by forcing a dummy read. */
volatile int c = U1RXBUF;
(void) c;
}
#ifdef MODULE_UART0
else if (uart0_handler_pid != KERNEL_PID_UNDEF) {
volatile int c = U1RXBUF;
uart0_handle_incoming(c);
uart0_notify_thread();
}
#endif
}

46
boards/wsn430-common/board_init.c
View File

@ -13,6 +13,7 @@
#include "kernel_internal.h"
#include "msp430.h"
#include "debug.h"
#include "msp430_stdio.h"
volatile static uint32_t __msp430_cpu_speed = MSP430_INITIAL_CPU_SPEED;
@ -25,30 +26,6 @@ typedef enum {
MCLK_8MHZ_SCLK_8MHZ = 8000000uL
}speed_t;
/*---------------------------------------------------------------------------*/
static uint8_t calc_umctl(uint16_t br) {
// from TI slaa049
register uint8_t CMOD = 256 * br - 256 * (br + 1) / 2;
register uint8_t c = 0;
register int i = 0;
register uint8_t a = CMOD;
a <<= 1;
do {
if( a & 0x80 ) { // Overflow to integer?
a = a - 128 + CMOD; // Yes, subtract 1.000000
c |= 0x80;
}
else {
a += CMOD; // No, add fraction
}
if( i == 7 ) {
return c;
}
i++;
c >>= 1;
} while(1);
}
static void msb_ports_init(void)
{
// Port 1: GDO, Flash, BSL TX
@ -90,24 +67,6 @@ void msp430_set_cpu_speed(uint32_t speed)
disableIRQ();
__msp430_cpu_speed = speed;
msp430_init_dco();
uint16_t br;
U0CTL = SWRST;
U0CTL = SWRST | CHAR; // 8-bit character
U0TCTL = SSEL1 | TXEPT; // UCLK = SCLK
U0RCTL = 0;
// activate
ME1 |= UTXE0 + URXE0; // Enable USART0 TXD/RXD
br = (uint16_t)((__msp430_cpu_speed & 0xFFFFF0) / 115200uL);
UBR00 = br; // set baudrate
UBR10 = br>>8;
UMCTL0 = calc_umctl(br); // set modulation
U0CTL &= ~SWRST;
//URCTL0 |= URXEIE; // allow chars to interrupt
IE1 |= URXIE0; // enable rx interrupt
IFG1 &= ~UTXIFG0;
enableIRQ();
}
@ -152,4 +111,7 @@ void board_init(void)
LED_RED_ON;
msp430_set_cpu_speed(MCLK_8MHZ_SCLK_8MHZ);
/* initialize the STDIO */
msp430_stdio_init();
}

31
boards/wsn430-common/include/periph_conf.h
View File

@ -25,6 +25,16 @@
extern "C" {
#endif
/**
* @brief Clock configuration
*
* @todo Move all clock configuration code here from the board.h
*/
#define CLOCK_CORECLOCK (8000000U)
#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
/** @} */
/**
* @brief Timer configuration
* @{
@ -35,6 +45,27 @@ extern "C" {
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
/**
* @brief UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN (1U)
#define UART_DEV (USART_0)
#define UART_IE (SFR->IE1)
#define UART_IF (SFR->IFG1)
#define UART_IE_RX_BIT (1 << 6)
#define UART_IE_TX_BIT (1 << 7)
#define UART_ME (SFR->ME1)
#define UART_ME_BITS (0xc0)
#define UART_PORT (PORT_3)
#define UART_RX_PIN (1 << 4)
#define UART_TX_PIN (1 << 5)
#define UART_RX_ISR (USART0RX_VECTOR)
#define UART_TX_ISR (USART0TX_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif

73
boards/wsn430-common/wsn430-uart0.c
View File

@ -1,73 +0,0 @@
/*
* uart0.c - Implementation of the uart.
* Copyright (C) 2013 Milan Babel <babel@inf.fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <stdio.h>
#include "board.h"
#define UART0_TX U0TXBUF
#define UART0_WAIT_TXDONE() while( (U0TCTL & TXEPT) == 0 ) { _NOP(); }
#include "kernel.h"
#include "board_uart0.h"
int putchar(int c)
{
UART0_TX = c;
UART0_WAIT_TXDONE();
if (c == 10) {
UART0_TX = 13;
UART0_WAIT_TXDONE();
}
return c;
}
int getchar(void)
{
#ifdef MODULE_UART0
return uart0_readc();
#else
return U0RXBUF;
#endif
}
void usart0irq(void);
/**
* \brief the interrupt function
*/
void __attribute__((interrupt(USART0RX_VECTOR))) usart0irq(void) {
volatile int dummy = 0;
/* Check status register for receive errors. */
if(U0RCTL & RXERR) {
if (U0RCTL & FE) {
puts("rx framing error");
}
if (U0RCTL & OE) {
puts("rx overrun error");
}
if (U0RCTL & PE) {
puts("rx parity error");
}
if (U0RCTL & BRK) {
puts("rx break error");
}
/* Clear error flags by forcing a dummy read. */
dummy = U0RXBUF;
(void)dummy;
}
#ifdef MODULE_UART0
else if (uart0_handler_pid != KERNEL_PID_UNDEF) {
dummy = U0RXBUF;
uart0_handle_incoming(dummy);
uart0_notify_thread();
}
#endif
}

9
boards/wsn430-v1_3b/include/board.h
View File

@ -54,6 +54,15 @@ extern "C" {
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{
*/
#define STDIO (0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
//MSB430 core
#define MSP430_INITIAL_CPU_SPEED 800000uL
#define F_CPU MSP430_INITIAL_CPU_SPEED

17
boards/wsn430-v1_4/include/board.h
View File

@ -34,6 +34,11 @@
extern "C" {
#endif
/* for correct inclusion of <msp430.h> */
#ifndef __MSP430F1611__
#define __MSP430F1611__
#endif
/**
* @brief Xtimer configuration
* @{
@ -49,10 +54,14 @@ extern "C" {
*/
#define HW_TIMER (0)
/* for correct inclusion of <msp430.h> */
#ifndef __MSP430F1611__
#define __MSP430F1611__
#endif
/**
* @brief Standard input/output device configuration
* @{
*/
#define STDIO (0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/* MSB430 core */
#define MSP430_INITIAL_CPU_SPEED 800000uL

8
boards/z1/board.c
View File

@ -24,9 +24,7 @@
#include "cpu.h"
#include "board.h"
void uart_init(void);
#include "msp430_stdio.h"
static void z1_ports_init(void)
{
@ -217,8 +215,8 @@ void board_init(void)
/* initializes DCO */
msp430_init_dco();
/* initialize UART/USB module */
uart_init();
/* initialize STDIO */
msp430_stdio_init();
/* enable interrupts */
__bis_SR_register(GIE);

18
boards/z1/include/board.h
View File

@ -54,6 +54,24 @@ extern "C" {
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{
*/
#define STDIO (0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/**
* @brief Standard input/output device configuration
* @{
*/
#define STDIO (0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/* MSP430 core */
#define MSP430_INITIAL_CPU_SPEED 8000000uL
#ifndef F_CPU

31
boards/z1/include/periph_conf.h
View File

@ -25,6 +25,16 @@
extern "C" {
#endif
/**
* @brief Clock configuration
*
* @todo Move all clock configuration code here from the board.h
*/
#define CLOCK_CORECLOCK (8000000U)
#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
/** @} */
/**
* @brief Timer configuration
* @{
@ -35,6 +45,27 @@ extern "C" {
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
/**
* @brief UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN (1U)
#define UART_USE_USIC
#define UART_DEV (USCI_0)
#define UART_IE (SFR->IE2)
#define UART_IF (SFR->IFG2)
#define UART_IE_RX_BIT (1 << 0)
#define UART_IE_TX_BIT (1 << 1)
#define UART_RX_PORT ((msp_port_isr_t *)PORT_2)
#define UART_RX_PIN (1 << 2)
#define UART_TX_PORT ((msp_port_isr_t *)PORT_1)
#define UART_TX_PIN (1 << 1)
#define UART_RX_ISR (USCIAB0RX_VECTOR)
#define UART_TX_ISR (USCIAB0TX_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif

137
boards/z1/uart.c
View File

@ -1,137 +0,0 @@
/*
* uart.c - Implementation for the Zolertia Z1 UART
* Copyright (C) 2014 INRIA
*
* Author : Kevin Roussel <kevin.roussel@inria.fr>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_z1
* @{
*
* @file
* @brief Board specific UART/USB driver HAL for the Zolertia Z1
*
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
*
* @}
*/
#include <stdio.h>
#include <stdint.h>
#include "cpu.h"
#include "board.h"
#include "kernel.h"
#include "irq.h"
#include "board_uart0.h"
#define BAUDRATE (115200ul)
#define BAUD_RATE_MAJOR (int)(MSP430_INITIAL_CPU_SPEED / BAUDRATE)
#define BAUD_RATE_MINOR (int)(((MSP430_INITIAL_CPU_SPEED / BAUDRATE) - BAUD_RATE_MAJOR) * 8)
void uart_init(void)
{
/*
* NOTE : MCU pin (GPIO port) initialisation is done
* in board.c, function z1_ports_init().
*/
UCA0CTL1 = UCSWRST; /* hold UART module in reset state
while we configure it */
UCA0CTL1 |= UCSSEL_2; /* source UART's BRCLK from 8 MHz SMCLK */
UCA0MCTL = UCBRS1 + UCBRS0; /* low-frequency baud rate generation,
modulation type 4 */
/* 115200 baud, divided from 8 MHz == 69 */
UCA0BR0 = BAUD_RATE_MAJOR;
UCA0BR1 = BAUD_RATE_MINOR;
/* remaining registers : set to default */
UCA0CTL0 = 0x00; /* put in asynchronous (== UART) mode, LSB first */
UCA0STAT = 0x00; /* reset status flags */
/* clear UART-related interrupt flags */
IFG2 &= ~(UCA0RXIFG | UCA0TXIFG);
/* configuration done, release reset bit => start UART */
UCA0CTL1 &= ~UCSWRST;
/* enable UART0 RX interrupt, disable UART0 TX interrupt */
IE2 |= UCA0RXIE;
IE2 &= ~UCA0TXIE;
}
int putchar(int c)
{
unsigned sr = disableIRQ();
/* the LF endline character needs to be "doubled" into CR+LF */
if (c == '\n') {
putchar('\r');
}
/* wait for a previous transmission to end */
while ((IFG2 & UCA0TXIFG) == 0) {
__asm__("nop");
}
/* load TX byte buffer */
UCA0TXBUF = (uint8_t) c;
restoreIRQ(sr);
return c;
}
int getchar(void)
{
#ifdef MODULE_UART0
return uart0_readc();
#else
return UCA0RXBUF;
#endif
}
uint8_t uart_readByte(void)
{
return UCA0RXBUF;
}
/**
* \brief the interrupt handler for UART reception
*/
void __attribute__((interrupt(USCIAB0RX_VECTOR))) usart1irq(void)
{
volatile int c;
/* Check status register for receive errors. */
if (UCA0STAT & UCRXERR) {
if (UCA0STAT & UCFE) {
puts("UART RX framing error");
}
if (UCA0STAT & UCOE) {
puts("UART RX overrun error");
}
if (UCA0STAT & UCPE) {
puts("UART RX parity error");
}
if (UCA0STAT & UCBRK) {
puts("UART RX break condition -> error");
}
/* Clear error flags by forcing a dummy read. */
c = UCA0RXBUF;
(void)c;
}
#ifdef MODULE_UART0
else if (uart0_handler_pid != KERNEL_PID_UNDEF) {
/* All went well -> let's signal the reception to adequate callbacks */
c = UCA0RXBUF;
uart0_handle_incoming(c);
uart0_notify_thread();
}
#endif
}

4
cpu/msp430fxyz/Makefile.include
View File

@ -2,4 +2,6 @@ INCLUDES += -I$(RIOTCPU)/msp430fxyz/include/
include $(RIOTCPU)/msp430-common/Makefile.include
export USEMODULE += periph hwtimer_compat
USEMODULE += periph
USEMODULE += hwtimer_compat
export USEMODULE

282
cpu/msp430fxyz/include/msp430_regs.h
View File

@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_msp430-common
* @ingroup cpu_msp430fxyz
* @{
*
* @file
@ -41,12 +41,12 @@ extern "C" {
* @brief Special function registers
*/
typedef struct {
REG8 IE1; /**< interrupt enable 1 */
REG8 IE2; /**< interrupt enable 2 */
REG8 IFG1; /**< interrupt flag 1 */
REG8 IFG2; /**< interrupt flag 2 */
REG8 ME1; /**< module enable 1 */
REG8 ME2; /**< module enable 2 */
REG8 IE1; /**< interrupt enable 1 */
REG8 IE2; /**< interrupt enable 2 */
REG8 IFG1; /**< interrupt flag 1 */
REG8 IFG2; /**< interrupt flag 2 */
REG8 ME1; /**< module enable 1 */
REG8 ME2; /**< module enable 2 */
} msp_sfr_t;
/**
@ -81,26 +81,35 @@ typedef struct {
REG8 RCTL; /**< receive control */
REG8 MCTL; /**< modulation control */
REG8 BR0; /**< baud rate control 0 */
REG8 RR1; /**< baud rate control 1 */
REG8 BR1; /**< baud rate control 1 */
REG8 RXBUF; /**< receive buffer */
REG8 TXBUF; /**< transmit buffer */
} msp_usart_t;
/**
* @brief System clock module configuration registers
* @brief USCI universal serial control interface registers
*/
typedef struct {
REG8 DCOCTL; /**< digital controlled oscillator control */
REG8 BCSCTL1; /**< basic clock system control 1 */
REG8 BCSCTL2; /**< basic clock system control 2 */
} msp_clk_t;
/**
* @brief Watchdog configuration registers
*/
typedef struct {
REG16 TCTL; /**< watchdog time control */
} msp_wd_t;
REG8 ABCTL; /**< auto baud rate control */
REG8 IRTCTL; /**< IrDA transmit control */
REG8 IRRCTL; /**< IrDA receive control */
REG8 ACTL0; /**< A control 0 */
REG8 ACTL1; /**< A control 1 */
REG8 ABR0; /**< A baud rate control 0 */
REG8 ABR1; /**< A baud rate control 1 */
REG8 AMCTL; /**< A modulation control */
REG8 ASTAT; /**< A status */
REG8 ARXBUF; /**< A receive buffer */
REG8 ATXBUF; /**< A transmit buffer */
REG8 BCTL0; /**< B control 0 */
REG8 BCTL1; /**< B control 1 */
REG8 BBR0; /**< B baud rate 0 */
REG8 BBR1; /**< B baud rate 1 */
REG8 BI2CIE; /**< I2C interrupt enable */
REG8 BSTAT; /**< B status */
REG8 BRXBUF; /**< B receive buffer */
REG8 BTXBUF; /**< B transmit buffer */
} msp_usci_t;
/**
* @brief Timer interrupt status registers
@ -121,53 +130,206 @@ typedef struct {
REG16 CCR[7]; /**< capture compare channel values */
} msp_timer_t;
/**
* @brief SFR interrupt enable 1 register bitmap
* @{
*/
#define SFR_IE1_OFIE (0x02)
#define SFR_IE1_URXIE0 (0x40)
#define SFR_IE1_UTXIE0 (0x80)
/** @} */
/**
* @brief SFR interrupt enable 2 register bitmap
* @{
*/
#define SFR_IE2_UCA0RXIE (0x01)
#define SFR_IE2_UCA0TXIE (0x02)
#define SFR_IE2_URXIE2 (0x10)
#define SFR_IE2_UTXIE2 (0x20)
/** @} */
/**
* @brief SFR interrupt flag 1 register bitmap
* @{
*/
#define SFR_IFG1_OFIFG (0x02)
#define SFR_IFG1_URXIFG0 (0x40)
#define SFR_IFG1_UTXIFG0 (0x80)
/** @} */
/**
* @brief SFR interrupt flag 2 register bitmap
* @{
*/
#define SFR_IFG2_UCA0RXIFG (0x01)
#define SFR_IFG2_UCA0TXIFG (0x02)
#define SFR_IFG2_URXIFG1 (0x10)
#define SFR_IFG2_UTXIFG1 (0x20)
/** @} */
/**
* @brief SFR module enable register 1
* @{
*/
#define SFR_ME1_USPIE0 (0x40)
/** @} */
/**
* @brief SFR module enable register 2
* @{
*/
#define SFR_ME2_USPIE1 (0x10)
/** @} */
/**
* @brief USART control register bitmap
* @{
*/
#define USART_CTL_SWRST (0x01)
#define USART_CTL_MM (0x02)
#define USART_CTL_SYNC (0x04)
#define USART_CTL_LISTEN (0x08)
#define USART_CTL_CHAR (0x10)
#define USART_CTL_SPB (0x20)
#define USART_CTL_PEV (0x40)
#define USART_CTL_PENA (0x80)
/** @} */
/**
* @brief USART transmit control register bitmap
* @{
*/
#define USART_TCTL_TXEPT (0x01)
#define USART_TCTL_TXWAKE (0x04)
#define USART_TCTL_URXSE (0x08)
#define USART_TCTL_SSEL_MASK (0x30)
#define USART_TCTL_SSEL_UCLKI (0x00)
#define USART_TCTL_SSEL_ACLK (0x10)
#define USART_TCTL_SSEL_SMCLK (0x20)
#define USART_TCTL_CKPL (0x40)
/** @} */
/**
* @brief USART receive control register bitmap
* @{
*/
#define USART_RCTL_RXERR (0x01)
#define USART_RCTL_RXWAKE (0x02)
#define USART_RCTL_URXWIE (0x04)
#define USART_RCTL_URXEIE (0x08)
#define USART_RCTL_BRK (0x10)
#define USART_RCTL_OE (0x20)
#define USART_RCTL_PE (0x40)
#define USART_RCTL_FE (0x80)
/** @} */
/**
* @brief USCI control A register 0 bitmap
* @{
*/
#define USCI_ACTL0_UCSYNC (0x01)
#define USCI_ACTL0_MODE_MASK (0x06)
#define USCI_ACTL0_MODE_UART (0x00)
#define USCI_ACTL0_MODE_ILMM (0x02)
#define USCI_ACTL0_MODE_ABMM (0x04)
#define USCI_ACTL0_MODE_UART_ABR (0x06)
#define USCI_ACTL0_SPB (0x08)
#define USCI_ACTL0_7BIT (0x10)
#define USCI_ACTL0_MSB (0x20)
#define USCI_ACTL0_PAR (0x40)
#define USCI_ACTL0_PEN (0x80)
/** @} */
/**
* @brief USCI control A register 1 bitmap
* @{
*/
#define USCI_ACTL1_SWRST (0x01)
#define USCI_ACTL1_TXBRK (0x02)
#define USCI_ACTL1_TXADDR (0x04)
#define USCI_ACTL1_DORM (0x08)
#define USCI_ACTL1_BRKIE (0x10)
#define USCI_ACTL1_RXEIE (0x20)
#define USCI_ACTL1_SSEL_MASK (0xc0)
#define USCI_ACTL1_SSEL_UCLK (0x00)
#define USCI_ACTL1_SSEL_ACLK (0x40)
#define USCI_ACTL1_SSEL_SMCLK (0xc0)
/** @} */
/**
* @brief USCI modulation A control register
* @{
*/
#define USCI_AMCTL_OS16 (0x01)
#define USCI_AMCTL_BRS_MASK (0xe0)
#define USCI_AMCTL_BRS_SHIFT (1U)
#define USCI_AMCTL_BRF_MASK (0xf0)
#define USCI_AMCTL_BRF_SHIFT (4U)
/** @} */
/**
* @brief USCI status A register bitmap
* @{
*/
#define USCI_ASTAT_BUSY (0x01)
#define USCI_ASTAT_IDLE (0x02)
#define USCI_ASTAT_ADDR (0x02)
#define USCI_ASTAT_RXERR (0x04)
#define USCI_ASTAT_BRK (0x08)
#define USCI_ASTAT_PE (0x10)
#define USCI_ASTAT_OE (0x20)
#define USCI_ASTAT_FE (0x40)
#define USCI_ASTAT_LISTEN (0x80)
/** @} */
/**
* @brief Timer Control register bitmap
* @{
*/
#define CTL_IFG (0x0001)
#define CTL_IE (0x0002)
#define CTL_CLR (0x0004)
#define CTL_MC_MASK (0x0030)
#define CTL_MC_STOP (0x0000)
#define CTL_MC_UP (0x0010)
#define CTL_MC_CONT (0x0020)
#define CTL_MC_UPDOWN (0x0030)
#define CTL_ID_MASK (0x00c0)
#define CTL_ID_DIV1 (0x0000)
#define CTL_ID_DIV2 (0x0040)
#define CTL_ID_DIV4 (0x0080)
#define CTL_ID_DIV8 (0x00c0)
#define CTL_TASSEL_MASK (0x0300)
#define CTL_TASSEL_TCLK (0x0000)
#define CTL_TASSEL_ACLK (0x0100)
#define CTL_TASSEL_SMCLK (0x0200)
#define CTL_TASSEL_INV_TCLK (0x0300)
#define TIMER_CTL_IFG (0x0001)
#define TIMER_CTL_IE (0x0002)
#define TIMER_CTL_CLR (0x0004)
#define TIMER_CTL_MC_MASK (0x0030)
#define TIMER_CTL_MC_STOP (0x0000)
#define TIMER_CTL_MC_UP (0x0010)
#define TIMER_CTL_MC_CONT (0x0020)
#define TIMER_CTL_MC_UPDOWN (0x0030)
#define TIMER_CTL_ID_MASK (0x00c0)
#define TIMER_CTL_ID_DIV1 (0x0000)
#define TIMER_CTL_ID_DIV2 (0x0040)
#define TIMER_CTL_ID_DIV4 (0x0080)
#define TIMER_CTL_ID_DIV8 (0x00c0)
#define TIMER_CTL_TASSEL_MASK (0x0300)
#define TIMER_CTL_TASSEL_TCLK (0x0000)
#define TIMER_CTL_TASSEL_ACLK (0x0100)
#define TIMER_CTL_TASSEL_SMCLK (0x0200)
#define TIMER_CTL_TASSEL_INV_TCLK (0x0300)
/** @} */
/**
* @brief Timer Channel Control register bitmap
* @{
*/
#define CCTL_CCIFG (0x0001)
#define CCTL_COV (0x0002)
#define CCTL_OUT (0x0004)
#define CCTL_CCI (0x0008)
#define CCTL_CCIE (0x0010)
#define CCTL_OUTMOD_MASK (0x00e0)
#define CCTL_OUTMOD_OUTVAL (0x0000)
#define CCTL_OUTMOD_SET (0x0020)
#define CCTL_OUTMOD_TOG_RESET (0x0040)
#define CCTL_OUTMOD_SET_RESET (0x0060)
#define CCTL_OUTMOD_TOGGLE (0x0080)
#define CCTL_OUTMOD_RESET (0x00a0)
#define CCTL_OUTMOD_TOG_SET (0x00c0)
#define CCTL_OUTMOD_RESET_SET (0x00e0)
#define CCTL_CAP (0x0100)
#define CCTL_CLLD_MASK (0x0600)
#define CCTL_SCS (0x0800)
#define CCTL_CCIS_MASK (0x3000)
#define CCTL_CM_MASK (0xc000)
#define TIMER_CCTL_CCIFG (0x0001)
#define TIMER_CCTL_COV (0x0002)
#define TIMER_CCTL_OUT (0x0004)
#define TIMER_CCTL_CCI (0x0008)
#define TIMER_CCTL_CCIE (0x0010)
#define TIMER_CCTL_OUTMOD_MASK (0x00e0)
#define TIMER_CCTL_OUTMOD_OUTVAL (0x0000)
#define TIMER_CCTL_OUTMOD_SET (0x0020)
#define TIMER_CCTL_OUTMOD_TOG_RESET (0x0040)
#define TIMER_CCTL_OUTMOD_SET_RESET (0x0060)
#define TIMER_CCTL_OUTMOD_TOGGLE (0x0080)
#define TIMER_CCTL_OUTMOD_RESET (0x00a0)
#define TIMER_CCTL_OUTMOD_TOG_SET (0x00c0)
#define TIMER_CCTL_OUTMOD_RESET_SET (0x00e0)
#define TIMER_CCTL_CAP (0x0100)
#define TIMER_CCTL_CLLD_MASK (0x0600)
#define TIMER_CCTL_SCS (0x0800)
#define TIMER_CCTL_CCIS_MASK (0x3000)
#define TIMER_CCTL_CM_MASK (0xc000)
/** @} */
/**
@ -181,13 +343,15 @@ typedef struct {
#define PORT_4_BASE ((uint16_t)0x001c)
#define PORT_5_BASE ((uint16_t)0x0030)
#define PORT_6_BASE ((uint16_t)0x0034)
#define CLK_BASE ((uint16_t)0x0056)
#define CLK_BASE ((uint16_t)0x0053)
#define USART_0_BASE ((uint16_t)0x0070)
#define USART_1_BASE ((uint16_t)0x0078)
#define TIMER_IVEC_BASE ((uint16_t)0x011e)
#define TIMER_A_BASE ((uint16_t)0x0160)
#define TIMER_B_BASE ((uint16_t)0x0180)
#define WD_BASE ((uint16_t)0x0120)
#define USCI_0_BASE ((uint16_t)0x005d)
#define USCI_1_BASE ((uint16_t)0x00cd)
/** @} */
/**
@ -208,6 +372,8 @@ typedef struct {
#define TIMER_A ((msp_timer_t *)TIMER_A_BASE)
#define TIMER_B ((msp_timer_t *)TIMER_B_BASE)
#define WD ((msp_wd_t *)WD_BASE)
#define USCI_0 ((msp_usci_t *)USCI_0_BASE)
#define USCI_1 ((msp_usci_t *)USCI_1_BASE)
/** @} */
#ifdef __cplusplus

37
cpu/msp430fxyz/include/msp430_stdio.h Normal file
View File

@ -0,0 +1,37 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430fxyz
*
* @{
* @file
* @brief STDIO over UART for MSP430 platforms
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef MSP430_STDIO_H
#define MSP430_STDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize the STDIO data structured and the underlying UART driver
* as define in board.h
*/
void msp430_stdio_init(void);
#ifdef __cplusplus
}
#endif
#endif /* MSP430_STDIO_H */
/** @} */

86
cpu/msp430fxyz/msp430_stdio.c Normal file
View File

@ -0,0 +1,86 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430fxyz
* @{
*
* @file
* @brief Implementation of getchar and putchar for MSP430 CPUs
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "irq.h"
#include "mutex.h"
#include "board.h"
#include "ringbuffer.h"
#include "periph/uart.h"
#include <stdio.h>
static mutex_t rx_lock = MUTEX_INIT;
static ringbuffer_t rx_buf;
static char rx_buf_mem[STDIO_RX_BUFSIZE];
static inline int safe_read(void)
{
int res;
unsigned state = disableIRQ();
res = ringbuffer_get_one(&rx_buf);
restoreIRQ(state);
return res;
}
static void rx_cb(void *arg, char data)
{
(void)arg;
ringbuffer_add_one(&rx_buf, data);
/* this is a little dirty hack: it seems the MSP430 boards are too slow for
* processing data @ 115200 baud and calling mutex_unock() for each byte. By
* asserting, that the STDIO is used for the shell and we are only
* interested in completed lines anyway, we can reduce the overhead here by
* only waking the shell on newline chars */
if (data == '\n') {
mutex_unlock(&rx_lock);
}
}
void msp430_stdio_init(void)
{
mutex_lock(&rx_lock);
ringbuffer_init(&rx_buf, rx_buf_mem, STDIO_RX_BUFSIZE);
uart_init(STDIO, STDIO_BAUDRATE, rx_cb, NULL, 0);
}
/**
* @brief Get one character from STDIO - used by the libc
*/
int getchar(void)
{
int res = safe_read();
while (res == -1) {
mutex_lock(&rx_lock);
res = safe_read();
}
return res;
}
/**
* @brief Write one character to the STDIO UART interface - used by e.g.
* printf and puts
*/
int putchar(int c)
{
uart_write_blocking(STDIO, (char)c);
return 1;
}

22
cpu/msp430fxyz/periph/timer.c
View File

@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_msp430-common
* @ingroup cpu_msp430fxyz
* @{
*
* @file
@ -47,17 +47,17 @@ int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
}
/* reset the timer A configuration */
TIMER_DEV->CTL = CTL_CLR;
TIMER_DEV->CTL = TIMER_CTL_CLR;
/* save callback */
isr_cb = callback;
/* configure timer to use the SMCLK with prescaler of 8 */
TIMER_DEV->CTL = (CTL_TASSEL_SMCLK | CTL_ID_DIV8);
TIMER_DEV->CTL = (TIMER_CTL_TASSEL_SMCLK | TIMER_CTL_ID_DIV8);
/* configure CC channels */
for (int i = 0; i < TIMER_CHAN; i++) {
TIMER_DEV->CCTL[i] = 0;
}
/* start the timer in continuous mode */
TIMER_DEV->CTL |= CTL_MC_CONT;
TIMER_DEV->CTL |= TIMER_CTL_MC_CONT;
return 0;
}
@ -73,8 +73,8 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
return -1;
}
TIMER_DEV->CCR[channel] = value;
TIMER_DEV->CCTL[channel] &= ~(CCTL_CCIFG);
TIMER_DEV->CCTL[channel] |= (CCTL_CCIE);
TIMER_DEV->CCTL[channel] &= ~(TIMER_CCTL_CCIFG);
TIMER_DEV->CCTL[channel] |= (TIMER_CCTL_CCIE);
return 0;
}
@ -83,7 +83,7 @@ int timer_clear(tim_t dev, int channel)
if (dev != 0 || channel > TIMER_CHAN) {
return -1;
}
TIMER_DEV->CCTL[channel] &= ~(CCTL_CCIE);
TIMER_DEV->CCTL[channel] &= ~(TIMER_CCTL_CCIE);
return 0;
}
@ -94,12 +94,12 @@ unsigned int timer_read(tim_t dev)
void timer_start(tim_t dev)
{
TIMER_DEV->CTL |= CTL_MC_CONT;
TIMER_DEV->CTL |= TIMER_CTL_MC_CONT;
}
void timer_stop(tim_t dev)
{
TIMER_DEV->CTL &= ~(CTL_MC_MASK);
TIMER_DEV->CTL &= ~(TIMER_CTL_MC_MASK);
}
void timer_irq_enable(tim_t dev)
@ -128,7 +128,7 @@ ISR(TIMER_ISR_CC0, isr_timer_a_cc0)
{
__enter_isr();
TIMER_DEV->CCTL[0] &= ~(CCTL_CCIE);
TIMER_DEV->CCTL[0] &= ~(TIMER_CCTL_CCIE);
isr_cb(0);
__exit_isr();
@ -139,7 +139,7 @@ ISR(TIMER_ISR_CCX, isr_timer_a_ccx)
__enter_isr();
int chan = (int)(TIMER_IVEC->TAIV >> 1);
TIMER_DEV->CCTL[chan] &= ~(CCTL_CCIE);
TIMER_DEV->CCTL[chan] &= ~(TIMER_CCTL_CCIE);
isr_cb(chan);
__exit_isr();

298
cpu/msp430fxyz/periph/uart.c Normal file
View File

@ -0,0 +1,298 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430fxyz
* @{
*
* @file
* @brief Low-level UART driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph_cpu.h"
#include "periph_conf.h"
#include "periph/uart.h"
/**
* @brief Keep track of the interrupt context
* @{
*/
static uart_rx_cb_t ctx_rx_cb;
static uart_tx_cb_t ctx_tx_cb;
static void *ctx_isr_arg;
/** @} */
/* per default, we use the legacy MSP430 USART module for UART functionality */
#ifndef UART_USE_USIC
int uart_init(uart_t uart, uint32_t baudrate,
uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
{
if (uart_init_blocking(uart, baudrate) < 0) {
return -1;
}
/* save interrupt context */
ctx_rx_cb = rx_cb;
ctx_tx_cb = tx_cb;
ctx_isr_arg = arg;
/* reset interrupt flags and enable RX interrupt */
UART_IE &= ~(UART_IE_TX_BIT);
UART_IF &= ~(UART_IE_RX_BIT);
UART_IF |= (UART_IE_TX_BIT);
UART_IE |= (UART_IE_RX_BIT);
return 0;
}
int uart_init_blocking(uart_t uart, uint32_t baudrate)
{
if (uart != 0) {
return -1;
}
/* get the default UART for now -> TODO: enable for multiple devices */
msp_usart_t *dev = UART_DEV;
/* power off and reset device */
uart_poweroff(uart);
dev->CTL = USART_CTL_SWRST;
/* configure to 8N1 and using the SMCLK*/
dev->CTL |= USART_CTL_CHAR;
dev->TCTL = (USART_TCTL_TXEPT | USART_TCTL_URXSE | USART_TCTL_SSEL_SMCLK);
dev->RCTL = 0x00;
/* baudrate configuration */
uint16_t br = (uint16_t)(CLOCK_CMCLK / baudrate);
dev->BR0 = (uint8_t)br;
dev->BR1 = (uint8_t)(br >> 8);
/* TODO: calculate value for modulation register */
dev->MCTL = 0;
/* configure pins -> TODO: move into GPIO driver (once implemented) */
UART_PORT->SEL |= (UART_RX_PIN | UART_TX_PIN);
UART_PORT->OD |= UART_RX_PIN;
UART_PORT->OD &= ~(UART_TX_PIN);
UART_PORT->DIR |= UART_TX_PIN;
UART_PORT->DIR &= ~(UART_RX_PIN);
/* enable receiver and transmitter */
uart_poweron(uart);
/* and finally release the software reset bit */
dev->CTL &= ~(USART_CTL_SWRST);
return 0;
}
void uart_tx_begin(uart_t uart)
{
(void)uart;
UART_IE |= UART_IE_TX_BIT;
}
int uart_write(uart_t uart, char data)
{
(void)uart;
msp_usart_t *dev = UART_DEV;
dev->TXBUF = (uint8_t)data;
return 1;
}
int uart_write_blocking(uart_t uart, char data)
{
(void)uart;
msp_usart_t *dev = UART_DEV;
while (!(dev->TCTL & USART_TCTL_TXEPT));
dev->TXBUF = (uint8_t)data;
return 1;
}
int uart_read_blocking(uart_t uart, char *data)
{
(void)uart;
msp_usart_t *dev = UART_DEV;
while (!(UART_IF & UART_IE_RX_BIT));
*data = (char)dev->RXBUF;
return 1;
}
void uart_poweron(uart_t uart)
{
UART_ME |= UART_ME_BITS;
}
void uart_poweroff(uart_t uart)
{
UART_ME &= ~(UART_ME_BITS);
}
ISR(UART_RX_ISR, isr_uart_0_rx)
{
__enter_isr();
if (UART_IF & UART_IE_RX_BIT) {
char data = (char)UART_DEV->RXBUF;
UART_IF &= ~(UART_IE_RX_BIT);
ctx_rx_cb(ctx_isr_arg, data);
}
__exit_isr();
}
ISR(UART_TX_ISR, isr_uart_0_tx)
{
__enter_isr();
if (UART_IF & UART_IE_TX_BIT) {
if (ctx_tx_cb(ctx_isr_arg) == 0) {
UART_IE &= ~(UART_IE_TX_BIT);
}
else {
UART_IF &= ~(UART_IE_TX_BIT);
}
}
__exit_isr();
}
/* we use alternative UART code in case the board used the USIC module for UART
* in case of the (older) USART module */
#else
int uart_init(uart_t uart, uint32_t baudrate,
uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
{
if (uart_init_blocking(uart, baudrate) < 0) {
return -1;
}
/* save interrupt context */
ctx_rx_cb = rx_cb;
ctx_tx_cb = tx_cb;
ctx_isr_arg = arg;
/* reset interrupt flags and enable RX interrupt */
UART_IF &= ~(UART_IE_RX_BIT);
UART_IF |= (UART_IE_TX_BIT);
UART_IE |= (UART_IE_RX_BIT);
UART_IE &= ~(UART_IE_TX_BIT);
return 0;
}
int uart_init_blocking(uart_t uart, uint32_t baudrate)
{
if (uart != 0) {
return -1;
}
/* get the default UART for now -> TODO: enable for multiple devices */
msp_usci_t *dev = UART_DEV;
/* put device in reset mode while configuration is going on */
dev->ACTL1 = USCI_ACTL1_SWRST;
/* configure to UART, using SMCLK in 8N1 mode */
dev->ACTL1 |= USCI_ACTL1_SSEL_SMCLK;
dev->ACTL0 = 0;
dev->ASTAT = 0;
/* configure baudrate */
uint32_t base = ((CLOCK_CMCLK << 7) / baudrate);
uint16_t br = (uint16_t)(base >> 7);
uint8_t brs = (((base & 0x3f) * 8) >> 7);
dev->ABR0 = (uint8_t)br;
dev->ABR1 = (uint8_t)(br >> 8);
dev->AMCTL = (brs << USCI_AMCTL_BRS_SHIFT);
/* pin configuration -> TODO: move to GPIO driver once implemented */
UART_RX_PORT->SEL |= UART_RX_PIN;
UART_TX_PORT->SEL |= UART_TX_PIN;
UART_RX_PORT->DIR &= ~(UART_RX_PIN);
UART_TX_PORT->DIR &= ~(UART_TX_PIN);
/* releasing the software reset bit starts the UART */
dev->ACTL1 &= ~(USCI_ACTL1_SWRST);
return 0;
}
void uart_tx_begin(uart_t uart)
{
UART_IE |= (UART_IE_TX_BIT);
}
int uart_write(uart_t uart, char data)
{
(void)uart;
UART_DEV->ATXBUF = (uint8_t)data;
return 1;
}
int uart_write_blocking(uart_t uart, char data)
{
(void)uart;
while (!(UART_IF & UART_IE_TX_BIT));
UART_DEV->ATXBUF = (uint8_t)data;
return 1;
}
int uart_read_blocking(uart_t uart, char *data)
{
(void)uart;
while (!(UART_IF & UART_IE_RX_BIT));
*data = (char)UART_DEV->ARXBUF;
return 1;
}
void uart_poweron(uart_t uart)
{
(void)uart;
/* n/a */
}
void uart_poweroff(uart_t uart)
{
(void)uart;
/* n/a */
}
ISR(UART_RX_ISR, isr_uart_0_rx)
{
__enter_isr();
uint8_t stat = UART_DEV->ASTAT;
char data = (char)UART_DEV->ARXBUF;
if (stat & (USCI_ASTAT_FE | USCI_ASTAT_OE | USCI_ASTAT_PE | USCI_ASTAT_BRK)) {
/* some error which we do not handle, just do a pseudo read to reset the
* status register */
(void)data;
}
else {
ctx_rx_cb(ctx_isr_arg, data);
}
__exit_isr();
}
ISR(UART_TX_ISR, isr_uart0_tx)
{
__enter_isr();
if (ctx_tx_cb(ctx_isr_arg) == 0) {
UART_IE &= ~(UART_IE_TX_BIT);
}
else {
UART_IF &= ~(UART_IE_TX_BIT);
}
__exit_isr();
}
#endif