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Merge pull request #3724 from haukepetersen/add_msp430_periph_timer

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cpu/[msp|cc]430: added peripheral timer driver
This commit is contained in:
Hauke Petersen 2015-09-03 12:00:07 +02:00
commit fb8d15d34a
48 changed files with 1023 additions and 495 deletions
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1
boards/chronos/Makefile.features
View File

@ -1,2 +1,3 @@
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = msp430

17
boards/chronos/include/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2013 Freie Universität Berlin
* Copyright (C) 2013,2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -32,6 +32,21 @@ extern "C" {
#define __CC430F6137__
#endif
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
#define MSP430_INITIAL_CPU_SPEED 7372800uL
#define F_CPU MSP430_INITIAL_CPU_SPEED
#define F_RC_OSCILLATOR 32768

20
boards/chronos/include/periph_conf.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -14,17 +15,28 @@
* @brief Chronos peripheral configuration
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Real Time Clock configuration
* @brief Timer configuration
* @{
*/
#define TIMER_DEV (TIMER_A0)
#define TIMER_CHAN (5)
#define TIMER_ISR_CC0 (TIMER0_A0_VECTOR)
#define TIMER_ISR_CCX (TIMER0_A1_VECTOR)
/** @} */
/**
* @brief Real Time Clock configuration
*/
#define RTC_NUMOF (1)
@ -32,4 +44,4 @@ extern "C" {
}
#endif
#endif /* PERIPH_CONF_H_ */
#endif /* PERIPH_CONF_H */

5
boards/msb-430-common/board_init.c
View File

@ -21,6 +21,7 @@
*/
#include "cpu.h"
#include "irq.h"
#include "board.h"
#include "kernel_internal.h"
#include "msp430.h"
@ -130,7 +131,7 @@ static void msb_ports_init(void)
void msp430_set_cpu_speed(uint32_t speed)
{
dint();
disableIRQ();
__msp430_cpu_speed = speed;
msp430_init_dco();
uint16_t br;
@ -148,7 +149,7 @@ void msp430_set_cpu_speed(uint32_t speed)
IE2 |= URXIE1;
//clock_init();
eint();
enableIRQ();
}
/*---------------------------------------------------------------------------*/

2
boards/msb-430-common/uart1.c
View File

@ -53,7 +53,7 @@ void usart0irq(void);
/**
* \brief the interrupt function
*/
interrupt(USART1RX_VECTOR) usart0irq(void)
void __attribute__((interrupt(USART1RX_VECTOR))) usart0irq(void)
{
U1TCTL &= ~URXSE; /* Clear the URXS signal */
U1TCTL |= URXSE; /* Re-enable URXS - needed here?*/

1
boards/msb-430/Makefile.features
View File

@ -1 +1,2 @@
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = msp430

15
boards/msb-430/include/board.h
View File

@ -37,6 +37,21 @@ extern "C" {
#define __MSP430F1612__
#endif
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/* MSB430 core */
#define MSP430_INITIAL_CPU_SPEED 2457600uL
#define F_CPU MSP430_INITIAL_CPU_SPEED

26
boards/msb-430/include/periph_conf.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -14,11 +15,28 @@
* @brief MSB-430 peripheral configuration
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* make Travis happy: #ifdef __cplusplus extern "C" { #endif */
#ifdef __cplusplus
extern "C" {
#endif
#endif /* PERIPH_CONF_H_ */
/**
* @brief Timer configuration
* @{
*/
#define TIMER_DEV (TIMER_A)
#define TIMER_CHAN (3)
#define TIMER_ISR_CC0 (TIMERA0_VECTOR)
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */

1
boards/msb-430h/Makefile.features
View File

@ -1,2 +1,3 @@
FEATURES_PROVIDED += config
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = msp430

18
boards/msb-430h/include/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009, Freie Universitaet Berlin (FUB). All rights reserved.
* Copyright 2009, 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -16,6 +16,7 @@
* @brief Basic definitions for the MSB-430H board
*
* @author Freie Universität Berlin, Computer Systems & Telematics, FeuerWhere project
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef MSB_BOARD_H_
@ -30,6 +31,21 @@ extern "C" {
#define __MSP430F1612__
#endif
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
//MSB430 core
#define MSP430_INITIAL_CPU_SPEED 7372800uL
#define F_CPU MSP430_INITIAL_CPU_SPEED

26
boards/msb-430h/include/periph_conf.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -14,11 +15,28 @@
* @brief MSB-430h peripheral configuration
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* make Travis happy: #ifdef __cplusplus extern "C" { #endif */
#ifdef __cplusplus
extern "C" {
#endif
#endif /* PERIPH_CONF_H_ */
/**
* @brief Timer configuration
* @{
*/
#define TIMER_DEV (TIMER_A)
#define TIMER_CHAN (3)
#define TIMER_ISR_CC0 (TIMERA0_VECTOR)
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */

1
boards/telosb/Makefile.features
View File

@ -1 +1,2 @@
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = msp430

17
boards/telosb/include/board.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2013, 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -21,6 +22,7 @@
* @brief Basic definitions for the TelosB board
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef TELOSB_BOARD_H_
@ -35,6 +37,21 @@ extern "C" {
#define __MSP430F1611__
#endif
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/* TelosB core */
#define MSP430_INITIAL_CPU_SPEED 2457600uL
#define F_CPU MSP430_INITIAL_CPU_SPEED

26
boards/telosb/include/periph_conf.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -14,11 +15,28 @@
* @brief TelosB peripheral configuration
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* make Travis happy: #ifdef __cplusplus extern "C" { #endif */
#ifdef __cplusplus
extern "C" {
#endif
#endif /* PERIPH_CONF_H_ */
/**
* @brief Timer configuration
* @{
*/
#define TIMER_DEV (TIMER_A)
#define TIMER_CHAN (3)
#define TIMER_ISR_CC0 (TIMERA0_VECTOR)
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */

2
boards/telosb/uart.c
View File

@ -90,7 +90,7 @@ void usart1irq(void);
/**
* \brief the interrupt function
*/
interrupt(USART1RX_VECTOR) usart1irq(void)
void __attribute__((interrupt(USART1RX_VECTOR))) usart1irq(void)
{
/* Check status register for receive errors. */
if (U1RCTL & RXERR) {

6
boards/wsn430-common/board_init.c
View File

@ -8,6 +8,7 @@
*/
#include "cpu.h"
#include "irq.h"
#include "board.h"
#include "kernel_internal.h"
#include "msp430.h"
@ -86,8 +87,7 @@ static void msb_ports_init(void)
void msp430_set_cpu_speed(uint32_t speed)
{
dint();
disableIRQ();
__msp430_cpu_speed = speed;
msp430_init_dco();
uint16_t br;
@ -108,7 +108,7 @@ void msp430_set_cpu_speed(uint32_t speed)
//URCTL0 |= URXEIE; // allow chars to interrupt
IE1 |= URXIE0; // enable rx interrupt
IFG1 &= ~UTXIFG0;
eint();
enableIRQ();
}
/*---------------------------------------------------------------------------*/

26
boards/wsn430-common/include/periph_conf.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -14,11 +15,28 @@
* @brief WSN30 peripheral configuration
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* make Travis happy: #ifdef __cplusplus extern "C" { #endif */
#ifdef __cplusplus
extern "C" {
#endif
#endif /* PERIPH_CONF_H_ */
/**
* @brief Timer configuration
* @{
*/
#define TIMER_DEV (TIMER_A)
#define TIMER_CHAN (3)
#define TIMER_ISR_CC0 (TIMERA0_VECTOR)
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */

2
boards/wsn430-common/wsn430-uart0.c
View File

@ -43,7 +43,7 @@ void usart0irq(void);
/**
* \brief the interrupt function
*/
interrupt(USART0RX_VECTOR) usart0irq(void) {
void __attribute__((interrupt(USART0RX_VECTOR))) usart0irq(void) {
volatile int dummy = 0;
/* Check status register for receive errors. */
if(U0RCTL & RXERR) {

1
boards/wsn430-v1_3b/Makefile.features
View File

@ -1,2 +1,3 @@
FEATURES_PROVIDED += config
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = msp430

17
boards/wsn430-v1_3b/include/board.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2013 Milan Babel <babel@inf.fu-berlin.de>
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -21,6 +22,7 @@
* @brief Basic definitions for the Senslab WSN430 v1.3b board
*
* @author Milan Babel <babel@inf.fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef WSN_BOARD_H_
@ -37,6 +39,21 @@ extern "C" {
#define __MSP430F1611__
#endif
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
//MSB430 core
#define MSP430_INITIAL_CPU_SPEED 800000uL
#define F_CPU MSP430_INITIAL_CPU_SPEED

1
boards/wsn430-v1_4/Makefile.features
View File

@ -1,2 +1,3 @@
FEATURES_PROVIDED += config
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = msp430

17
boards/wsn430-v1_4/include/board.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2013 Milan Babel <babel@inf.fu-berlin.de>
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -21,6 +22,7 @@
* @brief Basic definitions for the Senslab WSN430 v1.4 board
*
* @author Milan Babel <babel@inf.fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef WSN_BOARD_H_
@ -32,6 +34,21 @@
extern "C" {
#endif
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/* for correct inclusion of <msp430.h> */
#ifndef __MSP430F1611__
#define __MSP430F1611__

1
boards/z1/Makefile.features
View File

@ -1 +1,2 @@
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = msp430

22
boards/z1/include/board.h
View File

@ -1,6 +1,6 @@
/*
* board.h - Zolertia Z1 Board.
* Copyright (C) 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -20,13 +20,12 @@
\li CC2420
* @{
*/
/**
*
* @file
* @brief Zolertia Z1 board configuration
*
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
*/
@ -40,6 +39,21 @@ extern "C" {
#define __MSP430F2617__
#endif
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/* MSP430 core */
#define MSP430_INITIAL_CPU_SPEED 8000000uL
#ifndef F_CPU

26
boards/z1/include/periph_conf.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -14,11 +15,28 @@
* @brief Zolertia Z1 peripheral configuration
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* make Travis happy: #ifdef __cplusplus extern "C" { #endif */
#ifdef __cplusplus
extern "C" {
#endif
#endif /* PERIPH_CONF_H_ */
/**
* @brief Timer configuration
* @{
*/
#define TIMER_DEV (TIMER_A)
#define TIMER_CHAN (3)
#define TIMER_ISR_CC0 (TIMERA0_VECTOR)
#define TIMER_ISR_CCX (TIMERA1_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */

2
boards/z1/uart.c
View File

@ -104,7 +104,7 @@ uint8_t uart_readByte(void)
/**
* \brief the interrupt handler for UART reception
*/
interrupt(USCIAB0RX_VECTOR) usart1irq(void)
void __attribute__((interrupt(USCIAB0RX_VECTOR))) usart1irq(void)
{
volatile int c;

2
cpu/cc430/Makefile.include
View File

@ -2,4 +2,4 @@ INCLUDES += -I$(RIOTBASE)/cpu/cc430/include/
include $(RIOTCPU)/msp430-common/Makefile.include
export USEMODULE += periph
export USEMODULE += periph hwtimer_compat

2
cpu/cc430/cc430-adc.c
View File

@ -72,7 +72,7 @@ uint16_t adc12_single_conversion(uint16_t ref, uint16_t sht, uint16_t channel)
ADC12CTL1 = ADC12SHP; /* Enable sample timer */
ADC12MCTL0 = ADC12SREF_1 + channel; /* ADC input channel */
ADC12IE = 0x001; /* ADC_IFG upon conv result-ADCMEMO */
eINT();
enableIRQ();
/* Wait 2 ticks (66us) to allow internal reference to settle */
hwtimer_wait(2);

75
cpu/cc430/hwtimer_cc430.c
View File

@ -1,75 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cc430
* @{
*/
/**
* @file
* @brief cc430 hardware timer driver
*
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Aleksandr Mikoff <sir.enmity@gmail.com>
*
*/
#include "cpu.h"
#include "hwtimer.h"
#include "arch/hwtimer_arch.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
extern void (*int_handler)(int);
extern void timer_unset(short timer);
msp430_timer_t msp430_timer[HWTIMER_MAXTIMERS];
void timerA_init(void)
{
volatile unsigned int *ccr = &TA0CCR0;
volatile unsigned int *ctl = &TA0CCTL0;
TA0CTL = TASSEL_1 + TACLR; /* Clear the timer counter, set ACLK */
TA0CTL &= ~TAIFG; /* Clear the IFG */
TA0CTL &= ~TAIE; /* Disable TAIE (overflow IRQ) */
for (int i = 0; i < HWTIMER_MAXTIMERS; i++) {
*(ccr + i) = 0;
*(ctl + i) &= ~(CCIFG);
*(ctl + i) &= ~(CCIE);
}
TA0CTL |= MC_2;
}
interrupt(TIMER0_A0_VECTOR) __attribute__((naked)) timer0_a0_isr(void)
{
__enter_isr();
timer_unset(0);
int_handler(0);
__exit_isr();
}
interrupt(TIMER0_A1_VECTOR) __attribute__((naked)) timer0_a1_5_isr(void)
{
__enter_isr();
/* determine which CCR has been hit, and fire the appropriate callback */
short timer = TA0IV >> 1;
timer_unset(timer);
int_handler(timer);
__exit_isr();
}

123
cpu/cc430/include/cc430_regs.h Normal file
View File

@ -0,0 +1,123 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc430
* @{
*
* @file
* @brief Cortex CMSIS style definition of CC430 registers
*
* @todo This file is incomplete, not all registers are listed. Further
* There are probably some inconsistencies throughout the MSP430
* family which need to be addressed.
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef CC430_REGS_H
#define CC430_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Shortcut to specify 8-bit wide registers
*/
#define REG8 volatile uint8_t
/**
* @brief Shortcut to specify 16-bit wide registers
*/
#define REG16 volatile uint16_t
/**
* @brief Timer module registers
*/
typedef struct {
REG16 CTL; /**< timer control */
REG16 CCTL[7]; /**< capture compare channel control */
REG16 R; /**< current counter value */
REG16 CCR[7]; /**< capture compare channel values */
REG16 reserved[7]; /**< reserved */
REG16 IV; /**< interrupt vector */
REG16 EX0; /**< expansion 0 */
} msp_timer_t;
/**
* @brief Timer Control register bitmap
* @{
*/
#define CTL_IFG (0x0001)
#define CTL_IE (0x0002)
#define CTL_CLR (0x0004)
#define CTL_MC_MASK (0x0030)
#define CTL_MC_STOP (0x0000)
#define CTL_MC_UP (0x0010)
#define CTL_MC_CONT (0x0020)
#define CTL_MC_UPDOWN (0x0030)
#define CTL_ID_MASK (0x00c0)
#define CTL_ID_DIV1 (0x0000)
#define CTL_ID_DIV2 (0x0040)
#define CTL_ID_DIV4 (0x0080)
#define CTL_ID_DIV8 (0x00c0)
#define CTL_TASSEL_MASK (0x0300)
#define CTL_TASSEL_TCLK (0x0000)
#define CTL_TASSEL_ACLK (0x0100)
#define CTL_TASSEL_SMCLK (0x0200)
#define CTL_TASSEL_INV_TCLK (0x0300)
/** @} */
/**
* @brief Timer Channel Control register bitmap
* @{
*/
#define CCTL_CCIFG (0x0001)
#define CCTL_COV (0x0002)
#define CCTL_OUT (0x0004)
#define CCTL_CCI (0x0008)
#define CCTL_CCIE (0x0010)
#define CCTL_OUTMOD_MASK (0x00e0)
#define CCTL_OUTMOD_OUTVAL (0x0000)
#define CCTL_OUTMOD_SET (0x0020)
#define CCTL_OUTMOD_TOG_RESET (0x0040)
#define CCTL_OUTMOD_SET_RESET (0x0060)
#define CCTL_OUTMOD_TOGGLE (0x0080)
#define CCTL_OUTMOD_RESET (0x00a0)
#define CCTL_OUTMOD_TOG_SET (0x00c0)
#define CCTL_OUTMOD_RESET_SET (0x00e0)
#define CCTL_CAP (0x0100)
#define CCTL_CLLD_MASK (0x0600)
#define CCTL_SCS (0x0800)
#define CCTL_CCIS_MASK (0x3000)
#define CCTL_CM_MASK (0xc000)
/** @} */
/**
* @brief Base register address definitions
* @{
*/
#define TIMER_A0_BASE ((uint16_t)0x0340)
#define TIMER_A1_BASE ((uint16_t)0x0380)
/** @} */
/**
* @brief Typing of base register objects
* @{
*/
#define TIMER_A0 ((msp_timer_t *)TIMER_A0_BASE)
#define TIMER_A1 ((msp_timer_t *)TIMER_A1_BASE)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CC430_REGS_H */
/** @} */

36
cpu/cc430/include/periph_cpu.h Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc430
* @{
*
* @file
* @brief CPU specific definitions for internal peripheral handling
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/
#ifndef CPU_PERIPH_H_
#define CPU_PERIPH_H_
#include "cpu.h"
#include "cc430_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* more to come here... */
#ifdef __cplusplus
}
#endif
#endif /* CPU_PERIPH_H_ */
/** @} */

2
cpu/cc430/periph/Makefile
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@ -1 +1,3 @@
MODULE = periph
include $(RIOTBASE)/Makefile.base

146
cpu/cc430/periph/timer.c Normal file
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@ -0,0 +1,146 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc430
* @{
*
* @file
* @brief Low-level timer driver implementation
*
* This implementation does only support one fixed timer, as defined in the
* boards periph_conf.h file.
*
* @todo Generalize to handle more timers and make them configurable
* through the board's `periph_conf.h`
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph_cpu.h"
#include "periph_conf.h"
#include "periph/timer.h"
/**
* @brief Save reference to the timer callback
*/
static void (*isr_cb)(int chan);
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
{
/* using fixed TIMER_DEV for now */
if (dev != 0) {
return -1;
}
/* TODO: configure time-base depending on us_per_tick value */
if (us_per_tick != 1) {
return -1;
}
/* reset the timer A configuration */
TIMER_DEV->CTL = CTL_CLR;
/* save callback */
isr_cb = callback;
/* configure timer to use the SMCLK with prescaler of 8 */
TIMER_DEV->CTL = (CTL_TASSEL_SMCLK | CTL_ID_DIV8);
/* configure CC channels */
for (int i = 0; i < TIMER_CHAN; i++) {
TIMER_DEV->CCTL[i] = 0;
}
/* start the timer in continuous mode */
TIMER_DEV->CTL |= CTL_MC_CONT;
return 0;
}
int timer_set(tim_t dev, int channel, unsigned int timeout)
{
uint16_t target = TIMER_DEV->R + (uint16_t)timeout;
return timer_set_absolute(dev, channel, (unsigned int)target);
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
if (dev != 0 || channel > TIMER_CHAN) {
return -1;
}
TIMER_DEV->CCR[channel] = value;
TIMER_DEV->CCTL[channel] &= ~(CCTL_CCIFG);
TIMER_DEV->CCTL[channel] |= (CCTL_CCIE);
return 0;
}
int timer_clear(tim_t dev, int channel)
{
if (dev != 0 || channel > TIMER_CHAN) {
return -1;
}
TIMER_DEV->CCTL[channel] &= ~(CCTL_CCIE);
return 0;
}
unsigned int timer_read(tim_t dev)
{
return (unsigned int)TIMER_DEV->R;
}
void timer_start(tim_t dev)
{
TIMER_DEV->CTL |= CTL_MC_CONT;
}
void timer_stop(tim_t dev)
{
TIMER_DEV->CTL &= ~(CTL_MC_MASK);
}
void timer_irq_enable(tim_t dev)
{
/* TODO: not supported, yet
*
* Problem here: there is no means, of globally disabling timer interrupts.
* We could just enable the interrupts for all CC channels, but this would
* mean, that we might enable interrupts for channels, that are not active.
* I guess we need to remember the interrupt state of all channels before
* disabling and then restore this state when enabling again?! */
}
void timer_irq_disable(tim_t dev)
{
/* TODO: not supported, yet */
}
void timer_reset(tim_t dev)
{
TIMER_DEV->R = 0;
}
ISR(TIMER_ISR_CC0, isr_timer_a_cc0)
{
__enter_isr();
TIMER_DEV->CCTL[0] &= ~(CCTL_CCIE);
isr_cb(0);
__exit_isr();
}
ISR(TIMER_ISR_CCX, isr_timer_a_ccx_isr)
{
__enter_isr();
int chan = (int)(TIMER_DEV->IV >> 1);
TIMER_DEV->CCTL[chan] &= ~(CCTL_CCIE);
isr_cb(chan);
__exit_isr();
}

2
cpu/msp430-common/Makefile
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@ -1,3 +1,3 @@
MODULE =msp430_common
MODULE = msp430_common
include $(RIOTBASE)/Makefile.base

182
cpu/msp430-common/hwtimer_cpu.c
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@ -1,182 +0,0 @@
/*
* Copyright (C) 2014 Freie Universitaet Berlin (FUB) and INRIA. All rights reserved.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu
* @{
*/
/**
* @file
* @brief msp430 hardware timer driver generic functions
*
* @author Freie Universitaet Berlin, Computer Systems and Telematics group
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
*
*/
#include <stdint.h>
#include "cpu.h"
#include "panic.h"
#include "hwtimer.h"
#include "arch/hwtimer_arch.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
void (*int_handler)(int);
extern void timerA_init(void);
#ifndef CC430
extern void timerB_init(void);
#endif
extern volatile msp430_timer_t msp430_timer[HWTIMER_MAXTIMERS];
/*
* the 3 following functions handle the diversity of timers
* we can encounter in the various MCUs in the MSP430 family
*/
static volatile unsigned int *get_control_reg_for_msp430_timer(int index)
{
volatile unsigned int *ptr = NULL;
#ifndef CC430
switch (msp430_timer[index].base_timer) {
case TIMER_A:
ptr = &TACCTL0;
break;
case TIMER_B:
ptr = &TBCCTL0;
break;
default:
core_panic(0x0, "Wrong timer kind for MSP430");
}
#else
ptr = &TA0CCTL0;
#endif
ptr += msp430_timer[index].ccr_num;
return ptr;
}
static volatile unsigned int *get_comparator_reg_for_msp430_timer(int index)
{
volatile unsigned int *ptr = NULL;
#ifndef CC430
switch (msp430_timer[index].base_timer) {
case TIMER_A:
ptr = &TACCR0;
break;
case TIMER_B:
ptr = &TBCCR0;
break;
default:
core_panic(0x0, "Wrong timer kind for MSP430");
}
#else
ptr = &TA0CCR0;
#endif
ptr += msp430_timer[index].ccr_num;
return ptr;
}
#ifdef CC430
/* CC430 have "TimerA0", "TimerA1" and so on... */
#define TIMER_VAL_REG (TA0R)
#else
/* ... while other MSP430 MCUs have "TimerA", "TimerB".
Cheers for TI and its consistency! */
#define TIMER_VAL_REG (TBR)
#endif
/* hardware-dependent functions */
static void timer_disable_interrupt(short timer)
{
volatile unsigned int *ptr = get_control_reg_for_msp430_timer(timer);
*ptr &= ~(CCIFG);
*ptr &= ~(CCIE);
}
static void timer_enable_interrupt(short timer)
{
volatile unsigned int *ptr = get_control_reg_for_msp430_timer(timer);
*ptr |= CCIE;
*ptr &= ~(CCIFG);
}
static void timer_set_nostart(uint32_t value, short timer)
{
volatile unsigned int *ptr = get_comparator_reg_for_msp430_timer(timer);
/* ensure we won't set the timer to a "past" tick */
if (value <= hwtimer_arch_now()) {
value = hwtimer_arch_now() + 2;
}
*ptr = (value & 0xFFFF);
}
static void timer_set(uint32_t value, short timer)
{
DEBUG("Setting timer %u to %lu\n", timer, value);
timer_set_nostart(value, timer);
timer_enable_interrupt(timer);
}
void timer_unset(short timer)
{
volatile unsigned int *ptr = get_comparator_reg_for_msp430_timer(timer);
timer_disable_interrupt(timer);
*ptr = 0;
}
unsigned long hwtimer_arch_now(void)
{
return (TIMER_VAL_REG & 0xffff);
}
void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu)
{
(void) fcpu;
#ifndef CC430
timerB_init();
#endif
timerA_init();
int_handler = handler;
}
void hwtimer_arch_enable_interrupt(void)
{
for (int i = 0; i < HWTIMER_MAXTIMERS; i++) {
timer_enable_interrupt(i);
}
}
void hwtimer_arch_disable_interrupt(void)
{
for (int i = 0; i < HWTIMER_MAXTIMERS; i++) {
timer_disable_interrupt(i);
}
}
void hwtimer_arch_set(unsigned long offset, short timer)
{
uint32_t value = hwtimer_arch_now() + offset;
hwtimer_arch_set_absolute(value, timer);
}
void hwtimer_arch_set_absolute(unsigned long value, short timer)
{
timer_set(value, timer);
}
void hwtimer_arch_unset(short timer)
{
timer_unset(timer);
}

23
cpu/msp430-common/include/cpu.h
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@ -22,7 +22,6 @@
*/
#include <stdio.h>
#include <legacymsp430.h>
#include <msp430.h>
#include "board.h"
@ -40,6 +39,19 @@ extern "C" {
*/
#define WORDSIZE 16
/**
* @brief Macro for defining interrupt service routines
*/
#define ISR(a,b) void __attribute__((naked, interrupt (a))) b(void)
/**
* @brief Deprecated interrupt control functions for backward compatibility
* @{
*/
#define eINT enableIRQ
#define dINT disableIRQ
/** @} */
/**
* @brief The current ISR state (inside or not)
*/
@ -50,13 +62,6 @@ extern volatile int __inISR;
*/
extern char __isr_stack[MSP430_ISR_STACK_SIZE];
/**
* @brief definition of legacy interrupt control functions
*/
#define eINT enableIRQ
#define dINT disableIRQ
/** @} */
/**
* @brief Save the current thread context from inside an ISR
*/
@ -105,7 +110,7 @@ inline void __restore_context_isr(void)
inline void __enter_isr(void)
{
__save_context_isr();
__asm__("mov.w %0,r1" : : "i"(__isr_stack+MSP430_ISR_STACK_SIZE));
__asm__("mov.w %0,r1" : : "i"(__isr_stack + MSP430_ISR_STACK_SIZE));
__inISR = 1;
}

63
cpu/msp430-common/include/hwtimer_cpu.h
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@ -1,5 +1,6 @@
/*
* Copyright (C) 2014 Freie Universitaet Berlin (FUB) and INRIA. All rights reserved.
* Copyright (C) 2014 INRIA
* 2014, 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -7,66 +8,36 @@
*/
/**
* @ingroup cpu_msp430_common
* @ingroup cpu_msp430-common
* @{
*/
/**
* @file
* @brief msp430 hardware timer driver definitions
*
* @author Freie Universitaet Berlin, Computer Systems and Telematics group
* @file
* @brief Hardware timer configuration for MSP430 based CPUs
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
*/
#ifndef HWTIMER_CPU_H_
#define HWTIMER_CPU_H_
#include <stdint.h>
#include "cpu.h"
#include "board.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__MSP430_HAS_TA2__)
#define TIMER_A_MAXCOMP 2
#elif defined (__MSP430_HAS_TA3__)
#define TIMER_A_MAXCOMP 3
#elif defined (__MSP430_HAS_T0A5__)
#define TIMER_A_MAXCOMP 5
#else
#define TIMER_A_MAXCOMP 0
#endif
#if defined (__MSP430_HAS_TB3__)
#define TIMER_B_MAXCOMP 3
#elif defined (__MSP430_HAS_TB7__)
#define TIMER_B_MAXCOMP 7
#else
#define TIMER_B_MAXCOMP 0
#endif
#define HWTIMER_MAXTIMERS (TIMER_A_MAXCOMP + TIMER_B_MAXCOMP)
#ifndef HWTIMER_MAXTIMERS
#warning "HWTIMER_MAXTIMERS UNSET!"
#define HWTIMER_MAXTIMERS 0
#endif
typedef struct {
enum {
TIMER_A,
TIMER_B,
} base_timer;
uint8_t ccr_num;
} msp430_timer_t;
#define HWTIMER_SPEED (F_RC_OSCILLATOR)
#define HWTIMER_MAXTICKS (0x0000FFFF)
/**
* @brief Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS (TIMER_CHAN)
#define HWTIMER_SPEED (F_RC_OSCILLATOR)
#define HWTIMER_MAXTICKS (0x0000FFFF)
/** @} */
#ifdef __cplusplus
}

5
cpu/msp430-common/msp430-main.c
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@ -43,6 +43,7 @@
*/
#include "cpu.h"
#include "irq.h"
/*---------------------------------------------------------------------------*/
static void
@ -109,10 +110,10 @@ static char *cur_break = (char *) &_end;
void msp430_cpu_init(void)
{
dint();
disableIRQ();
init_ports();
// lpm_init();
eint();
enableIRQ();
if ((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug!*/
cur_break++;

2
cpu/msp430fxyz/Makefile
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@ -2,6 +2,6 @@ MODULE =cpu
include $(RIOTCPU)/$(CPU)/Makefile.include
DIRS = $(RIOTCPU)/msp430-common/
DIRS = $(RIOTCPU)/msp430-common periph
include $(RIOTBASE)/Makefile.base

2
cpu/msp430fxyz/Makefile.include
View File

@ -1,3 +1,5 @@
INCLUDES += -I$(RIOTCPU)/msp430fxyz/include/
include $(RIOTCPU)/msp430-common/Makefile.include
export USEMODULE += periph hwtimer_compat

127
cpu/msp430fxyz/hwtimer_msp430.c
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@ -1,127 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu
* @{
*
* @file
* @brief MSP430Fxyz timer functions
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Milan Babel <babel@inf.fu-berlin.de>
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
*
* @}
*/
#include "cpu.h"
#include "hwtimer.h"
#include "arch/hwtimer_arch.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
extern void (*int_handler)(int);
extern void timer_unset(short timer);
msp430_timer_t msp430_timer[HWTIMER_MAXTIMERS];
#define CCRA_NUM_TO_INDEX(ccr) (ccr)
#define CCRB_NUM_TO_INDEX(ccr) ((ccr) + TIMER_A_MAXCOMP)
void timerA_init(void)
{
TACTL = TASSEL_1 + TACLR; /* Clear the timer counter, set ACLK */
TACTL &= ~(TAIFG); /* Clear the IFG */
TACTL &= ~(TAIE); /* Disable TAIE (overflow IRQ) */
for (uint8_t i = 0; i < TIMER_A_MAXCOMP; i++) {
volatile unsigned int *ccr = &TACCR0 + (i);
volatile unsigned int *ctl = &TACCTL0 + (i);
*ccr = 0;
*ctl &= ~(CCIFG);
*ctl &= ~(CCIE);
/* intialize the corresponding msp430_timer struct */
short index = CCRA_NUM_TO_INDEX(i);
msp430_timer[index].base_timer = TIMER_A;
msp430_timer[index].ccr_num = i;
}
TACTL |= MC_2;
}
void timerB_init(void)
{
TBCTL = TBSSEL_1 + TBCLR; /* Clear the timer counter, set ACLK */
TBCTL &= ~(TBIFG); /* Clear the IFG */
TBCTL &= ~(TBIE); /* Disable TBIE (overflow IRQ) */
for (uint8_t i = 0; i < TIMER_B_MAXCOMP; i++) {
volatile unsigned int *ccr = &TBCCR0 + (i);
volatile unsigned int *ctl = &TBCCTL0 + (i);
*ccr = 0;
*ctl &= ~(CCIFG);
*ctl &= ~(CCIE);
/* intialize the corresponding msp430_timer struct */
short index = CCRB_NUM_TO_INDEX(i);
msp430_timer[index].base_timer = TIMER_B;
msp430_timer[index].ccr_num = i;
}
TBCTL |= MC_2;
}
interrupt(TIMERA0_VECTOR) __attribute__((naked)) timerA_isr_ccr0(void)
{
__enter_isr();
short timer = CCRA_NUM_TO_INDEX(0);
timer_unset(timer);
int_handler(timer);
__exit_isr();
}
interrupt(TIMERA1_VECTOR) __attribute__((naked)) timerA_isr(void)
{
__enter_isr();
/* determine which CCR has been hit, and fire the appropriate callback */
short timer = CCRA_NUM_TO_INDEX(TAIV >> 1);
timer_unset(timer);
int_handler(timer);
__exit_isr();
}
interrupt(TIMERB0_VECTOR) __attribute__((naked)) timerB_isr_ccr0(void)
{
__enter_isr();
short timer = CCRB_NUM_TO_INDEX(0);
timer_unset(timer);
int_handler(timer);
__exit_isr();
}
interrupt(TIMERB1_VECTOR) __attribute__((naked)) timerB_isr(void)
{
__enter_isr();
/* determine which CCR has been hit, and fire the appropriate callback */
short timer = CCRB_NUM_TO_INDEX(TBIV >> 1);
timer_unset(timer);
int_handler(timer);
__exit_isr();
}

218
cpu/msp430fxyz/include/msp430_regs.h Normal file
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@ -0,0 +1,218 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430-common
* @{
*
* @file
* @brief Cortex CMSIS style definition of MSP430 registers
*
* @todo This file is incomplete, not all registers are listed. Further
* There are probably some inconsistencies throughout the MSP430
* family which need to be addressed.
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef MSP430_REGS_H
#define MSP430_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Shortcut to specify 8-bit wide registers
*/
#define REG8 volatile uint8_t
/**
* @brief Shortcut to specify 16-bit wide registers
*/
#define REG16 volatile uint16_t
/**
* @brief Special function registers
*/
typedef struct {
REG8 IE1; /**< interrupt enable 1 */
REG8 IE2; /**< interrupt enable 2 */
REG8 IFG1; /**< interrupt flag 1 */
REG8 IFG2; /**< interrupt flag 2 */
REG8 ME1; /**< module enable 1 */
REG8 ME2; /**< module enable 2 */
} msp_sfr_t;
/**
* @brief Digital I/O Port w/o interrupt functionality (P3-P6)
*/
typedef struct {
REG8 IN; /**< input data */
REG8 OD; /**< output data */
REG8 DIR; /**< pin direction */
REG8 SEL; /**< alternative function select */
} msp_port_t;
/**
* @brief Digital I/O Port with interrupt functionality (P1 & P2)
*/
typedef struct {
REG8 IN; /**< input data */
REG8 OD; /**< output data */
REG8 DIR; /**< pin direction */
REG8 IFG; /**< interrupt flag */
REG8 IES; /**< interrupt edge select */
REG8 IE; /**< interrupt enable */
REG8 SEL; /**< alternative function select */
} msp_port_isr_t;
/**
* @brief USART (UART, SPI and I2C) registers
*/
typedef struct {
REG8 CTL; /**< USART control */
REG8 TCTL; /**< transmit control */
REG8 RCTL; /**< receive control */
REG8 MCTL; /**< modulation control */
REG8 BR0; /**< baud rate control 0 */
REG8 RR1; /**< baud rate control 1 */
REG8 RXBUF; /**< receive buffer */
REG8 TXBUF; /**< transmit buffer */
} msp_usart_t;
/**
* @brief System clock module configuration registers
*/
typedef struct {
REG8 DCOCTL; /**< digital controlled oscillator control */
REG8 BCSCTL1; /**< basic clock system control 1 */
REG8 BCSCTL2; /**< basic clock system control 2 */
} msp_clk_t;
/**
* @brief Watchdog configuration registers
*/
typedef struct {
REG16 TCTL; /**< watchdog time control */
} msp_wd_t;
/**
* @brief Timer interrupt status registers
*/
typedef struct {
REG16 TBIV; /**< TIMER_A interrupt status */
REG16 reserved[7]; /**< reserved */
REG16 TAIV; /**< TIMER_B interrupt status */
} msp_timer_ivec_t;
/**
* @brief Timer module registers
*/
typedef struct {
REG16 CTL; /**< timer control */
REG16 CCTL[7]; /**< capture compare channel control */
REG16 R; /**< current counter value */
REG16 CCR[7]; /**< capture compare channel values */
} msp_timer_t;
/**
* @brief Timer Control register bitmap
* @{
*/
#define CTL_IFG (0x0001)
#define CTL_IE (0x0002)
#define CTL_CLR (0x0004)
#define CTL_MC_MASK (0x0030)
#define CTL_MC_STOP (0x0000)
#define CTL_MC_UP (0x0010)
#define CTL_MC_CONT (0x0020)
#define CTL_MC_UPDOWN (0x0030)
#define CTL_ID_MASK (0x00c0)
#define CTL_ID_DIV1 (0x0000)
#define CTL_ID_DIV2 (0x0040)
#define CTL_ID_DIV4 (0x0080)
#define CTL_ID_DIV8 (0x00c0)
#define CTL_TASSEL_MASK (0x0300)
#define CTL_TASSEL_TCLK (0x0000)
#define CTL_TASSEL_ACLK (0x0100)
#define CTL_TASSEL_SMCLK (0x0200)
#define CTL_TASSEL_INV_TCLK (0x0300)
/** @} */
/**
* @brief Timer Channel Control register bitmap
* @{
*/
#define CCTL_CCIFG (0x0001)
#define CCTL_COV (0x0002)
#define CCTL_OUT (0x0004)
#define CCTL_CCI (0x0008)
#define CCTL_CCIE (0x0010)
#define CCTL_OUTMOD_MASK (0x00e0)
#define CCTL_OUTMOD_OUTVAL (0x0000)
#define CCTL_OUTMOD_SET (0x0020)
#define CCTL_OUTMOD_TOG_RESET (0x0040)
#define CCTL_OUTMOD_SET_RESET (0x0060)
#define CCTL_OUTMOD_TOGGLE (0x0080)
#define CCTL_OUTMOD_RESET (0x00a0)
#define CCTL_OUTMOD_TOG_SET (0x00c0)
#define CCTL_OUTMOD_RESET_SET (0x00e0)
#define CCTL_CAP (0x0100)
#define CCTL_CLLD_MASK (0x0600)
#define CCTL_SCS (0x0800)
#define CCTL_CCIS_MASK (0x3000)
#define CCTL_CM_MASK (0xc000)
/** @} */
/**
* @brief Base register address definitions
* @{
*/
#define SFR_BASE ((uint16_t)0x0000)
#define PORT_1_BASE ((uint16_t)0x0020)
#define PORT_2_BASE ((uint16_t)0x0028)
#define PORT_3_BASE ((uint16_t)0x0018)
#define PORT_4_BASE ((uint16_t)0x001c)
#define PORT_5_BASE ((uint16_t)0x0030)
#define PORT_6_BASE ((uint16_t)0x0034)
#define CLK_BASE ((uint16_t)0x0056)
#define USART_0_BASE ((uint16_t)0x0070)
#define USART_1_BASE ((uint16_t)0x0078)
#define TIMER_IVEC_BASE ((uint16_t)0x011e)
#define TIMER_A_BASE ((uint16_t)0x0160)
#define TIMER_B_BASE ((uint16_t)0x0180)
#define WD_BASE ((uint16_t)0x0120)
/** @} */
/**
* @brief Typing of base register objects
* @{
*/
#define SFR ((msp_sfr_t *)SFR_BASE)
#define PORT_1 ((msp_port_t *)PORT_1_BASE)
#define PORT_2 ((msp_port_t *)PORT_2_BASE)
#define PORT_3 ((msp_port_t *)PORT_3_BASE)
#define PORT_4 ((msp_port_t *)PORT_4_BASE)
#define PORT_5 ((msp_port_t *)PORT_5_BASE)
#define PORT_6 ((msp_port_t *)PORT_6_BASE)
#define CLK ((msp_clk_t *)CLK_BASE)
#define USART_0 ((msp_usart_t *)USART_0_BASE)
#define USART_1 ((msp_usart_t *)USART_1_BASE)
#define TIMER_IVEC ((msp_timer_ivec_t *)TIMER_IVEC_BASE)
#define TIMER_A ((msp_timer_t *)TIMER_A_BASE)
#define TIMER_B ((msp_timer_t *)TIMER_B_BASE)
#define WD ((msp_wd_t *)WD_BASE)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* MSP430_REGS_H */
/** @} */

36
cpu/msp430fxyz/include/periph_cpu.h Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430-common
* @{
*
* @file
* @brief CPU specific definitions for internal peripheral handling
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/
#ifndef CPU_PERIPH_H_
#define CPU_PERIPH_H_
#include "cpu.h"
#include "msp430_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* more to come here... */
#ifdef __cplusplus
}
#endif
#endif /* CPU_PERIPH_H_ */
/** @} */

3
cpu/msp430fxyz/periph/Makefile Normal file
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@ -0,0 +1,3 @@
MODULE = periph
include $(RIOTBASE)/Makefile.base

146
cpu/msp430fxyz/periph/timer.c Normal file
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@ -0,0 +1,146 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430-common
* @{
*
* @file
* @brief Low-level timer driver implementation
*
* This implementation does only support one fixed timer, as defined in the
* boards periph_conf.h file.
*
* @todo Generalize to handle more timers and make them configurable
* through the board's `periph_conf.h`
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph_cpu.h"
#include "periph_conf.h"
#include "periph/timer.h"
/**
* @brief Save reference to the timer callback
*/
static void (*isr_cb)(int chan);
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
{
/* using fixed TIMER_DEV for now */
if (dev != 0) {
return -1;
}
/* TODO: configure time-base depending on us_per_tick value */
if (us_per_tick != 1) {
return -1;
}
/* reset the timer A configuration */
TIMER_DEV->CTL = CTL_CLR;
/* save callback */
isr_cb = callback;
/* configure timer to use the SMCLK with prescaler of 8 */
TIMER_DEV->CTL = (CTL_TASSEL_SMCLK | CTL_ID_DIV8);
/* configure CC channels */
for (int i = 0; i < TIMER_CHAN; i++) {
TIMER_DEV->CCTL[i] = 0;
}
/* start the timer in continuous mode */
TIMER_DEV->CTL |= CTL_MC_CONT;
return 0;
}
int timer_set(tim_t dev, int channel, unsigned int timeout)
{
uint16_t target = TIMER_DEV->R + (uint16_t)timeout;
return timer_set_absolute(dev, channel, (unsigned int)target);
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
if (dev != 0 || channel > TIMER_CHAN) {
return -1;
}
TIMER_DEV->CCR[channel] = value;
TIMER_DEV->CCTL[channel] &= ~(CCTL_CCIFG);
TIMER_DEV->CCTL[channel] |= (CCTL_CCIE);
return 0;
}
int timer_clear(tim_t dev, int channel)
{
if (dev != 0 || channel > TIMER_CHAN) {
return -1;
}
TIMER_DEV->CCTL[channel] &= ~(CCTL_CCIE);
return 0;
}
unsigned int timer_read(tim_t dev)
{
return (unsigned int)TIMER_DEV->R;
}
void timer_start(tim_t dev)
{
TIMER_DEV->CTL |= CTL_MC_CONT;
}
void timer_stop(tim_t dev)
{
TIMER_DEV->CTL &= ~(CTL_MC_MASK);
}
void timer_irq_enable(tim_t dev)
{
/* TODO: not supported, yet
*
* Problem here: there is no means, of globally disabling timer interrupts.
* We could just enable the interrupts for all CC channels, but this would
* mean, that we might enable interrupts for channels, that are not active.
* I guess we need to remember the interrupt state of all channels before
* disabling and then restore this state when enabling again?! */
}
void timer_irq_disable(tim_t dev)
{
/* TODO: not supported, yet */
}
void timer_reset(tim_t dev)
{
TIMER_DEV->R = 0;
}
ISR(TIMER_ISR_CC0, isr_timer_a_cc0)
{
__enter_isr();
TIMER_DEV->CCTL[0] &= ~(CCTL_CCIE);
isr_cb(0);
__exit_isr();
}
ISR(TIMER_ISR_CCX, isr_timer_a_ccx)
{
__enter_isr();
int chan = (int)(TIMER_IVEC->TAIV >> 1);
TIMER_DEV->CCTL[chan] &= ~(CCTL_CCIE);
isr_cb(chan);
__exit_isr();
}

14
tests/xtimer_remove/main.c
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@ -24,7 +24,7 @@
#include "thread.h"
#include "xtimer.h"
#define N (3U)
#define NUMOF (3U)
int main(void)
{
@ -32,18 +32,18 @@ int main(void)
kernel_pid_t me = thread_getpid();
for (unsigned int n = 0; n < N; n++) {
printf("Setting %u timers, removing timer %u/%u\n", N, n, N);
xtimer_t timers[N];
msg_t msg[N];
for (unsigned int i = 0; i < N; i++) {
for (unsigned int n = 0; n < NUMOF; n++) {
printf("Setting %u timers, removing timer %u/%u\n", NUMOF, n, NUMOF);
xtimer_t timers[NUMOF];
msg_t msg[NUMOF];
for (unsigned int i = 0; i < NUMOF; i++) {
msg[i].type = i;
xtimer_set_msg(&timers[i], 100000*(i+1), &msg[i], me);
}
xtimer_remove(&timers[n]);
unsigned int num = N-1;
unsigned int num = NUMOF-1;
while(num--) {
msg_t m;
msg_receive(&m);

2
tests/xtimer_usleep_until/Makefile
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@ -4,6 +4,8 @@ include ../Makefile.tests_common
BOARD ?= native
RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := chronos
FEATURES_REQUIRED += periph_timer
USEMODULE += xtimer

8
tests/xtimer_usleep_until/main.c
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@ -22,9 +22,9 @@
#include "xtimer.h"
#include "periph_conf.h"
#define N 1000
#define NUMOF 1000
uint32_t res[N];
uint32_t res[NUMOF];
int main(void)
{
@ -32,7 +32,7 @@ int main(void)
uint32_t interval = 1000;
for (int i = 0; i < N; i++) {
for (int i = 0; i < NUMOF; i++) {
printf("Testing interval %u...\n", (unsigned)interval);
uint32_t last_wakeup = xtimer_now();
uint32_t before = last_wakeup;
@ -42,7 +42,7 @@ int main(void)
interval -= 1;
}
for (int i = 0; i < N; i++) {
for (int i = 0; i < NUMOF; i++) {
printf("%4d diff=%i\n", i, (int)res[i]);
}