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Merge #19923
19923: boards: add Silabs EFM32 Giant Gecko GG11 Starter Kit r=miri64 a=gschorcht ### Contribution description The PR adds the support for the EFM32GG11B family and the Silabs EFM32 Giant Gecko GG11 Starter Kit board. The Silabs EFM32 Giant Gecko GG11 has the following on-board features: - EFM32GG11B MCU with 2 MB flash and 512 kB RAM - J-Link USB debugger - 176x176 RGB LCD (not supported) - 2 user buttons, 2 user RGB LEDs and a touch slider - Si7021 Relative Humidity and Temperature Sensor - Si7210 Hall-Effect Sensor (not supported) - USB OTG interface (Device mode supported) - 32 MByte Quad-SPI Flash (not supported yet) - SD card slot (not supported yet, follow-up PR based on PR #19760) - RJ-45 Ethernet (not supported) - Dual microphones (not supported) ### Testing procedure Basic tests should work. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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32
boards/slstk3701a/Kconfig
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32
boards/slstk3701a/Kconfig
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@ -0,0 +1,32 @@
|
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# Copyright (c) 2020 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
|
||||
config BOARD
|
||||
default "slstk3701a" if BOARD_SLSTK3701A
|
||||
|
||||
config BOARD_SLSTK3701A
|
||||
bool
|
||||
default y
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||||
select BOARD_COMMON_SILABS
|
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select CPU_MODEL_EFM32GG11B820F2048GL192
|
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select HAS_PERIPH_ADC
|
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select HAS_PERIPH_DAC
|
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select HAS_PERIPH_I2C
|
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select HAS_PERIPH_RTC
|
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select HAS_PERIPH_RTT
|
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select HAS_PERIPH_SPI
|
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select HAS_PERIPH_TIMER
|
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select HAS_PERIPH_UART
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select HAS_PERIPH_UART_MODECFG
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select HAS_PERIPH_USBDEV
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|
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select HAVE_SAUL_GPIO
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select HAVE_SI7021
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|
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select MODULE_SILABS_AEM if TEST_KCONFIG
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select MODULE_SILABS_BC if TEST_KCONFIG
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source "$(RIOTBOARD)/common/silabs/Kconfig"
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5
boards/slstk3701a/Makefile
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5
boards/slstk3701a/Makefile
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@ -0,0 +1,5 @@
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MODULE = board
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DIRS = $(RIOTBOARD)/common/silabs
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include $(RIOTBASE)/Makefile.base
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13
boards/slstk3701a/Makefile.dep
Normal file
13
boards/slstk3701a/Makefile.dep
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@ -0,0 +1,13 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += efm32_coretemp
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USEMODULE += saul_gpio
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USEMODULE += si7021
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endif
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# add board common drivers
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USEMODULE += boards_common_silabs
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USEMODULE += silabs_aem
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USEMODULE += silabs_bc
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# include board common dependencies
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include $(RIOTBOARD)/common/silabs/Makefile.dep
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16
boards/slstk3701a/Makefile.features
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16
boards/slstk3701a/Makefile.features
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@ -0,0 +1,16 @@
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CPU = efm32
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CPU_FAM = efm32gg11b
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CPU_MODEL = efm32gg11b820f2048gl192
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_dac
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart periph_uart_modecfg
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FEATURES_PROVIDED += periph_usbdev
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include $(RIOTBOARD)/common/silabs/Makefile.features
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12
boards/slstk3701a/Makefile.include
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12
boards/slstk3701a/Makefile.include
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@ -0,0 +1,12 @@
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# set default port depending on operating system
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# setup serial terminal
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include $(RIOTMAKE)/tools/serial.inc.mk
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# setup JLink for flashing
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JLINK_PRE_FLASH = r
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# include board common
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include $(RIOTBOARD)/common/silabs/Makefile.include
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31
boards/slstk3701a/board.c
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31
boards/slstk3701a/board.c
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@ -0,0 +1,31 @@
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/*
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* Copyright (C) 2015-2020 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
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/**
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* @ingroup boards_slstk3701a
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* @{
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*
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* @file
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* @brief Board specific implementations SLSTK3701A board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Bas Stottelaar <basstottelaar@gmail.com>
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*
|
||||
* @}
|
||||
*/
|
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|
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#include "board.h"
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#include "board_common.h"
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|
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void board_init(void)
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{
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#ifndef RIOTBOOT
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/* perform common board initialization */
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board_common_init();
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#endif
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}
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288
boards/slstk3701a/doc.txt
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288
boards/slstk3701a/doc.txt
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@ -0,0 +1,288 @@
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/**
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* @defgroup boards_slstk3701a Silicon Labs SLSTK3701A starter kit
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* @ingroup boards
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* @brief Support for Silicon Labs SLSTK3701A starter kit
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## Overview
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Silicon Labs EFM32 Giant Gecko GG11 Starter Kit is equipped with the EFM32 microcontroller.
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It is specifically designed for low-power applications, having energy-saving
|
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peripherals, different energy modes and short wake-up times.
|
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|
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The starter kit is equipped with an Advanced Energy Monitor. This allows you to
|
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actively measure the power consumption of your hardware and code, in real-time.
|
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|
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## Hardware
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|
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### MCU
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|
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| MCU | EFM32GG11B820F2048GL192 |
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|-----------------|------------------------------------------------------|
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| Family | ARM Cortex-M4F |
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| Vendor | Silicon Labs |
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| Vendor Family | EFM32 Giant Gecko 11B |
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| RAM | 512.0 KiB |
|
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| Flash | 2048.0 KiB |
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| EEPROM | no |
|
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| Frequency | up to 50 MHz |
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| FPU | yes |
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| MPU | yes |
|
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| DMA | 24 channels |
|
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| Timers | 4 x 32-bit + 7 x 16-bit + 1 x 16-bit (low power) |
|
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| ADCs | 2 x 12-bit ADC (1 Msample/s) |
|
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| DACs | 2 x 12-bit VDAC (500 ksamples/s), 1 x IDAC |
|
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| I2Cs | 3 x |
|
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| SPIs | 4 x USART |
|
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| UARTs | 4 x USART, 1 x LEUART |
|
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| USB | 1 x Low Energy Full-Speed USB 2.0 |
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| Ethernet | Ethernet MAC 10/100 Mbps |
|
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| Vcc | 1.85 V - 3.8 V |
|
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| Datasheet | [Datasheet](https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf) |
|
||||
| Manual | [Manual](https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf) |
|
||||
| Board Manual | [Board Manual](https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf) |
|
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| Board Schematic | Can be downloaded using Silicon Labs' Simplicity Studio |
|
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|
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### Pinout
|
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|
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This is the pinout of the expansion header on the right side of the board.
|
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PIN 1 is the bottom-left contact when the header faces you horizontally.
|
||||
|
||||
| RIOT Peripheral | Name | PIN | PIN | Name | RIOT Peripheral |
|
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|-----------------|------|-----|-----|--------|-----------------|
|
||||
| | 3V3 | 20 | 19 | ID SDA | |
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||||
| | 5V | 18 | 17 | ID SCL | |
|
||||
| I2C_DEV(0):SDA | PC0 | 16 | 15 | PC1 | I2C_DEV(0):SCL |
|
||||
| UART_DEV(1):RX | PE9 | 14 | 13 | PB9 | |
|
||||
| UART_DEV(1):TX | PE8 | 12 | 11 | PB11 | DAC_LINE(0) |
|
||||
| | PE13 | 10 | 9 | PC5 | I2C_DEV(1):SCL |
|
||||
| SPI_DEV(0):CLK | PE12 | 8 | 7 | PC4 | I2C_DEV(1):SDA |
|
||||
| SPI_DEV(0):MISO | PE11 | 6 | 5 | PA13 | |
|
||||
| SPI_DEV(0):MOSI | PE10 | 4 | 3 | PA12 | |
|
||||
| | VMCU | 2 | 1 | GND | |
|
||||
|
||||
**Note**: not all starter kits by Silicon Labs share the same pinout!
|
||||
|
||||
**Note:** some pins are connected to the board controller, when enabled!
|
||||
|
||||
### Peripheral mapping
|
||||
|
||||
| Peripheral | Number | Hardware | Pins | Comments |
|
||||
|-------------|---------|------------|------------------|-------------------------------------|
|
||||
| ADC | 0 | ADC0:CH0 | | Internal temperature |
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||||
| ADC | 1 | ADC0:CH1 | | AVDD |
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||||
| DAC | 0 | DAC0:OUT0 | PB11 | AVVD as reference voltage |
|
||||
| I2C | 0 | I2C0 | SDA:PC0, SCL:PC1 | Normal speed |
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||||
| I2C | 1 | I2C1 | SDA:PC7, SCL:PC5 | Normal speed |
|
||||
| I2C | 2 | I2C2 | SDA:PI4, SCL:PI5 | Normal speed, Sensor I2C bus |
|
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| HWCRYPTO | - | - | | AES128/AES256, SHA1, SHA224/SHA256 |
|
||||
| HWRNG | - | TNRG0 | | True Random Number Generator (TRNG) |
|
||||
| RTT | - | RTCC | | 1 Hz interval, either RTT or RTC |
|
||||
| RTC | - | RTCC | | 1 Hz interval, either RTT or RTC |
|
||||
| SPI | 0 | USART0 | MOSI:PE10, MISO:PE11, CLK:PE12 | |
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||||
| Timer | 0 | WTIMER0 + WTIMER1 | | WTIMER0 is used as prescaler |
|
||||
| Timer | 1 | TIMER0 + TIMER1 | | TIMER0 is used as prescaler |
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| Timer | 2 | LETIMER0 | | |
|
||||
| UART | 0 | USART4 | RX:PH5, TX:PH4 | Default STDIO |
|
||||
| UART | 1 | USART5 | RX:PE9, TX:PE8 | |
|
||||
|
||||
### User interface
|
||||
|
||||
| Peripheral | Mapped to | Pin | Comments |
|
||||
|------------|-----------|-----------|------------|
|
||||
| Button | PB0_PIN | PC8 | |
|
||||
| | PB1_PIN | PC9 | |
|
||||
| LED | LED0R_PIN | PH10 | |
|
||||
| | LED0G_PIN | PH11 | |
|
||||
| | LED0B_PIN | PH12 | |
|
||||
| | LED1R_PIN | PH13 | |
|
||||
| | LED1G_PIN | PH14 | |
|
||||
| | LED1B_PIN | PH15 | |
|
||||
| | LED0_PIN | LED0R_PIN | |
|
||||
| | LED1_PIN | LED1R_PIN | |
|
||||
|
||||
## Implementation Status
|
||||
|
||||
| Device | ID | Supported | Comments |
|
||||
|------------------|------------|-----------|----------------------------------------------------|
|
||||
| MCU | EFM32GG11B | yes | Power modes supported |
|
||||
| Low-level driver | ADC | yes | |
|
||||
| | DAC | yes | VDAC, IDAC is not supported |
|
||||
| | Ethernet | no | |
|
||||
| | Flash | yes | |
|
||||
| | GPIO | yes | Interrupts are shared across pins (see ref manual) |
|
||||
| | HW Crypto | yes | |
|
||||
| | I2C | yes | |
|
||||
| | PWM | yes | |
|
||||
| | RTCC | yes | As RTT or RTC |
|
||||
| | SPI | yes | Only master mode |
|
||||
| | Timer | yes | |
|
||||
| | TRNG | yes | True Random Number Generator |
|
||||
| | UART | yes | USART is shared with SPI. LEUART baud rate limited |
|
||||
| | USB | yes | Device mode |
|
||||
|
||||
## Board configuration
|
||||
|
||||
### Board controller
|
||||
|
||||
The starter kit is equipped with a Board Controller. This controller provides a
|
||||
virtual serial port. The board controller is enabled via a GPIO pin.
|
||||
|
||||
By default, this pin is enabled. You can disable the board controller module by
|
||||
passing `DISABLE_MODULE=silabs_bc` to the `make` command.
|
||||
|
||||
**Note:** to use the virtual serial port, ensure you have the latest board
|
||||
controller firmware installed.
|
||||
|
||||
**Note:** the board controller *always* configures the virtual serial port at
|
||||
115200 baud with 8 bits, no parity and one stop bit. This also means that it
|
||||
expects data from the MCU with the same settings.
|
||||
|
||||
### Advanced Energy Monitor
|
||||
|
||||
This development kit has an Advanced Energy Monitor. It can be connected to the
|
||||
Simplicity Studio development software.
|
||||
|
||||
This development kit can measure energy consumption and correlate this with the
|
||||
code. It allows you to measure energy consumption on code-level.
|
||||
|
||||
The board controller is responsible for measuring energy consumption. For
|
||||
real-time code correlation, the CoreDebug peripheral will be configured to
|
||||
output MCU register data and interrupt data via the SWO port.
|
||||
|
||||
By default, this feature is enabled. It can be disabled by passing
|
||||
`DISABLE_MODULE=silabs_aem` to the `make` command.
|
||||
|
||||
Note that Simplicity Studio requires debug symbols to correlate code. RIOT-OS
|
||||
defaults to GDB debug symbols, but Simplicity Studio requires DWARF-2 debug
|
||||
symbols (`-gdwarf-2` for GCC).
|
||||
|
||||
### Clock selection
|
||||
|
||||
There are several clock sources that are available for the different
|
||||
peripherals. You are advised to read [AN0004.0]
|
||||
(https://www.silabs.com/documents/public/application-notes/an0004.0-efm32-cmu.pdf)
|
||||
to get familiar with the different clocks.
|
||||
|
||||
| Source | Internal | Speed | Comments |
|
||||
|--------|----------|------------|------------------------------------|
|
||||
| HFRCO | Yes | 19 MHz | Enabled during startup, changeable |
|
||||
| HFXO | No | 50 MHz | |
|
||||
| LFRCO | Yes | 32.768 kHz | |
|
||||
| LFXO | No | 32.768 kHz | |
|
||||
| ULFRCO | No | 1 kHz | Not very reliable as a time source |
|
||||
|
||||
The sources can be used to clock following branches:
|
||||
|
||||
| Branch | Sources | Comments |
|
||||
|--------|-------------------------|------------------------------|
|
||||
| HF | HFRCO, HFXO | Core, peripherals |
|
||||
| LFA | LFRCO, LFXO | Low-power timers |
|
||||
| LFB | LFRCO, LFXO, CORELEDIV2 | Low-power UART |
|
||||
| LFE | LFRCO, LFXO | Real-time Clock and Calendar |
|
||||
|
||||
CORELEDIV2 is a source that depends on the clock source that powers the core.
|
||||
It is divided by 2 or 4 to not exceed maximum clock frequencies (EMLIB takes
|
||||
care of this).
|
||||
|
||||
The frequencies mentioned in the tables above are specific for this starter
|
||||
kit.
|
||||
|
||||
It is important that the clock speeds are known to the code, for proper
|
||||
calculations of speeds and baud rates. If the HFXO or LFXO are different from
|
||||
the speeds above, ensure to pass `EFM32_HFXO_FREQ=freq_in_hz` and
|
||||
`EFM32_LFXO_FREQ=freq_in_hz` to your compiler.
|
||||
|
||||
You can override the branch's clock source by adding `CLOCK_LFA=source` to your
|
||||
compiler defines, e.g. `CLOCK_LFA=cmuSelect_LFRCO`.
|
||||
|
||||
### Low-power peripherals
|
||||
|
||||
The low-power UART is capable of providing an UART peripheral using a low-speed
|
||||
clock. When the LFB clock source is the LFRCO or LFXO, it can still be used in
|
||||
EM2. However, this limits the baud rate to 9600 baud. If a higher baud rate is
|
||||
desired, set the clock source to CORELEDIV2.
|
||||
|
||||
**Note:** peripheral mappings in your board definitions will not be affected by
|
||||
this setting. Ensure you do not refer to any low-power peripherals.
|
||||
|
||||
### RTC or RTT
|
||||
|
||||
RIOT-OS has support for *Real-Time Tickers* and *Real-Time Clocks*.
|
||||
|
||||
However, this board MCU family has support for a 32-bit *Real-Time Clock and
|
||||
Calendar*, which can be configured in ticker mode **or** calendar mode.
|
||||
Therefore, only one of both peripherals can be enabled at the same time.
|
||||
|
||||
Configured at 1 Hz interval, the RTCC will overflow each 136 years.
|
||||
|
||||
### Hardware crypto
|
||||
This MCU is equipped with a hardware-accelerated crypto peripheral that can
|
||||
speed up AES128, AES256, SHA1, SHA256 and several other cryptographic
|
||||
computations.
|
||||
|
||||
A peripheral driver interface is proposed, but not yet implemented.
|
||||
|
||||
### Usage of EMLIB
|
||||
|
||||
This port makes uses of EMLIB by Silicon Labs to abstract peripheral registers.
|
||||
While some overhead is to be expected, it ensures proper setup of devices,
|
||||
provides chip errata and simplifies development. The exact overhead depends on
|
||||
the application and peripheral usage, but the largest overhead is expected
|
||||
during peripheral setup. A lot of read/write/get/set methods are implemented as
|
||||
inline methods or macros (which have no overhead).
|
||||
|
||||
Another advantage of EMLIB are the included assertions. These assertions ensure
|
||||
that peripherals are used properly. To enable this, pass `DEBUG_EFM` to your
|
||||
compiler.
|
||||
|
||||
### Pin locations
|
||||
|
||||
The EFM32 platform supports peripherals to be mapped to different pins
|
||||
(predefined locations). The definitions in `periph_conf.h` mostly consist of a
|
||||
location number and the actual pins. The actual pins are required to configure
|
||||
the pins via GPIO driver, while the location is used to map the peripheral to
|
||||
these pins.
|
||||
|
||||
In other words, these definitions must match. Refer to the data sheet for more
|
||||
information.
|
||||
|
||||
This MCU has extended pin mapping support. Each pin of a peripheral can be
|
||||
connected separately to one of the predefined pins for that peripheral.
|
||||
|
||||
## Flashing the device
|
||||
|
||||
The board provides a on-board SEGGER J-Link debugger through the micro USB
|
||||
board so that flashing and debugging is very easy.
|
||||
|
||||
Flashing is supported by RIOT-OS using the command below:
|
||||
|
||||
```
|
||||
make flash
|
||||
```
|
||||
|
||||
To run the GDB debugger, use the command:
|
||||
|
||||
```
|
||||
make debug
|
||||
```
|
||||
|
||||
Or, to connect with your own debugger:
|
||||
|
||||
```
|
||||
make debug-server
|
||||
```
|
||||
|
||||
Some boards have (limited) support for emulation, which can be started with:
|
||||
|
||||
```
|
||||
make emulate
|
||||
```
|
||||
|
||||
## Supported Toolchains
|
||||
For using the Silicon Labs SLSTK3701A starter kit we strongly recommend
|
||||
the usage of the [GNU Tools for ARM Embedded Processors](https://developer.arm.com/open-source/gnu-toolchain/gnu-rm)
|
||||
toolchain.
|
||||
|
||||
## License information
|
||||
* Silicon Labs' EMLIB: zlib-style license (permits distribution of source).
|
||||
*/
|
||||
138
boards/slstk3701a/include/board.h
Normal file
138
boards/slstk3701a/include/board.h
Normal file
@ -0,0 +1,138 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2020 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_slstk3701a
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Board specific definitions for the SLSTK3701A starter kit
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Bas Stottelaar <basstottelaar@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
#include "cpu.h"
|
||||
#include "periph_conf.h"
|
||||
#include "periph/gpio.h"
|
||||
#include "periph/spi.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Xtimer configuration
|
||||
*
|
||||
* The timer runs at 1000 kHz to increase accuracy, or at 32.768 kHz if
|
||||
* LETIMER is used.
|
||||
* @{
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_EFM32_XTIMER_USE_LETIMER)
|
||||
#define XTIMER_DEV (TIMER_DEV(2))
|
||||
#define XTIMER_HZ (32768UL)
|
||||
#define XTIMER_WIDTH (16)
|
||||
#else
|
||||
#define XTIMER_DEV (TIMER_DEV(0))
|
||||
#define XTIMER_HZ (1000000UL)
|
||||
#define XTIMER_WIDTH (32)
|
||||
#endif
|
||||
#define XTIMER_CHAN (0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Board controller configuration
|
||||
*
|
||||
* Define the GPIO pin to enable the BC, to allow serial communication
|
||||
* via the USB port.
|
||||
* @{
|
||||
*/
|
||||
#define BC_PIN GPIO_PIN(PE, 1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Push button pin definitions
|
||||
* @{
|
||||
*/
|
||||
#define PB0_PIN GPIO_PIN(PC, 8)
|
||||
#define PB1_PIN GPIO_PIN(PC, 9)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name LED pin definitions
|
||||
* @{
|
||||
*/
|
||||
#define LED0R_PIN GPIO_PIN(PH, 10)
|
||||
#define LED0G_PIN GPIO_PIN(PH, 11)
|
||||
#define LED0B_PIN GPIO_PIN(PH, 12)
|
||||
#define LED1R_PIN GPIO_PIN(PH, 13)
|
||||
#define LED1G_PIN GPIO_PIN(PH, 14)
|
||||
#define LED1B_PIN GPIO_PIN(PH, 15)
|
||||
#define LED0_PIN LED0R_PIN
|
||||
#define LED1_PIN LED1R_PIN
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Macros for controlling the on-board LEDs
|
||||
* @{
|
||||
*/
|
||||
#define LED0_ON gpio_set(LED0_PIN)
|
||||
#define LED0_OFF gpio_clear(LED0_PIN)
|
||||
#define LED0_TOGGLE gpio_toggle(LED0_PIN)
|
||||
#define LED1_ON gpio_set(LED1_PIN)
|
||||
#define LED1_OFF gpio_clear(LED1_PIN)
|
||||
#define LED1_TOGGLE gpio_toggle(LED1_PIN)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Display configuration
|
||||
*
|
||||
* Connection to the on-board Sharp Memory LCD (LS013B7DH03).
|
||||
* @{
|
||||
*/
|
||||
#define DISP_SPI SPI_DEV(0)
|
||||
#define DISP_COM_PIN GPIO_PIN(PA, 11)
|
||||
#define DISP_CS_PIN GPIO_PIN(PC, 14)
|
||||
#define DISP_EN_PIN GPIO_PIN(PA, 9)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Temperature sensor configuration
|
||||
*
|
||||
* Connection to the on-board temperature/humidity sensor (Si7021).
|
||||
* @{
|
||||
*/
|
||||
#define SI7021_I2C I2C_DEV(2)
|
||||
#define SI7021_EN_PIN GPIO_PIN(PB, 3)
|
||||
|
||||
#define SI70XX_PARAM_I2C_DEV SI7021_I2C
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Core temperature sensor configuration
|
||||
*
|
||||
* Connection to the on-chip temperature sensor.
|
||||
* @{
|
||||
*/
|
||||
#define CORETEMP_ADC ADC_LINE(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Initialize the board (GPIO, sensors, clocks).
|
||||
*/
|
||||
void board_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BOARD_H */
|
||||
/** @} */
|
||||
63
boards/slstk3701a/include/gpio_params.h
Normal file
63
boards/slstk3701a/include/gpio_params.h
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (C) 2016-2020 Bas Stottelaar <basstottelaar@gmail.com>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_slstk3701a
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Board specific configuration of direct mapped GPIOs
|
||||
*
|
||||
* @author Bas Stottelaar <basstottelaar@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef GPIO_PARAMS_H
|
||||
#define GPIO_PARAMS_H
|
||||
|
||||
#include "board.h"
|
||||
#include "saul/periph.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO pin configuration
|
||||
*/
|
||||
static const saul_gpio_params_t saul_gpio_params[] =
|
||||
{
|
||||
{
|
||||
.name = "LED 0",
|
||||
.pin = LED0_PIN,
|
||||
.mode = GPIO_OUT
|
||||
},
|
||||
{
|
||||
.name = "LED 1",
|
||||
.pin = LED1_PIN,
|
||||
.mode = GPIO_OUT
|
||||
},
|
||||
{
|
||||
.name = "Button 1",
|
||||
.pin = PB0_PIN,
|
||||
.mode = GPIO_IN_PU,
|
||||
.flags = SAUL_GPIO_INVERTED
|
||||
},
|
||||
{
|
||||
.name = "Button 2",
|
||||
.pin = PB1_PIN,
|
||||
.mode = GPIO_IN_PU,
|
||||
.flags = SAUL_GPIO_INVERTED
|
||||
}
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GPIO_PARAMS_H */
|
||||
/** @} */
|
||||
265
boards/slstk3701a/include/periph_conf.h
Normal file
265
boards/slstk3701a/include/periph_conf.h
Normal file
@ -0,0 +1,265 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2020 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_slstk3701a
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configuration of CPU peripherals for the SLSTK3701A starter kit
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Bas Stottelaar <basstottelaar@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CONF_H
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "cpu.h"
|
||||
#include "periph_cpu.h"
|
||||
#include "em_cmu.h"
|
||||
#include "usbdev_cfg_otg_fs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock configuration
|
||||
* @{
|
||||
*/
|
||||
#ifndef CLOCK_HF
|
||||
#define CLOCK_HF cmuSelect_HFXO
|
||||
#endif
|
||||
#ifndef CLOCK_CORE_DIV
|
||||
#define CLOCK_CORE_DIV cmuClkDiv_1
|
||||
#endif
|
||||
#ifndef CLOCK_LFA
|
||||
#define CLOCK_LFA cmuSelect_LFXO
|
||||
#endif
|
||||
#ifndef CLOCK_LFB
|
||||
#define CLOCK_LFB cmuSelect_LFXO
|
||||
#endif
|
||||
#ifndef CLOCK_LFE
|
||||
#define CLOCK_LFE cmuSelect_LFXO
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
* @{
|
||||
*/
|
||||
static const adc_conf_t adc_config[] = {
|
||||
{
|
||||
.dev = ADC0,
|
||||
.cmu = cmuClock_ADC0,
|
||||
}
|
||||
};
|
||||
|
||||
static const adc_chan_conf_t adc_channel_config[] = {
|
||||
{
|
||||
.dev = 0,
|
||||
.input = adcPosSelTEMP,
|
||||
.reference = adcRef1V25,
|
||||
.acq_time = adcAcqTime8
|
||||
},
|
||||
{
|
||||
.dev = 0,
|
||||
.input = adcPosSelAVDD,
|
||||
.reference = adcRef5V,
|
||||
.acq_time = adcAcqTime8
|
||||
}
|
||||
};
|
||||
|
||||
#define ADC_DEV_NUMOF ARRAY_SIZE(adc_config)
|
||||
#define ADC_NUMOF ARRAY_SIZE(adc_channel_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name DAC configuration
|
||||
* @{
|
||||
*/
|
||||
static const dac_conf_t dac_config[] = {
|
||||
{
|
||||
.dev = VDAC0,
|
||||
.ref = vdacRefAvdd,
|
||||
.cmu = cmuClock_VDAC0,
|
||||
},
|
||||
};
|
||||
|
||||
static const dac_chan_conf_t dac_channel_config[] = {
|
||||
{
|
||||
.dev = 0,
|
||||
.index = 0,
|
||||
},
|
||||
};
|
||||
|
||||
#define DAC_DEV_NUMOF ARRAY_SIZE(dac_config)
|
||||
#define DAC_NUMOF ARRAY_SIZE(dac_channel_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C0,
|
||||
.sda_pin = GPIO_PIN(PC, 0),
|
||||
.scl_pin = GPIO_PIN(PC, 1),
|
||||
.loc = I2C_ROUTELOC0_SDALOC_LOC4 |
|
||||
I2C_ROUTELOC0_SCLLOC_LOC4,
|
||||
.cmu = cmuClock_I2C0,
|
||||
.irq = I2C0_IRQn,
|
||||
.speed = I2C_SPEED_NORMAL
|
||||
},
|
||||
{
|
||||
.dev = I2C1,
|
||||
.sda_pin = GPIO_PIN(PC, 7),
|
||||
.scl_pin = GPIO_PIN(PC, 5),
|
||||
.loc = I2C_ROUTELOC0_SDALOC_LOC0 |
|
||||
I2C_ROUTELOC0_SCLLOC_LOC0,
|
||||
.cmu = cmuClock_I2C1,
|
||||
.irq = I2C1_IRQn,
|
||||
.speed = I2C_SPEED_NORMAL
|
||||
},
|
||||
{
|
||||
.dev = I2C2,
|
||||
.sda_pin = GPIO_PIN(PI, 4),
|
||||
.scl_pin = GPIO_PIN(PI, 5),
|
||||
.loc = I2C_ROUTELOC0_SDALOC_LOC7 |
|
||||
I2C_ROUTELOC0_SCLLOC_LOC7,
|
||||
.cmu = cmuClock_I2C2,
|
||||
.irq = I2C2_IRQn,
|
||||
.speed = I2C_SPEED_NORMAL
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
|
||||
#define I2C_0_ISR isr_i2c0
|
||||
#define I2C_1_ISR isr_i2c1
|
||||
#define I2C_2_ISR isr_i2c2
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RTT configuration
|
||||
* @{
|
||||
*/
|
||||
#ifndef RTT_FREQUENCY
|
||||
#define RTT_FREQUENCY (1U)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI configuration
|
||||
* @{
|
||||
*/
|
||||
static const spi_dev_t spi_config[] = {
|
||||
{
|
||||
.dev = USART0,
|
||||
.mosi_pin = GPIO_PIN(PE, 10),
|
||||
.miso_pin = GPIO_PIN(PE, 11),
|
||||
.clk_pin = GPIO_PIN(PE, 12),
|
||||
.loc = USART_ROUTELOC0_TXLOC_LOC0 |
|
||||
USART_ROUTELOC0_RXLOC_LOC0 |
|
||||
USART_ROUTELOC0_CLKLOC_LOC0,
|
||||
.cmu = cmuClock_USART0,
|
||||
.irq = USART0_RX_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define SPI_NUMOF ARRAY_SIZE(spi_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Timer configuration
|
||||
*
|
||||
* The implementation uses two timers in cascade mode.
|
||||
* @{
|
||||
*/
|
||||
static const timer_conf_t timer_config[] = {
|
||||
{
|
||||
.prescaler = {
|
||||
.dev = WTIMER0,
|
||||
.cmu = cmuClock_WTIMER0
|
||||
},
|
||||
.timer = {
|
||||
.dev = WTIMER1,
|
||||
.cmu = cmuClock_WTIMER1
|
||||
},
|
||||
.irq = WTIMER1_IRQn,
|
||||
.channel_numof = 3
|
||||
},
|
||||
{
|
||||
.prescaler = {
|
||||
.dev = TIMER0,
|
||||
.cmu = cmuClock_TIMER0
|
||||
},
|
||||
.timer = {
|
||||
.dev = TIMER1,
|
||||
.cmu = cmuClock_TIMER1
|
||||
},
|
||||
.irq = TIMER1_IRQn,
|
||||
.channel_numof = 3
|
||||
},
|
||||
{
|
||||
.prescaler = {
|
||||
.dev = NULL,
|
||||
.cmu = cmuClock_LETIMER0
|
||||
},
|
||||
.timer = {
|
||||
.dev = LETIMER0,
|
||||
.cmu = cmuClock_LETIMER0
|
||||
},
|
||||
.irq = LETIMER0_IRQn,
|
||||
.channel_numof = 2
|
||||
}
|
||||
};
|
||||
|
||||
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
|
||||
#define TIMER_0_ISR isr_wtimer1
|
||||
#define TIMER_1_ISR isr_timer1
|
||||
#define TIMER_2_ISR isr_letimer0
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name UART configuration
|
||||
* @{
|
||||
*/
|
||||
static const uart_conf_t uart_config[] = {
|
||||
{
|
||||
.dev = USART4,
|
||||
.rx_pin = GPIO_PIN(PH, 5),
|
||||
.tx_pin = GPIO_PIN(PH, 4),
|
||||
.loc = USART_ROUTELOC0_RXLOC_LOC4 |
|
||||
USART_ROUTELOC0_TXLOC_LOC4,
|
||||
.cmu = cmuClock_USART4,
|
||||
.irq = USART4_RX_IRQn,
|
||||
},
|
||||
{
|
||||
.dev = USART5,
|
||||
.rx_pin = GPIO_PIN(PE, 9),
|
||||
.tx_pin = GPIO_PIN(PE, 8),
|
||||
.loc = USART_ROUTELOC0_RXLOC_LOC4 |
|
||||
USART_ROUTELOC0_TXLOC_LOC4,
|
||||
.cmu = cmuClock_USART5,
|
||||
.irq = USART5_RX_IRQn,
|
||||
}
|
||||
};
|
||||
|
||||
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
||||
#define UART_0_ISR_RX isr_usart4_rx
|
||||
#define UART_1_ISR_RX isr_usart5_rx
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
@ -7,6 +7,9 @@ DIRS += $(RIOTCPU)/cortexm_common
|
||||
ifneq (,$(filter cpu_efm32gg,$(USEMODULE)))
|
||||
DIRS += families/efm32gg
|
||||
endif
|
||||
ifneq (,$(filter cpu_efm32gg11b,$(USEMODULE)))
|
||||
DIRS += families/efm32gg11b
|
||||
endif
|
||||
ifneq (,$(filter cpu_efm32gg12b,$(USEMODULE)))
|
||||
DIRS += families/efm32gg12b
|
||||
endif
|
||||
|
||||
328
cpu/efm32/families/efm32gg11b/Kconfig
Normal file
328
cpu/efm32/families/efm32gg11b/Kconfig
Normal file
@ -0,0 +1,328 @@
|
||||
# Copyright (c) 2020 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
|
||||
config CPU_FAM_EFM32GG11B
|
||||
bool
|
||||
select CPU_CORE_CORTEX_M4F
|
||||
select CPU_COMMON_EFM32
|
||||
select CPU_EFM32_SERIES1
|
||||
select HAS_PERIPH_HWRNG
|
||||
select HAS_CORTEXM_MPU
|
||||
|
||||
config MODULE_CPU_EFM32GG11B
|
||||
bool
|
||||
depends on CPU_FAM_EFM32GG11B
|
||||
depends on TEST_KCONFIG
|
||||
default y
|
||||
help
|
||||
EFM32GG11B family-specific code.
|
||||
|
||||
## CPU Models
|
||||
config CPU_MODEL_EFM32GG11B510F2048IL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B120F2048GM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B120F2048IQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048GL152
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B520F2048IM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B520F2048GQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024GL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048IL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B520F2048GL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024GQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024IM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048GQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048GQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048IM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048IL112
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B510F2048IQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B310F2048GL112
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024GL152
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B310F2048GQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B510F2048GQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B510F2048IM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048GQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048GL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048IM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048IQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024GQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B110F2048IQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B110F2048GM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B520F2048GQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048IL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024IQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048GQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048GL192
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B320F2048GL112
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B520F2048IQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B110F2048GQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B110F2048IM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B320F2048GQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048GL112
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B510F2048GQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048IQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048GM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B510F2048IQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B510F2048GM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024IL152
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048GL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024IL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B520F2048GM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B520F2048IQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B520F2048IL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024GL192
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B120F2048IM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B120F2048GQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048IQ100
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048IQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B420F2048GM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B510F2048GL120
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024IQ64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B840F1024GM64
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL_EFM32GG11B820F2048IL152
|
||||
bool
|
||||
select CPU_FAM_EFM32GG11B
|
||||
|
||||
## Common CPU symbols
|
||||
config CPU_FAM
|
||||
default "efm32gg11b" if CPU_FAM_EFM32GG11B
|
||||
|
||||
config CPU_MODEL
|
||||
default "efm32gg11b510f2048il120" if CPU_MODEL_EFM32GG11B510F2048IL120
|
||||
default "efm32gg11b120f2048gm64" if CPU_MODEL_EFM32GG11B120F2048GM64
|
||||
default "efm32gg11b120f2048iq64" if CPU_MODEL_EFM32GG11B120F2048IQ64
|
||||
default "efm32gg11b820f2048gl152" if CPU_MODEL_EFM32GG11B820F2048GL152
|
||||
default "efm32gg11b520f2048im64" if CPU_MODEL_EFM32GG11B520F2048IM64
|
||||
default "efm32gg11b520f2048gq64" if CPU_MODEL_EFM32GG11B520F2048GQ64
|
||||
default "efm32gg11b840f1024gl120" if CPU_MODEL_EFM32GG11B840F1024GL120
|
||||
default "efm32gg11b420f2048il120" if CPU_MODEL_EFM32GG11B420F2048IL120
|
||||
default "efm32gg11b520f2048gl120" if CPU_MODEL_EFM32GG11B520F2048GL120
|
||||
default "efm32gg11b840f1024gq64" if CPU_MODEL_EFM32GG11B840F1024GQ64
|
||||
default "efm32gg11b840f1024im64" if CPU_MODEL_EFM32GG11B840F1024IM64
|
||||
default "efm32gg11b820f2048gq100" if CPU_MODEL_EFM32GG11B820F2048GQ100
|
||||
default "efm32gg11b420f2048gq64" if CPU_MODEL_EFM32GG11B420F2048GQ64
|
||||
default "efm32gg11b420f2048im64" if CPU_MODEL_EFM32GG11B420F2048IM64
|
||||
default "efm32gg11b420f2048il112" if CPU_MODEL_EFM32GG11B420F2048IL112
|
||||
default "efm32gg11b510f2048iq100" if CPU_MODEL_EFM32GG11B510F2048IQ100
|
||||
default "efm32gg11b310f2048gl112" if CPU_MODEL_EFM32GG11B310F2048GL112
|
||||
default "efm32gg11b840f1024gl152" if CPU_MODEL_EFM32GG11B840F1024GL152
|
||||
default "efm32gg11b310f2048gq100" if CPU_MODEL_EFM32GG11B310F2048GQ100
|
||||
default "efm32gg11b510f2048gq64" if CPU_MODEL_EFM32GG11B510F2048GQ64
|
||||
default "efm32gg11b510f2048im64" if CPU_MODEL_EFM32GG11B510F2048IM64
|
||||
default "efm32gg11b820f2048gq64" if CPU_MODEL_EFM32GG11B820F2048GQ64
|
||||
default "efm32gg11b820f2048gl120" if CPU_MODEL_EFM32GG11B820F2048GL120
|
||||
default "efm32gg11b820f2048im64" if CPU_MODEL_EFM32GG11B820F2048IM64
|
||||
default "efm32gg11b420f2048iq100" if CPU_MODEL_EFM32GG11B420F2048IQ100
|
||||
default "efm32gg11b840f1024gq100" if CPU_MODEL_EFM32GG11B840F1024GQ100
|
||||
default "efm32gg11b110f2048iq64" if CPU_MODEL_EFM32GG11B110F2048IQ64
|
||||
default "efm32gg11b110f2048gm64" if CPU_MODEL_EFM32GG11B110F2048GM64
|
||||
default "efm32gg11b520f2048gq100" if CPU_MODEL_EFM32GG11B520F2048GQ100
|
||||
default "efm32gg11b820f2048il120" if CPU_MODEL_EFM32GG11B820F2048IL120
|
||||
default "efm32gg11b840f1024iq100" if CPU_MODEL_EFM32GG11B840F1024IQ100
|
||||
default "efm32gg11b420f2048gq100" if CPU_MODEL_EFM32GG11B420F2048GQ100
|
||||
default "efm32gg11b820f2048gl192" if CPU_MODEL_EFM32GG11B820F2048GL192
|
||||
default "efm32gg11b320f2048gl112" if CPU_MODEL_EFM32GG11B320F2048GL112
|
||||
default "efm32gg11b520f2048iq100" if CPU_MODEL_EFM32GG11B520F2048IQ100
|
||||
default "efm32gg11b110f2048gq64" if CPU_MODEL_EFM32GG11B110F2048GQ64
|
||||
default "efm32gg11b110f2048im64" if CPU_MODEL_EFM32GG11B110F2048IM64
|
||||
default "efm32gg11b320f2048gq100" if CPU_MODEL_EFM32GG11B320F2048GQ100
|
||||
default "efm32gg11b420f2048gl112" if CPU_MODEL_EFM32GG11B420F2048GL112
|
||||
default "efm32gg11b510f2048gq100" if CPU_MODEL_EFM32GG11B510F2048GQ100
|
||||
default "efm32gg11b820f2048iq64" if CPU_MODEL_EFM32GG11B820F2048IQ64
|
||||
default "efm32gg11b820f2048gm64" if CPU_MODEL_EFM32GG11B820F2048GM64
|
||||
default "efm32gg11b510f2048iq64" if CPU_MODEL_EFM32GG11B510F2048IQ64
|
||||
default "efm32gg11b510f2048gm64" if CPU_MODEL_EFM32GG11B510F2048GM64
|
||||
default "efm32gg11b840f1024il152" if CPU_MODEL_EFM32GG11B840F1024IL152
|
||||
default "efm32gg11b420f2048gl120" if CPU_MODEL_EFM32GG11B420F2048GL120
|
||||
default "efm32gg11b840f1024il120" if CPU_MODEL_EFM32GG11B840F1024IL120
|
||||
default "efm32gg11b520f2048gm64" if CPU_MODEL_EFM32GG11B520F2048GM64
|
||||
default "efm32gg11b520f2048iq64" if CPU_MODEL_EFM32GG11B520F2048IQ64
|
||||
default "efm32gg11b520f2048il120" if CPU_MODEL_EFM32GG11B520F2048IL120
|
||||
default "efm32gg11b840f1024gl192" if CPU_MODEL_EFM32GG11B840F1024GL192
|
||||
default "efm32gg11b120f2048im64" if CPU_MODEL_EFM32GG11B120F2048IM64
|
||||
default "efm32gg11b120f2048gq64" if CPU_MODEL_EFM32GG11B120F2048GQ64
|
||||
default "efm32gg11b820f2048iq100" if CPU_MODEL_EFM32GG11B820F2048IQ100
|
||||
default "efm32gg11b420f2048iq64" if CPU_MODEL_EFM32GG11B420F2048IQ64
|
||||
default "efm32gg11b420f2048gm64" if CPU_MODEL_EFM32GG11B420F2048GM64
|
||||
default "efm32gg11b510f2048gl120" if CPU_MODEL_EFM32GG11B510F2048GL120
|
||||
default "efm32gg11b840f1024iq64" if CPU_MODEL_EFM32GG11B840F1024IQ64
|
||||
default "efm32gg11b840f1024gm64" if CPU_MODEL_EFM32GG11B840F1024GM64
|
||||
default "efm32gg11b820f2048il152" if CPU_MODEL_EFM32GG11B820F2048IL152
|
||||
6
cpu/efm32/families/efm32gg11b/Makefile
Normal file
6
cpu/efm32/families/efm32gg11b/Makefile
Normal file
@ -0,0 +1,6 @@
|
||||
MODULE = cpu_efm32gg11b
|
||||
|
||||
# (file triggers compiler bug. see #5775)
|
||||
SRC_NOLTO += vectors.c
|
||||
|
||||
include $(RIOTBASE)/Makefile.base
|
||||
7
cpu/efm32/families/efm32gg11b/Makefile.include
Normal file
7
cpu/efm32/families/efm32gg11b/Makefile.include
Normal file
@ -0,0 +1,7 @@
|
||||
# Find the header file that should exist if the CPU is supported. Only headers
|
||||
# for supported boards are included, but to support another CPU, it should be
|
||||
# as easy as adding the header file only.
|
||||
EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efm32gg11b/include/vendor/$(CPU_MODEL).h)
|
||||
|
||||
# include vendor device headers
|
||||
INCLUDES += -I$(RIOTCPU)/efm32/families/efm32gg11b/include/vendor
|
||||
65
cpu/efm32/families/efm32gg11b/efm32-info.mk
Normal file
65
cpu/efm32/families/efm32gg11b/efm32-info.mk
Normal file
@ -0,0 +1,65 @@
|
||||
# This file is automatically generated, and should not be changed. There is
|
||||
# probably little reason to edit this file anyway, since it should already
|
||||
# contain all information for the EFM32GG11B family of CPUs.
|
||||
|
||||
# Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio?
|
||||
EFM32_INFO_efm32gg11b510f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b120f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b120f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gl152 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gq64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024im64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048il112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b310f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gl152 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b310f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b110f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b110f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gl192 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b320f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b110f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b110f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b320f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024il152 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gl192 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b120f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b120f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024iq64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gm64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048il152 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gm64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gq64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048im64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048iq64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gm64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gq64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048im64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048iq64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gl112.h
vendored
Normal file
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gl112.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gq100.h
vendored
Normal file
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gl112.h
vendored
Normal file
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gl112.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gq100.h
vendored
Normal file
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl112.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl112.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl120.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gm64.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq100.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq64.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il112.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il112.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il120.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048im64.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq100.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq64.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gl120.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gm64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq100.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048il120.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048im64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq100.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gl120.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gm64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq100.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048il120.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048im64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq100.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl120.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl152.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl152.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl192.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl192.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gm64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq100.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il120.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il152.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il152.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048im64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq100.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl120.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl152.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl152.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl192.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl192.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gm64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq100.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il120.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il152.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il152.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024im64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024im64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq100.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq100.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_acmp.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_acmp.h
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2435
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_adc.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_adc.h
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403
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_pins.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_pins.h
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@ -0,0 +1,403 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_AF_PINS register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_Alternate_Function Alternate Function
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_AF_Pins Alternate Function Pins
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */
|
||||
#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */
|
||||
#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */
|
||||
#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */
|
||||
#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */
|
||||
#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */
|
||||
#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */
|
||||
#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */
|
||||
#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */
|
||||
#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */
|
||||
#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */
|
||||
#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */
|
||||
#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */
|
||||
#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */
|
||||
#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */
|
||||
#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */
|
||||
#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */
|
||||
#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */
|
||||
#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */
|
||||
#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */
|
||||
#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */
|
||||
#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */
|
||||
#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */
|
||||
#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */
|
||||
#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */
|
||||
#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */
|
||||
#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */
|
||||
#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */
|
||||
#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */
|
||||
#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */
|
||||
#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */
|
||||
#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */
|
||||
#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */
|
||||
#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */
|
||||
#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */
|
||||
#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */
|
||||
#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */
|
||||
#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */
|
||||
#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */
|
||||
#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */
|
||||
#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */
|
||||
#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */
|
||||
#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */
|
||||
#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */
|
||||
#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */
|
||||
#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */
|
||||
#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */
|
||||
#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */
|
||||
#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */
|
||||
#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */
|
||||
#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */
|
||||
#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */
|
||||
#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */
|
||||
#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */
|
||||
#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */
|
||||
#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */
|
||||
#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */
|
||||
#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */
|
||||
#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */
|
||||
#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */
|
||||
#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */
|
||||
#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */
|
||||
#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */
|
||||
#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */
|
||||
#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */
|
||||
#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */
|
||||
#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */
|
||||
#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */
|
||||
#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */
|
||||
#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */
|
||||
#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */
|
||||
#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */
|
||||
#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */
|
||||
#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */
|
||||
#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */
|
||||
#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */
|
||||
#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */
|
||||
#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */
|
||||
#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */
|
||||
#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */
|
||||
#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */
|
||||
#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */
|
||||
#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */
|
||||
#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */
|
||||
#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */
|
||||
#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */
|
||||
#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */
|
||||
#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */
|
||||
#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */
|
||||
#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */
|
||||
#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */
|
||||
#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */
|
||||
#define AF_ETH_MIITXCLK_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : -1) /**< Pin number for AF_ETH_MIITXCLK location number i */
|
||||
#define AF_ETH_MIITXD3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : -1) /**< Pin number for AF_ETH_MIITXD3 location number i */
|
||||
#define AF_ETH_MIITXD2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : -1) /**< Pin number for AF_ETH_MIITXD2 location number i */
|
||||
#define AF_ETH_MIITXD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : -1) /**< Pin number for AF_ETH_MIITXD1 location number i */
|
||||
#define AF_ETH_MIITXD0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Pin number for AF_ETH_MIITXD0 location number i */
|
||||
#define AF_ETH_MIITXEN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : -1) /**< Pin number for AF_ETH_MIITXEN location number i */
|
||||
#define AF_ETH_MIITXER_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : -1) /**< Pin number for AF_ETH_MIITXER location number i */
|
||||
#define AF_ETH_MIIRXCLK_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 12 : -1) /**< Pin number for AF_ETH_MIIRXCLK location number i */
|
||||
#define AF_ETH_MIIRXD3_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 11 : -1) /**< Pin number for AF_ETH_MIIRXD3 location number i */
|
||||
#define AF_ETH_MIIRXD2_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 10 : -1) /**< Pin number for AF_ETH_MIIRXD2 location number i */
|
||||
#define AF_ETH_MIIRXD1_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 9 : -1) /**< Pin number for AF_ETH_MIIRXD1 location number i */
|
||||
#define AF_ETH_MIIRXD0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 11 : (i) == 2 ? 9 : -1) /**< Pin number for AF_ETH_MIIRXD0 location number i */
|
||||
#define AF_ETH_MIIRXDV_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 8 : -1) /**< Pin number for AF_ETH_MIIRXDV location number i */
|
||||
#define AF_ETH_MIIRXER_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 7 : -1) /**< Pin number for AF_ETH_MIIRXER location number i */
|
||||
#define AF_ETH_MIICRS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 3 : -1) /**< Pin number for AF_ETH_MIICRS location number i */
|
||||
#define AF_ETH_MIICOL_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 4 : -1) /**< Pin number for AF_ETH_MIICOL location number i */
|
||||
#define AF_ETH_MDIO_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 0 : (i) == 3 ? 15 : -1) /**< Pin number for AF_ETH_MDIO location number i */
|
||||
#define AF_ETH_MDC_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 1 : (i) == 3 ? 6 : -1) /**< Pin number for AF_ETH_MDC location number i */
|
||||
#define AF_ETH_TSUEXTCLK_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 2 : (i) == 3 ? 8 : -1) /**< Pin number for AF_ETH_TSUEXTCLK location number i */
|
||||
#define AF_ETH_TSUTMRTOG_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 9 : -1) /**< Pin number for AF_ETH_TSUTMRTOG location number i */
|
||||
#define AF_ETH_RMIITXD1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : -1) /**< Pin number for AF_ETH_RMIITXD1 location number i */
|
||||
#define AF_ETH_RMIITXD0_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : -1) /**< Pin number for AF_ETH_RMIITXD0 location number i */
|
||||
#define AF_ETH_RMIITXEN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : -1) /**< Pin number for AF_ETH_RMIITXEN location number i */
|
||||
#define AF_ETH_RMIIRXD1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : -1) /**< Pin number for AF_ETH_RMIIRXD1 location number i */
|
||||
#define AF_ETH_RMIIRXD0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 9 : -1) /**< Pin number for AF_ETH_RMIIRXD0 location number i */
|
||||
#define AF_ETH_RMIIREFCLK_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 10 : -1) /**< Pin number for AF_ETH_RMIIREFCLK location number i */
|
||||
#define AF_ETH_RMIICRSDV_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : -1) /**< Pin number for AF_ETH_RMIICRSDV location number i */
|
||||
#define AF_ETH_RMIIRXER_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : -1) /**< Pin number for AF_ETH_RMIIRXER location number i */
|
||||
#define AF_SDIO_CLK_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : -1) /**< Pin number for AF_SDIO_CLK location number i */
|
||||
#define AF_SDIO_CMD_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : -1) /**< Pin number for AF_SDIO_CMD location number i */
|
||||
#define AF_SDIO_DAT0_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : -1) /**< Pin number for AF_SDIO_DAT0 location number i */
|
||||
#define AF_SDIO_DAT1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 1 : -1) /**< Pin number for AF_SDIO_DAT1 location number i */
|
||||
#define AF_SDIO_DAT2_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 2 : -1) /**< Pin number for AF_SDIO_DAT2 location number i */
|
||||
#define AF_SDIO_DAT3_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : -1) /**< Pin number for AF_SDIO_DAT3 location number i */
|
||||
#define AF_SDIO_DAT4_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : -1) /**< Pin number for AF_SDIO_DAT4 location number i */
|
||||
#define AF_SDIO_DAT5_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 5 : -1) /**< Pin number for AF_SDIO_DAT5 location number i */
|
||||
#define AF_SDIO_DAT6_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 3 : -1) /**< Pin number for AF_SDIO_DAT6 location number i */
|
||||
#define AF_SDIO_DAT7_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : -1) /**< Pin number for AF_SDIO_DAT7 location number i */
|
||||
#define AF_SDIO_CD_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 4 : (i) == 2 ? 6 : (i) == 3 ? 10 : -1) /**< Pin number for AF_SDIO_CD location number i */
|
||||
#define AF_SDIO_WP_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_SDIO_WP location number i */
|
||||
#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */
|
||||
#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */
|
||||
#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */
|
||||
#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */
|
||||
#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */
|
||||
#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */
|
||||
#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */
|
||||
#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */
|
||||
#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */
|
||||
#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */
|
||||
#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */
|
||||
#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */
|
||||
#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */
|
||||
#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */
|
||||
#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */
|
||||
#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */
|
||||
#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */
|
||||
#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */
|
||||
#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */
|
||||
#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */
|
||||
#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */
|
||||
#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */
|
||||
#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */
|
||||
#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */
|
||||
#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */
|
||||
#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */
|
||||
#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */
|
||||
#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */
|
||||
#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */
|
||||
#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */
|
||||
#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */
|
||||
#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */
|
||||
#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */
|
||||
#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */
|
||||
#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */
|
||||
#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */
|
||||
#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */
|
||||
#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */
|
||||
#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */
|
||||
#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */
|
||||
#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */
|
||||
#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */
|
||||
#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */
|
||||
#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */
|
||||
#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */
|
||||
#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */
|
||||
#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */
|
||||
#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */
|
||||
#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */
|
||||
#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */
|
||||
#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */
|
||||
#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */
|
||||
#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */
|
||||
#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */
|
||||
#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */
|
||||
#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */
|
||||
#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */
|
||||
#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */
|
||||
#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */
|
||||
#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */
|
||||
#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */
|
||||
#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */
|
||||
#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */
|
||||
#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */
|
||||
#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */
|
||||
#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */
|
||||
#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */
|
||||
#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */
|
||||
#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */
|
||||
#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */
|
||||
#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */
|
||||
#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */
|
||||
#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */
|
||||
#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */
|
||||
#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */
|
||||
#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */
|
||||
#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */
|
||||
#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */
|
||||
#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */
|
||||
#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */
|
||||
#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */
|
||||
#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */
|
||||
#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */
|
||||
#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */
|
||||
#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */
|
||||
#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */
|
||||
#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */
|
||||
#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */
|
||||
#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */
|
||||
#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */
|
||||
#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */
|
||||
#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */
|
||||
#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */
|
||||
#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */
|
||||
#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */
|
||||
#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */
|
||||
#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */
|
||||
#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */
|
||||
#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */
|
||||
#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */
|
||||
#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */
|
||||
#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */
|
||||
#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */
|
||||
#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */
|
||||
#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */
|
||||
#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */
|
||||
#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */
|
||||
#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */
|
||||
#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */
|
||||
#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */
|
||||
#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */
|
||||
#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */
|
||||
#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */
|
||||
#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */
|
||||
#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */
|
||||
#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */
|
||||
#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */
|
||||
#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */
|
||||
#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */
|
||||
#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */
|
||||
#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */
|
||||
#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */
|
||||
#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */
|
||||
#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */
|
||||
#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */
|
||||
#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */
|
||||
#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */
|
||||
#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */
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||||
#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */
|
||||
#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */
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||||
#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */
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||||
#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */
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||||
#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */
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||||
#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */
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||||
#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */
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||||
#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */
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||||
#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */
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||||
#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */
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||||
#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */
|
||||
#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */
|
||||
#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */
|
||||
#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */
|
||||
#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */
|
||||
#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */
|
||||
#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */
|
||||
#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */
|
||||
#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */
|
||||
#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */
|
||||
#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */
|
||||
#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */
|
||||
#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */
|
||||
#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */
|
||||
#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */
|
||||
#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */
|
||||
#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */
|
||||
#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */
|
||||
#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */
|
||||
#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */
|
||||
#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */
|
||||
#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */
|
||||
#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */
|
||||
#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */
|
||||
#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */
|
||||
#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */
|
||||
#define AF_QSPI0_SCLK_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 0 : -1) /**< Pin number for AF_QSPI0_SCLK location number i */
|
||||
#define AF_QSPI0_DQ0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Pin number for AF_QSPI0_DQ0 location number i */
|
||||
#define AF_QSPI0_DQ1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 3 : (i) == 2 ? 2 : -1) /**< Pin number for AF_QSPI0_DQ1 location number i */
|
||||
#define AF_QSPI0_DQ2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 4 : (i) == 2 ? 3 : -1) /**< Pin number for AF_QSPI0_DQ2 location number i */
|
||||
#define AF_QSPI0_DQ3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 4 : -1) /**< Pin number for AF_QSPI0_DQ3 location number i */
|
||||
#define AF_QSPI0_DQ4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_QSPI0_DQ4 location number i */
|
||||
#define AF_QSPI0_DQ5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Pin number for AF_QSPI0_DQ5 location number i */
|
||||
#define AF_QSPI0_DQ6_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 7 : -1) /**< Pin number for AF_QSPI0_DQ6 location number i */
|
||||
#define AF_QSPI0_DQ7_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_QSPI0_DQ7 location number i */
|
||||
#define AF_QSPI0_CS0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 9 : -1) /**< Pin number for AF_QSPI0_CS0 location number i */
|
||||
#define AF_QSPI0_CS1_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 10 : -1) /**< Pin number for AF_QSPI0_CS1 location number i */
|
||||
#define AF_QSPI0_DQS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 15 : (i) == 2 ? 11 : -1) /**< Pin number for AF_QSPI0_DQS location number i */
|
||||
#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */
|
||||
#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */
|
||||
#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */
|
||||
#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */
|
||||
#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */
|
||||
#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
|
||||
#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */
|
||||
#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */
|
||||
#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */
|
||||
#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */
|
||||
#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */
|
||||
#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */
|
||||
#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */
|
||||
#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */
|
||||
#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */
|
||||
#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */
|
||||
#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */
|
||||
#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */
|
||||
#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */
|
||||
#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */
|
||||
#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */
|
||||
#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */
|
||||
#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */
|
||||
#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */
|
||||
#define AF_USB_VBUSEN_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_USB_VBUSEN location number i */
|
||||
#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */
|
||||
#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */
|
||||
#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */
|
||||
#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */
|
||||
#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */
|
||||
#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */
|
||||
#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */
|
||||
#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */
|
||||
#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */
|
||||
#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_AF_Pins */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
403
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_ports.h
vendored
Normal file
403
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_ports.h
vendored
Normal file
@ -0,0 +1,403 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_AF_PORTS register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_Alternate_Function Alternate Function
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_AF_Ports Alternate Function Ports
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */
|
||||
#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */
|
||||
#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */
|
||||
#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */
|
||||
#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */
|
||||
#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */
|
||||
#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */
|
||||
#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */
|
||||
#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */
|
||||
#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */
|
||||
#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */
|
||||
#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */
|
||||
#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */
|
||||
#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */
|
||||
#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */
|
||||
#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */
|
||||
#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */
|
||||
#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */
|
||||
#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */
|
||||
#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */
|
||||
#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */
|
||||
#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */
|
||||
#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */
|
||||
#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */
|
||||
#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */
|
||||
#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */
|
||||
#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */
|
||||
#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */
|
||||
#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */
|
||||
#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */
|
||||
#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */
|
||||
#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */
|
||||
#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */
|
||||
#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */
|
||||
#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */
|
||||
#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */
|
||||
#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */
|
||||
#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */
|
||||
#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */
|
||||
#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */
|
||||
#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */
|
||||
#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */
|
||||
#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */
|
||||
#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */
|
||||
#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */
|
||||
#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */
|
||||
#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */
|
||||
#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */
|
||||
#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */
|
||||
#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */
|
||||
#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */
|
||||
#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */
|
||||
#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */
|
||||
#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */
|
||||
#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */
|
||||
#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */
|
||||
#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */
|
||||
#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */
|
||||
#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */
|
||||
#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */
|
||||
#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */
|
||||
#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */
|
||||
#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */
|
||||
#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */
|
||||
#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */
|
||||
#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */
|
||||
#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */
|
||||
#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */
|
||||
#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */
|
||||
#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */
|
||||
#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */
|
||||
#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */
|
||||
#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */
|
||||
#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */
|
||||
#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */
|
||||
#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */
|
||||
#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */
|
||||
#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */
|
||||
#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */
|
||||
#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */
|
||||
#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */
|
||||
#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */
|
||||
#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */
|
||||
#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */
|
||||
#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */
|
||||
#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */
|
||||
#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */
|
||||
#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */
|
||||
#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */
|
||||
#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */
|
||||
#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */
|
||||
#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */
|
||||
#define AF_ETH_MIITXCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXCLK location number i */
|
||||
#define AF_ETH_MIITXD3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD3 location number i */
|
||||
#define AF_ETH_MIITXD2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD2 location number i */
|
||||
#define AF_ETH_MIITXD1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD1 location number i */
|
||||
#define AF_ETH_MIITXD0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD0 location number i */
|
||||
#define AF_ETH_MIITXEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXEN location number i */
|
||||
#define AF_ETH_MIITXER_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXER location number i */
|
||||
#define AF_ETH_MIIRXCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXCLK location number i */
|
||||
#define AF_ETH_MIIRXD3_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD3 location number i */
|
||||
#define AF_ETH_MIIRXD2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD2 location number i */
|
||||
#define AF_ETH_MIIRXD1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD1 location number i */
|
||||
#define AF_ETH_MIIRXD0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXD0 location number i */
|
||||
#define AF_ETH_MIIRXDV_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXDV location number i */
|
||||
#define AF_ETH_MIIRXER_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXER location number i */
|
||||
#define AF_ETH_MIICRS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 6 : (i) == 2 ? 1 : -1) /**< Port number for AF_ETH_MIICRS location number i */
|
||||
#define AF_ETH_MIICOL_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 6 : (i) == 2 ? 1 : -1) /**< Port number for AF_ETH_MIICOL location number i */
|
||||
#define AF_ETH_MDIO_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_ETH_MDIO location number i */
|
||||
#define AF_ETH_MDC_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_ETH_MDC location number i */
|
||||
#define AF_ETH_TSUEXTCLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_ETH_TSUEXTCLK location number i */
|
||||
#define AF_ETH_TSUTMRTOG_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_ETH_TSUTMRTOG location number i */
|
||||
#define AF_ETH_RMIITXD1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXD1 location number i */
|
||||
#define AF_ETH_RMIITXD0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXD0 location number i */
|
||||
#define AF_ETH_RMIITXEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXEN location number i */
|
||||
#define AF_ETH_RMIIRXD1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIIRXD1 location number i */
|
||||
#define AF_ETH_RMIIRXD0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIRXD0 location number i */
|
||||
#define AF_ETH_RMIIREFCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIREFCLK location number i */
|
||||
#define AF_ETH_RMIICRSDV_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIICRSDV location number i */
|
||||
#define AF_ETH_RMIIRXER_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIRXER location number i */
|
||||
#define AF_SDIO_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Port number for AF_SDIO_CLK location number i */
|
||||
#define AF_SDIO_CMD_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Port number for AF_SDIO_CMD location number i */
|
||||
#define AF_SDIO_DAT0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT0 location number i */
|
||||
#define AF_SDIO_DAT1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT1 location number i */
|
||||
#define AF_SDIO_DAT2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT2 location number i */
|
||||
#define AF_SDIO_DAT3_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT3 location number i */
|
||||
#define AF_SDIO_DAT4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT4 location number i */
|
||||
#define AF_SDIO_DAT5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT5 location number i */
|
||||
#define AF_SDIO_DAT6_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : -1) /**< Port number for AF_SDIO_DAT6 location number i */
|
||||
#define AF_SDIO_DAT7_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : -1) /**< Port number for AF_SDIO_DAT7 location number i */
|
||||
#define AF_SDIO_CD_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Port number for AF_SDIO_CD location number i */
|
||||
#define AF_SDIO_WP_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 1 : -1) /**< Port number for AF_SDIO_WP location number i */
|
||||
#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */
|
||||
#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */
|
||||
#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */
|
||||
#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */
|
||||
#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */
|
||||
#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */
|
||||
#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */
|
||||
#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */
|
||||
#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */
|
||||
#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */
|
||||
#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */
|
||||
#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */
|
||||
#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */
|
||||
#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */
|
||||
#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */
|
||||
#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */
|
||||
#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */
|
||||
#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */
|
||||
#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */
|
||||
#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */
|
||||
#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */
|
||||
#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */
|
||||
#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */
|
||||
#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */
|
||||
#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */
|
||||
#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */
|
||||
#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */
|
||||
#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */
|
||||
#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */
|
||||
#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */
|
||||
#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */
|
||||
#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */
|
||||
#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */
|
||||
#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */
|
||||
#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */
|
||||
#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */
|
||||
#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */
|
||||
#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */
|
||||
#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */
|
||||
#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */
|
||||
#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */
|
||||
#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */
|
||||
#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */
|
||||
#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */
|
||||
#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */
|
||||
#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */
|
||||
#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */
|
||||
#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */
|
||||
#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */
|
||||
#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */
|
||||
#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */
|
||||
#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */
|
||||
#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */
|
||||
#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */
|
||||
#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */
|
||||
#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */
|
||||
#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */
|
||||
#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */
|
||||
#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */
|
||||
#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */
|
||||
#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */
|
||||
#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */
|
||||
#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */
|
||||
#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */
|
||||
#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */
|
||||
#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */
|
||||
#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */
|
||||
#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */
|
||||
#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */
|
||||
#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */
|
||||
#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */
|
||||
#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */
|
||||
#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */
|
||||
#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */
|
||||
#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */
|
||||
#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */
|
||||
#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */
|
||||
#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */
|
||||
#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */
|
||||
#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */
|
||||
#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */
|
||||
#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */
|
||||
#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */
|
||||
#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */
|
||||
#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */
|
||||
#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */
|
||||
#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */
|
||||
#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */
|
||||
#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */
|
||||
#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */
|
||||
#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */
|
||||
#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */
|
||||
#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */
|
||||
#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */
|
||||
#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */
|
||||
#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */
|
||||
#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */
|
||||
#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */
|
||||
#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */
|
||||
#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */
|
||||
#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */
|
||||
#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */
|
||||
#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */
|
||||
#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */
|
||||
#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */
|
||||
#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */
|
||||
#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */
|
||||
#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */
|
||||
#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */
|
||||
#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */
|
||||
#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */
|
||||
#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */
|
||||
#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */
|
||||
#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */
|
||||
#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */
|
||||
#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */
|
||||
#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */
|
||||
#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */
|
||||
#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */
|
||||
#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */
|
||||
#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */
|
||||
#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */
|
||||
#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */
|
||||
#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */
|
||||
#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */
|
||||
#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */
|
||||
#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */
|
||||
#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */
|
||||
#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */
|
||||
#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */
|
||||
#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */
|
||||
#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */
|
||||
#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */
|
||||
#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */
|
||||
#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */
|
||||
#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */
|
||||
#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */
|
||||
#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */
|
||||
#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */
|
||||
#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */
|
||||
#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */
|
||||
#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */
|
||||
#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */
|
||||
#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */
|
||||
#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */
|
||||
#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */
|
||||
#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */
|
||||
#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */
|
||||
#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */
|
||||
#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */
|
||||
#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */
|
||||
#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */
|
||||
#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */
|
||||
#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */
|
||||
#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */
|
||||
#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */
|
||||
#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */
|
||||
#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */
|
||||
#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */
|
||||
#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */
|
||||
#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */
|
||||
#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */
|
||||
#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */
|
||||
#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */
|
||||
#define AF_QSPI0_SCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_SCLK location number i */
|
||||
#define AF_QSPI0_DQ0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ0 location number i */
|
||||
#define AF_QSPI0_DQ1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ1 location number i */
|
||||
#define AF_QSPI0_DQ2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ2 location number i */
|
||||
#define AF_QSPI0_DQ3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ3 location number i */
|
||||
#define AF_QSPI0_DQ4_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ4 location number i */
|
||||
#define AF_QSPI0_DQ5_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ5 location number i */
|
||||
#define AF_QSPI0_DQ6_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ6 location number i */
|
||||
#define AF_QSPI0_DQ7_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ7 location number i */
|
||||
#define AF_QSPI0_CS0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_CS0 location number i */
|
||||
#define AF_QSPI0_CS1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_CS1 location number i */
|
||||
#define AF_QSPI0_DQS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQS location number i */
|
||||
#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */
|
||||
#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */
|
||||
#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */
|
||||
#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */
|
||||
#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */
|
||||
#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */
|
||||
#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */
|
||||
#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */
|
||||
#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */
|
||||
#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */
|
||||
#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */
|
||||
#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */
|
||||
#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */
|
||||
#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */
|
||||
#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */
|
||||
#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */
|
||||
#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */
|
||||
#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */
|
||||
#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */
|
||||
#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */
|
||||
#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */
|
||||
#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */
|
||||
#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */
|
||||
#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */
|
||||
#define AF_USB_VBUSEN_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_USB_VBUSEN location number i */
|
||||
#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */
|
||||
#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */
|
||||
#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */
|
||||
#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */
|
||||
#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */
|
||||
#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */
|
||||
#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */
|
||||
#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */
|
||||
#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */
|
||||
#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_AF_Ports */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
652
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can.h
vendored
Normal file
652
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can.h
vendored
Normal file
@ -0,0 +1,652 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_CAN register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_CAN CAN
|
||||
* @{
|
||||
* @brief EFM32GG11B_CAN Register Declaration
|
||||
******************************************************************************/
|
||||
/** CAN Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t ERRCNT; /**< Error Count Register */
|
||||
__IOM uint32_t BITTIMING; /**< Bit Timing Register */
|
||||
__IM uint32_t INTID; /**< Interrupt Identification Register */
|
||||
__IOM uint32_t TEST; /**< Test Register */
|
||||
__IOM uint32_t BRPE; /**< BRP Extension Register */
|
||||
__IM uint32_t TRANSREQ; /**< Transmission Request Register */
|
||||
__IM uint32_t MESSAGEDATA; /**< New Data Register */
|
||||
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t MESSAGESTATE; /**< Message Valid Register */
|
||||
__IOM uint32_t CONFIG; /**< Configuration Register */
|
||||
__IM uint32_t IF0IF; /**< Message Object Interrupt Flag Register */
|
||||
__IOM uint32_t IF0IFS; /**< Message Object Interrupt Flag Set Register */
|
||||
__IOM uint32_t IF0IFC; /**< Message Object Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IF0IEN; /**< Message Object Interrupt Enable Register */
|
||||
__IM uint32_t IF1IF; /**< Status Interrupt Flag Register */
|
||||
__IOM uint32_t IF1IFS; /**< Message Object Interrupt Flag Set Register */
|
||||
__IOM uint32_t IF1IFC; /**< Message Object Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IF1IEN; /**< Status Interrupt Enable Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
|
||||
uint32_t RESERVED1[3U]; /**< Reserved registers */
|
||||
CAN_MIR_TypeDef MIR[2U]; /**< Interface Registers */
|
||||
} CAN_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_CAN
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_CAN_BitFields CAN Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for CAN CTRL */
|
||||
#define _CAN_CTRL_RESETVALUE 0x00000001UL /**< Default value for CAN_CTRL */
|
||||
#define _CAN_CTRL_MASK 0x000000EFUL /**< Mask for CAN_CTRL */
|
||||
#define CAN_CTRL_INIT (0x1UL << 0) /**< Initialize */
|
||||
#define _CAN_CTRL_INIT_SHIFT 0 /**< Shift value for CAN_INIT */
|
||||
#define _CAN_CTRL_INIT_MASK 0x1UL /**< Bit mask for CAN_INIT */
|
||||
#define _CAN_CTRL_INIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_INIT_DEFAULT (_CAN_CTRL_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_IE (0x1UL << 1) /**< Module Interrupt Enable */
|
||||
#define _CAN_CTRL_IE_SHIFT 1 /**< Shift value for CAN_IE */
|
||||
#define _CAN_CTRL_IE_MASK 0x2UL /**< Bit mask for CAN_IE */
|
||||
#define _CAN_CTRL_IE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_IE_DEFAULT (_CAN_CTRL_IE_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_SIE (0x1UL << 2) /**< Status Change Interrupt Enable */
|
||||
#define _CAN_CTRL_SIE_SHIFT 2 /**< Shift value for CAN_SIE */
|
||||
#define _CAN_CTRL_SIE_MASK 0x4UL /**< Bit mask for CAN_SIE */
|
||||
#define _CAN_CTRL_SIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_SIE_DEFAULT (_CAN_CTRL_SIE_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_EIE (0x1UL << 3) /**< Error Interrupt Enable */
|
||||
#define _CAN_CTRL_EIE_SHIFT 3 /**< Shift value for CAN_EIE */
|
||||
#define _CAN_CTRL_EIE_MASK 0x8UL /**< Bit mask for CAN_EIE */
|
||||
#define _CAN_CTRL_EIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_EIE_DEFAULT (_CAN_CTRL_EIE_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_DAR (0x1UL << 5) /**< Disable Automatic Retransmission */
|
||||
#define _CAN_CTRL_DAR_SHIFT 5 /**< Shift value for CAN_DAR */
|
||||
#define _CAN_CTRL_DAR_MASK 0x20UL /**< Bit mask for CAN_DAR */
|
||||
#define _CAN_CTRL_DAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_DAR_DEFAULT (_CAN_CTRL_DAR_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_CCE (0x1UL << 6) /**< Configuration Change Enable */
|
||||
#define _CAN_CTRL_CCE_SHIFT 6 /**< Shift value for CAN_CCE */
|
||||
#define _CAN_CTRL_CCE_MASK 0x40UL /**< Bit mask for CAN_CCE */
|
||||
#define _CAN_CTRL_CCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_CCE_DEFAULT (_CAN_CTRL_CCE_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_TEST (0x1UL << 7) /**< Test Mode Enable Write */
|
||||
#define _CAN_CTRL_TEST_SHIFT 7 /**< Shift value for CAN_TEST */
|
||||
#define _CAN_CTRL_TEST_MASK 0x80UL /**< Bit mask for CAN_TEST */
|
||||
#define _CAN_CTRL_TEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_TEST_DEFAULT (_CAN_CTRL_TEST_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
|
||||
/* Bit fields for CAN STATUS */
|
||||
#define _CAN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CAN_STATUS */
|
||||
#define _CAN_STATUS_MASK 0x000000FFUL /**< Mask for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_SHIFT 0 /**< Shift value for CAN_LEC */
|
||||
#define _CAN_STATUS_LEC_MASK 0x7UL /**< Bit mask for CAN_LEC */
|
||||
#define _CAN_STATUS_LEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_NONE 0x00000000UL /**< Mode NONE for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_STUFF 0x00000001UL /**< Mode STUFF for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_FORM 0x00000002UL /**< Mode FORM for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_ACK 0x00000003UL /**< Mode ACK for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_BIT1 0x00000004UL /**< Mode BIT1 for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_BIT0 0x00000005UL /**< Mode BIT0 for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_CRC 0x00000006UL /**< Mode CRC for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_UNUSED 0x00000007UL /**< Mode UNUSED for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_DEFAULT (_CAN_STATUS_LEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_NONE (_CAN_STATUS_LEC_NONE << 0) /**< Shifted mode NONE for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_STUFF (_CAN_STATUS_LEC_STUFF << 0) /**< Shifted mode STUFF for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_FORM (_CAN_STATUS_LEC_FORM << 0) /**< Shifted mode FORM for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_ACK (_CAN_STATUS_LEC_ACK << 0) /**< Shifted mode ACK for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_BIT1 (_CAN_STATUS_LEC_BIT1 << 0) /**< Shifted mode BIT1 for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_BIT0 (_CAN_STATUS_LEC_BIT0 << 0) /**< Shifted mode BIT0 for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_CRC (_CAN_STATUS_LEC_CRC << 0) /**< Shifted mode CRC for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_UNUSED (_CAN_STATUS_LEC_UNUSED << 0) /**< Shifted mode UNUSED for CAN_STATUS */
|
||||
#define CAN_STATUS_TXOK (0x1UL << 3) /**< Transmitted a Message Successfully */
|
||||
#define _CAN_STATUS_TXOK_SHIFT 3 /**< Shift value for CAN_TXOK */
|
||||
#define _CAN_STATUS_TXOK_MASK 0x8UL /**< Bit mask for CAN_TXOK */
|
||||
#define _CAN_STATUS_TXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_TXOK_DEFAULT (_CAN_STATUS_TXOK_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_RXOK (0x1UL << 4) /**< Received a Message Successfully */
|
||||
#define _CAN_STATUS_RXOK_SHIFT 4 /**< Shift value for CAN_RXOK */
|
||||
#define _CAN_STATUS_RXOK_MASK 0x10UL /**< Bit mask for CAN_RXOK */
|
||||
#define _CAN_STATUS_RXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_RXOK_DEFAULT (_CAN_STATUS_RXOK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_EPASS (0x1UL << 5) /**< Error Passive */
|
||||
#define _CAN_STATUS_EPASS_SHIFT 5 /**< Shift value for CAN_EPASS */
|
||||
#define _CAN_STATUS_EPASS_MASK 0x20UL /**< Bit mask for CAN_EPASS */
|
||||
#define _CAN_STATUS_EPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_EPASS_DEFAULT (_CAN_STATUS_EPASS_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_EWARN (0x1UL << 6) /**< Warning Status */
|
||||
#define _CAN_STATUS_EWARN_SHIFT 6 /**< Shift value for CAN_EWARN */
|
||||
#define _CAN_STATUS_EWARN_MASK 0x40UL /**< Bit mask for CAN_EWARN */
|
||||
#define _CAN_STATUS_EWARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_EWARN_DEFAULT (_CAN_STATUS_EWARN_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_BOFF (0x1UL << 7) /**< Bus Off Status */
|
||||
#define _CAN_STATUS_BOFF_SHIFT 7 /**< Shift value for CAN_BOFF */
|
||||
#define _CAN_STATUS_BOFF_MASK 0x80UL /**< Bit mask for CAN_BOFF */
|
||||
#define _CAN_STATUS_BOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_BOFF_DEFAULT (_CAN_STATUS_BOFF_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
|
||||
/* Bit fields for CAN ERRCNT */
|
||||
#define _CAN_ERRCNT_RESETVALUE 0x00000000UL /**< Default value for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_MASK 0x0000FFFFUL /**< Mask for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_TEC_SHIFT 0 /**< Shift value for CAN_TEC */
|
||||
#define _CAN_ERRCNT_TEC_MASK 0xFFUL /**< Bit mask for CAN_TEC */
|
||||
#define _CAN_ERRCNT_TEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_TEC_DEFAULT (_CAN_ERRCNT_TEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_REC_SHIFT 8 /**< Shift value for CAN_REC */
|
||||
#define _CAN_ERRCNT_REC_MASK 0x7F00UL /**< Bit mask for CAN_REC */
|
||||
#define _CAN_ERRCNT_REC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_REC_DEFAULT (_CAN_ERRCNT_REC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_RECERRP (0x1UL << 15) /**< Receive Error Passive */
|
||||
#define _CAN_ERRCNT_RECERRP_SHIFT 15 /**< Shift value for CAN_RECERRP */
|
||||
#define _CAN_ERRCNT_RECERRP_MASK 0x8000UL /**< Bit mask for CAN_RECERRP */
|
||||
#define _CAN_ERRCNT_RECERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_RECERRP_FALSE 0x00000000UL /**< Mode FALSE for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_RECERRP_TRUE 0x00000001UL /**< Mode TRUE for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_RECERRP_DEFAULT (_CAN_ERRCNT_RECERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_RECERRP_FALSE (_CAN_ERRCNT_RECERRP_FALSE << 15) /**< Shifted mode FALSE for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_RECERRP_TRUE (_CAN_ERRCNT_RECERRP_TRUE << 15) /**< Shifted mode TRUE for CAN_ERRCNT */
|
||||
|
||||
/* Bit fields for CAN BITTIMING */
|
||||
#define _CAN_BITTIMING_RESETVALUE 0x00002301UL /**< Default value for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_MASK 0x00007FFFUL /**< Mask for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_BRP_SHIFT 0 /**< Shift value for CAN_BRP */
|
||||
#define _CAN_BITTIMING_BRP_MASK 0x3FUL /**< Bit mask for CAN_BRP */
|
||||
#define _CAN_BITTIMING_BRP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_BITTIMING */
|
||||
#define CAN_BITTIMING_BRP_DEFAULT (_CAN_BITTIMING_BRP_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_SJW_SHIFT 6 /**< Shift value for CAN_SJW */
|
||||
#define _CAN_BITTIMING_SJW_MASK 0xC0UL /**< Bit mask for CAN_SJW */
|
||||
#define _CAN_BITTIMING_SJW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BITTIMING */
|
||||
#define CAN_BITTIMING_SJW_DEFAULT (_CAN_BITTIMING_SJW_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_TSEG1_SHIFT 8 /**< Shift value for CAN_TSEG1 */
|
||||
#define _CAN_BITTIMING_TSEG1_MASK 0xF00UL /**< Bit mask for CAN_TSEG1 */
|
||||
#define _CAN_BITTIMING_TSEG1_DEFAULT 0x00000003UL /**< Mode DEFAULT for CAN_BITTIMING */
|
||||
#define CAN_BITTIMING_TSEG1_DEFAULT (_CAN_BITTIMING_TSEG1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_TSEG2_SHIFT 12 /**< Shift value for CAN_TSEG2 */
|
||||
#define _CAN_BITTIMING_TSEG2_MASK 0x7000UL /**< Bit mask for CAN_TSEG2 */
|
||||
#define _CAN_BITTIMING_TSEG2_DEFAULT 0x00000002UL /**< Mode DEFAULT for CAN_BITTIMING */
|
||||
#define CAN_BITTIMING_TSEG2_DEFAULT (_CAN_BITTIMING_TSEG2_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_BITTIMING */
|
||||
|
||||
/* Bit fields for CAN INTID */
|
||||
#define _CAN_INTID_RESETVALUE 0x00000000UL /**< Default value for CAN_INTID */
|
||||
#define _CAN_INTID_MASK 0x0000803FUL /**< Mask for CAN_INTID */
|
||||
#define _CAN_INTID_INTID_SHIFT 0 /**< Shift value for CAN_INTID */
|
||||
#define _CAN_INTID_INTID_MASK 0x3FUL /**< Bit mask for CAN_INTID */
|
||||
#define _CAN_INTID_INTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */
|
||||
#define CAN_INTID_INTID_DEFAULT (_CAN_INTID_INTID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_INTID */
|
||||
#define CAN_INTID_INTSTAT (0x1UL << 15) /**< Status Interupt */
|
||||
#define _CAN_INTID_INTSTAT_SHIFT 15 /**< Shift value for CAN_INTSTAT */
|
||||
#define _CAN_INTID_INTSTAT_MASK 0x8000UL /**< Bit mask for CAN_INTSTAT */
|
||||
#define _CAN_INTID_INTSTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */
|
||||
#define _CAN_INTID_INTSTAT_FALSE 0x00000000UL /**< Mode FALSE for CAN_INTID */
|
||||
#define _CAN_INTID_INTSTAT_TRUE 0x00000001UL /**< Mode TRUE for CAN_INTID */
|
||||
#define CAN_INTID_INTSTAT_DEFAULT (_CAN_INTID_INTSTAT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_INTID */
|
||||
#define CAN_INTID_INTSTAT_FALSE (_CAN_INTID_INTSTAT_FALSE << 15) /**< Shifted mode FALSE for CAN_INTID */
|
||||
#define CAN_INTID_INTSTAT_TRUE (_CAN_INTID_INTSTAT_TRUE << 15) /**< Shifted mode TRUE for CAN_INTID */
|
||||
|
||||
/* Bit fields for CAN TEST */
|
||||
#define _CAN_TEST_RESETVALUE 0x00000000UL /**< Default value for CAN_TEST */
|
||||
#define _CAN_TEST_MASK 0x000000FCUL /**< Mask for CAN_TEST */
|
||||
#define CAN_TEST_BASIC (0x1UL << 2) /**< Basic Mode */
|
||||
#define _CAN_TEST_BASIC_SHIFT 2 /**< Shift value for CAN_BASIC */
|
||||
#define _CAN_TEST_BASIC_MASK 0x4UL /**< Bit mask for CAN_BASIC */
|
||||
#define _CAN_TEST_BASIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_BASIC_DEFAULT (_CAN_TEST_BASIC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_SILENT (0x1UL << 3) /**< Silent Mode */
|
||||
#define _CAN_TEST_SILENT_SHIFT 3 /**< Shift value for CAN_SILENT */
|
||||
#define _CAN_TEST_SILENT_MASK 0x8UL /**< Bit mask for CAN_SILENT */
|
||||
#define _CAN_TEST_SILENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_SILENT_DEFAULT (_CAN_TEST_SILENT_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_LBACK (0x1UL << 4) /**< Loopback Mode */
|
||||
#define _CAN_TEST_LBACK_SHIFT 4 /**< Shift value for CAN_LBACK */
|
||||
#define _CAN_TEST_LBACK_MASK 0x10UL /**< Bit mask for CAN_LBACK */
|
||||
#define _CAN_TEST_LBACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_LBACK_DEFAULT (_CAN_TEST_LBACK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define _CAN_TEST_TX_SHIFT 5 /**< Shift value for CAN_TX */
|
||||
#define _CAN_TEST_TX_MASK 0x60UL /**< Bit mask for CAN_TX */
|
||||
#define _CAN_TEST_TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define _CAN_TEST_TX_CORE 0x00000000UL /**< Mode CORE for CAN_TEST */
|
||||
#define _CAN_TEST_TX_SAMPT 0x00000001UL /**< Mode SAMPT for CAN_TEST */
|
||||
#define _CAN_TEST_TX_LOW 0x00000002UL /**< Mode LOW for CAN_TEST */
|
||||
#define _CAN_TEST_TX_HIGH 0x00000003UL /**< Mode HIGH for CAN_TEST */
|
||||
#define CAN_TEST_TX_DEFAULT (_CAN_TEST_TX_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_TX_CORE (_CAN_TEST_TX_CORE << 5) /**< Shifted mode CORE for CAN_TEST */
|
||||
#define CAN_TEST_TX_SAMPT (_CAN_TEST_TX_SAMPT << 5) /**< Shifted mode SAMPT for CAN_TEST */
|
||||
#define CAN_TEST_TX_LOW (_CAN_TEST_TX_LOW << 5) /**< Shifted mode LOW for CAN_TEST */
|
||||
#define CAN_TEST_TX_HIGH (_CAN_TEST_TX_HIGH << 5) /**< Shifted mode HIGH for CAN_TEST */
|
||||
#define CAN_TEST_RX (0x1UL << 7) /**< Monitors the Actual Value of CAN_RX Pin */
|
||||
#define _CAN_TEST_RX_SHIFT 7 /**< Shift value for CAN_RX */
|
||||
#define _CAN_TEST_RX_MASK 0x80UL /**< Bit mask for CAN_RX */
|
||||
#define _CAN_TEST_RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define _CAN_TEST_RX_LOW 0x00000000UL /**< Mode LOW for CAN_TEST */
|
||||
#define _CAN_TEST_RX_HIGH 0x00000001UL /**< Mode HIGH for CAN_TEST */
|
||||
#define CAN_TEST_RX_DEFAULT (_CAN_TEST_RX_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_RX_LOW (_CAN_TEST_RX_LOW << 7) /**< Shifted mode LOW for CAN_TEST */
|
||||
#define CAN_TEST_RX_HIGH (_CAN_TEST_RX_HIGH << 7) /**< Shifted mode HIGH for CAN_TEST */
|
||||
|
||||
/* Bit fields for CAN BRPE */
|
||||
#define _CAN_BRPE_RESETVALUE 0x00000000UL /**< Default value for CAN_BRPE */
|
||||
#define _CAN_BRPE_MASK 0x0000000FUL /**< Mask for CAN_BRPE */
|
||||
#define _CAN_BRPE_BRPE_SHIFT 0 /**< Shift value for CAN_BRPE */
|
||||
#define _CAN_BRPE_BRPE_MASK 0xFUL /**< Bit mask for CAN_BRPE */
|
||||
#define _CAN_BRPE_BRPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BRPE */
|
||||
#define CAN_BRPE_BRPE_DEFAULT (_CAN_BRPE_BRPE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BRPE */
|
||||
|
||||
/* Bit fields for CAN TRANSREQ */
|
||||
#define _CAN_TRANSREQ_RESETVALUE 0x00000000UL /**< Default value for CAN_TRANSREQ */
|
||||
#define _CAN_TRANSREQ_MASK 0xFFFFFFFFUL /**< Mask for CAN_TRANSREQ */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_SHIFT 0 /**< Shift value for CAN_TXRQSTOUT */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_TXRQSTOUT */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TRANSREQ */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_FALSE 0x00000000UL /**< Mode FALSE for CAN_TRANSREQ */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_TRUE 0x00000001UL /**< Mode TRUE for CAN_TRANSREQ */
|
||||
#define CAN_TRANSREQ_TXRQSTOUT_DEFAULT (_CAN_TRANSREQ_TXRQSTOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_TRANSREQ */
|
||||
#define CAN_TRANSREQ_TXRQSTOUT_FALSE (_CAN_TRANSREQ_TXRQSTOUT_FALSE << 0) /**< Shifted mode FALSE for CAN_TRANSREQ */
|
||||
#define CAN_TRANSREQ_TXRQSTOUT_TRUE (_CAN_TRANSREQ_TXRQSTOUT_TRUE << 0) /**< Shifted mode TRUE for CAN_TRANSREQ */
|
||||
|
||||
/* Bit fields for CAN MESSAGEDATA */
|
||||
#define _CAN_MESSAGEDATA_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGEDATA */
|
||||
#define _CAN_MESSAGEDATA_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGEDATA */
|
||||
#define _CAN_MESSAGEDATA_VALID_SHIFT 0 /**< Shift value for CAN_VALID */
|
||||
#define _CAN_MESSAGEDATA_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */
|
||||
#define _CAN_MESSAGEDATA_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGEDATA */
|
||||
#define CAN_MESSAGEDATA_VALID_DEFAULT (_CAN_MESSAGEDATA_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGEDATA */
|
||||
|
||||
/* Bit fields for CAN MESSAGESTATE */
|
||||
#define _CAN_MESSAGESTATE_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGESTATE */
|
||||
#define _CAN_MESSAGESTATE_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGESTATE */
|
||||
#define _CAN_MESSAGESTATE_VALID_SHIFT 0 /**< Shift value for CAN_VALID */
|
||||
#define _CAN_MESSAGESTATE_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */
|
||||
#define _CAN_MESSAGESTATE_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGESTATE */
|
||||
#define CAN_MESSAGESTATE_VALID_DEFAULT (_CAN_MESSAGESTATE_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGESTATE */
|
||||
|
||||
/* Bit fields for CAN CONFIG */
|
||||
#define _CAN_CONFIG_RESETVALUE 0x00000000UL /**< Default value for CAN_CONFIG */
|
||||
#define _CAN_CONFIG_MASK 0x00008000UL /**< Mask for CAN_CONFIG */
|
||||
#define CAN_CONFIG_DBGHALT (0x1UL << 15) /**< Debug Halt */
|
||||
#define _CAN_CONFIG_DBGHALT_SHIFT 15 /**< Shift value for CAN_DBGHALT */
|
||||
#define _CAN_CONFIG_DBGHALT_MASK 0x8000UL /**< Bit mask for CAN_DBGHALT */
|
||||
#define _CAN_CONFIG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CONFIG */
|
||||
#define _CAN_CONFIG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for CAN_CONFIG */
|
||||
#define _CAN_CONFIG_DBGHALT_STALL 0x00000001UL /**< Mode STALL for CAN_CONFIG */
|
||||
#define CAN_CONFIG_DBGHALT_DEFAULT (_CAN_CONFIG_DBGHALT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_CONFIG */
|
||||
#define CAN_CONFIG_DBGHALT_NORMAL (_CAN_CONFIG_DBGHALT_NORMAL << 15) /**< Shifted mode NORMAL for CAN_CONFIG */
|
||||
#define CAN_CONFIG_DBGHALT_STALL (_CAN_CONFIG_DBGHALT_STALL << 15) /**< Shifted mode STALL for CAN_CONFIG */
|
||||
|
||||
/* Bit fields for CAN IF0IF */
|
||||
#define _CAN_IF0IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IF */
|
||||
#define _CAN_IF0IF_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IF */
|
||||
#define _CAN_IF0IF_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
|
||||
#define _CAN_IF0IF_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
|
||||
#define _CAN_IF0IF_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IF */
|
||||
#define CAN_IF0IF_MESSAGE_DEFAULT (_CAN_IF0IF_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IF */
|
||||
|
||||
/* Bit fields for CAN IF0IFS */
|
||||
#define _CAN_IF0IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFS */
|
||||
#define _CAN_IF0IFS_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFS */
|
||||
#define _CAN_IF0IFS_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
|
||||
#define _CAN_IF0IFS_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
|
||||
#define _CAN_IF0IFS_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFS */
|
||||
#define CAN_IF0IFS_MESSAGE_DEFAULT (_CAN_IF0IFS_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFS */
|
||||
|
||||
/* Bit fields for CAN IF0IFC */
|
||||
#define _CAN_IF0IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFC */
|
||||
#define _CAN_IF0IFC_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFC */
|
||||
#define _CAN_IF0IFC_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
|
||||
#define _CAN_IF0IFC_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
|
||||
#define _CAN_IF0IFC_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFC */
|
||||
#define CAN_IF0IFC_MESSAGE_DEFAULT (_CAN_IF0IFC_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFC */
|
||||
|
||||
/* Bit fields for CAN IF0IEN */
|
||||
#define _CAN_IF0IEN_RESETVALUE 0xFFFFFFFFUL /**< Default value for CAN_IF0IEN */
|
||||
#define _CAN_IF0IEN_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IEN */
|
||||
#define _CAN_IF0IEN_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
|
||||
#define _CAN_IF0IEN_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
|
||||
#define _CAN_IF0IEN_MESSAGE_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for CAN_IF0IEN */
|
||||
#define CAN_IF0IEN_MESSAGE_DEFAULT (_CAN_IF0IEN_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IEN */
|
||||
|
||||
/* Bit fields for CAN IF1IF */
|
||||
#define _CAN_IF1IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IF */
|
||||
#define _CAN_IF1IF_MASK 0x00000001UL /**< Mask for CAN_IF1IF */
|
||||
#define CAN_IF1IF_STATUS (0x1UL << 0) /**< Status Interrupt Flag */
|
||||
#define _CAN_IF1IF_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
|
||||
#define _CAN_IF1IF_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
|
||||
#define _CAN_IF1IF_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IF */
|
||||
#define CAN_IF1IF_STATUS_DEFAULT (_CAN_IF1IF_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IF */
|
||||
|
||||
/* Bit fields for CAN IF1IFS */
|
||||
#define _CAN_IF1IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFS */
|
||||
#define _CAN_IF1IFS_MASK 0x00000001UL /**< Mask for CAN_IF1IFS */
|
||||
#define CAN_IF1IFS_STATUS (0x1UL << 0) /**< Set STATUS Interrupt Flag */
|
||||
#define _CAN_IF1IFS_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
|
||||
#define _CAN_IF1IFS_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
|
||||
#define _CAN_IF1IFS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFS */
|
||||
#define CAN_IF1IFS_STATUS_DEFAULT (_CAN_IF1IFS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFS */
|
||||
|
||||
/* Bit fields for CAN IF1IFC */
|
||||
#define _CAN_IF1IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFC */
|
||||
#define _CAN_IF1IFC_MASK 0x00000001UL /**< Mask for CAN_IF1IFC */
|
||||
#define CAN_IF1IFC_STATUS (0x1UL << 0) /**< Clear STATUS Interrupt Flag */
|
||||
#define _CAN_IF1IFC_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
|
||||
#define _CAN_IF1IFC_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
|
||||
#define _CAN_IF1IFC_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFC */
|
||||
#define CAN_IF1IFC_STATUS_DEFAULT (_CAN_IF1IFC_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFC */
|
||||
|
||||
/* Bit fields for CAN IF1IEN */
|
||||
#define _CAN_IF1IEN_RESETVALUE 0x00000001UL /**< Default value for CAN_IF1IEN */
|
||||
#define _CAN_IF1IEN_MASK 0x00000001UL /**< Mask for CAN_IF1IEN */
|
||||
#define CAN_IF1IEN_STATUS (0x1UL << 0) /**< STATUS Interrupt Enable */
|
||||
#define _CAN_IF1IEN_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
|
||||
#define _CAN_IF1IEN_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
|
||||
#define _CAN_IF1IEN_STATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_IF1IEN */
|
||||
#define CAN_IF1IEN_STATUS_DEFAULT (_CAN_IF1IEN_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IEN */
|
||||
|
||||
/* Bit fields for CAN ROUTE */
|
||||
#define _CAN_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_MASK 0x0000071DUL /**< Mask for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXPEN (0x1UL << 0) /**< TX Pin Enable */
|
||||
#define _CAN_ROUTE_TXPEN_SHIFT 0 /**< Shift value for CAN_TXPEN */
|
||||
#define _CAN_ROUTE_TXPEN_MASK 0x1UL /**< Bit mask for CAN_TXPEN */
|
||||
#define _CAN_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXPEN_DEFAULT (_CAN_ROUTE_TXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_SHIFT 2 /**< Shift value for CAN_RXLOC */
|
||||
#define _CAN_ROUTE_RXLOC_MASK 0x1CUL /**< Bit mask for CAN_RXLOC */
|
||||
#define _CAN_ROUTE_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC0 (_CAN_ROUTE_RXLOC_LOC0 << 2) /**< Shifted mode LOC0 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_DEFAULT (_CAN_ROUTE_RXLOC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC1 (_CAN_ROUTE_RXLOC_LOC1 << 2) /**< Shifted mode LOC1 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC2 (_CAN_ROUTE_RXLOC_LOC2 << 2) /**< Shifted mode LOC2 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC3 (_CAN_ROUTE_RXLOC_LOC3 << 2) /**< Shifted mode LOC3 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC4 (_CAN_ROUTE_RXLOC_LOC4 << 2) /**< Shifted mode LOC4 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC5 (_CAN_ROUTE_RXLOC_LOC5 << 2) /**< Shifted mode LOC5 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC6 (_CAN_ROUTE_RXLOC_LOC6 << 2) /**< Shifted mode LOC6 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC7 (_CAN_ROUTE_RXLOC_LOC7 << 2) /**< Shifted mode LOC7 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_SHIFT 8 /**< Shift value for CAN_TXLOC */
|
||||
#define _CAN_ROUTE_TXLOC_MASK 0x700UL /**< Bit mask for CAN_TXLOC */
|
||||
#define _CAN_ROUTE_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC0 (_CAN_ROUTE_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_DEFAULT (_CAN_ROUTE_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC1 (_CAN_ROUTE_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC2 (_CAN_ROUTE_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC3 (_CAN_ROUTE_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC4 (_CAN_ROUTE_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC5 (_CAN_ROUTE_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC6 (_CAN_ROUTE_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC7 (_CAN_ROUTE_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for CAN_ROUTE */
|
||||
|
||||
/* Bit fields for CAN MIR_CMDMASK */
|
||||
#define _CAN_MIR_CMDMASK_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CMDMASK */
|
||||
#define _CAN_MIR_CMDMASK_MASK 0x000000FFUL /**< Mask for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_DATAB (0x1UL << 0) /**< CC Channel Mode */
|
||||
#define _CAN_MIR_CMDMASK_DATAB_SHIFT 0 /**< Shift value for CAN_DATAB */
|
||||
#define _CAN_MIR_CMDMASK_DATAB_MASK 0x1UL /**< Bit mask for CAN_DATAB */
|
||||
#define _CAN_MIR_CMDMASK_DATAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_DATAB_DEFAULT (_CAN_MIR_CMDMASK_DATAB_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_DATAA (0x1UL << 1) /**< Access Data Bytes 0-3 */
|
||||
#define _CAN_MIR_CMDMASK_DATAA_SHIFT 1 /**< Shift value for CAN_DATAA */
|
||||
#define _CAN_MIR_CMDMASK_DATAA_MASK 0x2UL /**< Bit mask for CAN_DATAA */
|
||||
#define _CAN_MIR_CMDMASK_DATAA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_DATAA_DEFAULT (_CAN_MIR_CMDMASK_DATAA_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_TXRQSTNEWDAT (0x1UL << 2) /**< Transmission Request Bit/ New Data Bit */
|
||||
#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_SHIFT 2 /**< Shift value for CAN_TXRQSTNEWDAT */
|
||||
#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_MASK 0x4UL /**< Bit mask for CAN_TXRQSTNEWDAT */
|
||||
#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT (_CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_CLRINTPND (0x1UL << 3) /**< Clear Interrupt Pending Bit */
|
||||
#define _CAN_MIR_CMDMASK_CLRINTPND_SHIFT 3 /**< Shift value for CAN_CLRINTPND */
|
||||
#define _CAN_MIR_CMDMASK_CLRINTPND_MASK 0x8UL /**< Bit mask for CAN_CLRINTPND */
|
||||
#define _CAN_MIR_CMDMASK_CLRINTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_CLRINTPND_DEFAULT (_CAN_MIR_CMDMASK_CLRINTPND_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_CONTROL (0x1UL << 4) /**< Access Control Bits */
|
||||
#define _CAN_MIR_CMDMASK_CONTROL_SHIFT 4 /**< Shift value for CAN_CONTROL */
|
||||
#define _CAN_MIR_CMDMASK_CONTROL_MASK 0x10UL /**< Bit mask for CAN_CONTROL */
|
||||
#define _CAN_MIR_CMDMASK_CONTROL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_CONTROL_DEFAULT (_CAN_MIR_CMDMASK_CONTROL_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_ARBACC (0x1UL << 5) /**< Access Arbitration Bits */
|
||||
#define _CAN_MIR_CMDMASK_ARBACC_SHIFT 5 /**< Shift value for CAN_ARBACC */
|
||||
#define _CAN_MIR_CMDMASK_ARBACC_MASK 0x20UL /**< Bit mask for CAN_ARBACC */
|
||||
#define _CAN_MIR_CMDMASK_ARBACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_ARBACC_DEFAULT (_CAN_MIR_CMDMASK_ARBACC_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_MASKACC (0x1UL << 6) /**< Access Mask Bits */
|
||||
#define _CAN_MIR_CMDMASK_MASKACC_SHIFT 6 /**< Shift value for CAN_MASKACC */
|
||||
#define _CAN_MIR_CMDMASK_MASKACC_MASK 0x40UL /**< Bit mask for CAN_MASKACC */
|
||||
#define _CAN_MIR_CMDMASK_MASKACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_MASKACC_DEFAULT (_CAN_MIR_CMDMASK_MASKACC_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_WRRD (0x1UL << 7) /**< Write/Read RAM */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_SHIFT 7 /**< Shift value for CAN_WRRD */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_MASK 0x80UL /**< Bit mask for CAN_WRRD */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_READ 0x00000000UL /**< Mode READ for CAN_MIR_CMDMASK */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_WRITE 0x00000001UL /**< Mode WRITE for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_WRRD_DEFAULT (_CAN_MIR_CMDMASK_WRRD_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_WRRD_READ (_CAN_MIR_CMDMASK_WRRD_READ << 7) /**< Shifted mode READ for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_WRRD_WRITE (_CAN_MIR_CMDMASK_WRRD_WRITE << 7) /**< Shifted mode WRITE for CAN_MIR_CMDMASK */
|
||||
|
||||
/* Bit fields for CAN MIR_MASK */
|
||||
#define _CAN_MIR_MASK_RESETVALUE 0xDFFFFFFFUL /**< Default value for CAN_MIR_MASK */
|
||||
#define _CAN_MIR_MASK_MASK 0xDFFFFFFFUL /**< Mask for CAN_MIR_MASK */
|
||||
#define _CAN_MIR_MASK_MASK_SHIFT 0 /**< Shift value for CAN_MASK */
|
||||
#define _CAN_MIR_MASK_MASK_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_MASK */
|
||||
#define _CAN_MIR_MASK_MASK_DEFAULT 0x1FFFFFFFUL /**< Mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MASK_DEFAULT (_CAN_MIR_MASK_MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MDIR (0x1UL << 30) /**< Mask Message Direction */
|
||||
#define _CAN_MIR_MASK_MDIR_SHIFT 30 /**< Shift value for CAN_MDIR */
|
||||
#define _CAN_MIR_MASK_MDIR_MASK 0x40000000UL /**< Bit mask for CAN_MDIR */
|
||||
#define _CAN_MIR_MASK_MDIR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MDIR_DEFAULT (_CAN_MIR_MASK_MDIR_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MXTD (0x1UL << 31) /**< Mask Extended Identifier */
|
||||
#define _CAN_MIR_MASK_MXTD_SHIFT 31 /**< Shift value for CAN_MXTD */
|
||||
#define _CAN_MIR_MASK_MXTD_MASK 0x80000000UL /**< Bit mask for CAN_MXTD */
|
||||
#define _CAN_MIR_MASK_MXTD_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MXTD_DEFAULT (_CAN_MIR_MASK_MXTD_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
|
||||
|
||||
/* Bit fields for CAN MIR_ARB */
|
||||
#define _CAN_MIR_ARB_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_ID_SHIFT 0 /**< Shift value for CAN_ID */
|
||||
#define _CAN_MIR_ARB_ID_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_ID */
|
||||
#define _CAN_MIR_ARB_ID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_ID_DEFAULT (_CAN_MIR_ARB_ID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_DIR (0x1UL << 29) /**< Message Direction */
|
||||
#define _CAN_MIR_ARB_DIR_SHIFT 29 /**< Shift value for CAN_DIR */
|
||||
#define _CAN_MIR_ARB_DIR_MASK 0x20000000UL /**< Bit mask for CAN_DIR */
|
||||
#define _CAN_MIR_ARB_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_DIR_RX 0x00000000UL /**< Mode RX for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_DIR_TX 0x00000001UL /**< Mode TX for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_DIR_DEFAULT (_CAN_MIR_ARB_DIR_DEFAULT << 29) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_DIR_RX (_CAN_MIR_ARB_DIR_RX << 29) /**< Shifted mode RX for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_DIR_TX (_CAN_MIR_ARB_DIR_TX << 29) /**< Shifted mode TX for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_XTD (0x1UL << 30) /**< Extended Identifier */
|
||||
#define _CAN_MIR_ARB_XTD_SHIFT 30 /**< Shift value for CAN_XTD */
|
||||
#define _CAN_MIR_ARB_XTD_MASK 0x40000000UL /**< Bit mask for CAN_XTD */
|
||||
#define _CAN_MIR_ARB_XTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_XTD_STD 0x00000000UL /**< Mode STD for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_XTD_EXT 0x00000001UL /**< Mode EXT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_XTD_DEFAULT (_CAN_MIR_ARB_XTD_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_XTD_STD (_CAN_MIR_ARB_XTD_STD << 30) /**< Shifted mode STD for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_XTD_EXT (_CAN_MIR_ARB_XTD_EXT << 30) /**< Shifted mode EXT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_MSGVAL (0x1UL << 31) /**< Message Valid */
|
||||
#define _CAN_MIR_ARB_MSGVAL_SHIFT 31 /**< Shift value for CAN_MSGVAL */
|
||||
#define _CAN_MIR_ARB_MSGVAL_MASK 0x80000000UL /**< Bit mask for CAN_MSGVAL */
|
||||
#define _CAN_MIR_ARB_MSGVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_MSGVAL_DEFAULT (_CAN_MIR_ARB_MSGVAL_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
|
||||
|
||||
/* Bit fields for CAN MIR_CTRL */
|
||||
#define _CAN_MIR_CTRL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CTRL */
|
||||
#define _CAN_MIR_CTRL_MASK 0x0000FF8FUL /**< Mask for CAN_MIR_CTRL */
|
||||
#define _CAN_MIR_CTRL_DLC_SHIFT 0 /**< Shift value for CAN_DLC */
|
||||
#define _CAN_MIR_CTRL_DLC_MASK 0xFUL /**< Bit mask for CAN_DLC */
|
||||
#define _CAN_MIR_CTRL_DLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_DLC_DEFAULT (_CAN_MIR_CTRL_DLC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_EOB (0x1UL << 7) /**< End of Buffer */
|
||||
#define _CAN_MIR_CTRL_EOB_SHIFT 7 /**< Shift value for CAN_EOB */
|
||||
#define _CAN_MIR_CTRL_EOB_MASK 0x80UL /**< Bit mask for CAN_EOB */
|
||||
#define _CAN_MIR_CTRL_EOB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_EOB_DEFAULT (_CAN_MIR_CTRL_EOB_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_TXRQST (0x1UL << 8) /**< Transmit Request */
|
||||
#define _CAN_MIR_CTRL_TXRQST_SHIFT 8 /**< Shift value for CAN_TXRQST */
|
||||
#define _CAN_MIR_CTRL_TXRQST_MASK 0x100UL /**< Bit mask for CAN_TXRQST */
|
||||
#define _CAN_MIR_CTRL_TXRQST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_TXRQST_DEFAULT (_CAN_MIR_CTRL_TXRQST_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_RMTEN (0x1UL << 9) /**< Remote Enable */
|
||||
#define _CAN_MIR_CTRL_RMTEN_SHIFT 9 /**< Shift value for CAN_RMTEN */
|
||||
#define _CAN_MIR_CTRL_RMTEN_MASK 0x200UL /**< Bit mask for CAN_RMTEN */
|
||||
#define _CAN_MIR_CTRL_RMTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_RMTEN_DEFAULT (_CAN_MIR_CTRL_RMTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_RXIE (0x1UL << 10) /**< Receive Interrupt Enable */
|
||||
#define _CAN_MIR_CTRL_RXIE_SHIFT 10 /**< Shift value for CAN_RXIE */
|
||||
#define _CAN_MIR_CTRL_RXIE_MASK 0x400UL /**< Bit mask for CAN_RXIE */
|
||||
#define _CAN_MIR_CTRL_RXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_RXIE_DEFAULT (_CAN_MIR_CTRL_RXIE_DEFAULT << 10) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_TXIE (0x1UL << 11) /**< Transmit Interrupt Enable */
|
||||
#define _CAN_MIR_CTRL_TXIE_SHIFT 11 /**< Shift value for CAN_TXIE */
|
||||
#define _CAN_MIR_CTRL_TXIE_MASK 0x800UL /**< Bit mask for CAN_TXIE */
|
||||
#define _CAN_MIR_CTRL_TXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_TXIE_DEFAULT (_CAN_MIR_CTRL_TXIE_DEFAULT << 11) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_UMASK (0x1UL << 12) /**< Use Acceptance Mask */
|
||||
#define _CAN_MIR_CTRL_UMASK_SHIFT 12 /**< Shift value for CAN_UMASK */
|
||||
#define _CAN_MIR_CTRL_UMASK_MASK 0x1000UL /**< Bit mask for CAN_UMASK */
|
||||
#define _CAN_MIR_CTRL_UMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_UMASK_DEFAULT (_CAN_MIR_CTRL_UMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_INTPND (0x1UL << 13) /**< Interrupt Pending */
|
||||
#define _CAN_MIR_CTRL_INTPND_SHIFT 13 /**< Shift value for CAN_INTPND */
|
||||
#define _CAN_MIR_CTRL_INTPND_MASK 0x2000UL /**< Bit mask for CAN_INTPND */
|
||||
#define _CAN_MIR_CTRL_INTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_INTPND_DEFAULT (_CAN_MIR_CTRL_INTPND_DEFAULT << 13) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_MESSAGEOF (0x1UL << 14) /**< Message Lost (only Valid for Message Objects With Direction = Receive) */
|
||||
#define _CAN_MIR_CTRL_MESSAGEOF_SHIFT 14 /**< Shift value for CAN_MESSAGEOF */
|
||||
#define _CAN_MIR_CTRL_MESSAGEOF_MASK 0x4000UL /**< Bit mask for CAN_MESSAGEOF */
|
||||
#define _CAN_MIR_CTRL_MESSAGEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_MESSAGEOF_DEFAULT (_CAN_MIR_CTRL_MESSAGEOF_DEFAULT << 14) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_DATAVALID (0x1UL << 15) /**< New Data */
|
||||
#define _CAN_MIR_CTRL_DATAVALID_SHIFT 15 /**< Shift value for CAN_DATAVALID */
|
||||
#define _CAN_MIR_CTRL_DATAVALID_MASK 0x8000UL /**< Bit mask for CAN_DATAVALID */
|
||||
#define _CAN_MIR_CTRL_DATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_DATAVALID_DEFAULT (_CAN_MIR_CTRL_DATAVALID_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
|
||||
/* Bit fields for CAN MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_DATA0_SHIFT 0 /**< Shift value for CAN_DATA0 */
|
||||
#define _CAN_MIR_DATAL_DATA0_MASK 0xFFUL /**< Bit mask for CAN_DATA0 */
|
||||
#define _CAN_MIR_DATAL_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define CAN_MIR_DATAL_DATA0_DEFAULT (_CAN_MIR_DATAL_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_DATA1_SHIFT 8 /**< Shift value for CAN_DATA1 */
|
||||
#define _CAN_MIR_DATAL_DATA1_MASK 0xFF00UL /**< Bit mask for CAN_DATA1 */
|
||||
#define _CAN_MIR_DATAL_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define CAN_MIR_DATAL_DATA1_DEFAULT (_CAN_MIR_DATAL_DATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_DATA2_SHIFT 16 /**< Shift value for CAN_DATA2 */
|
||||
#define _CAN_MIR_DATAL_DATA2_MASK 0xFF0000UL /**< Bit mask for CAN_DATA2 */
|
||||
#define _CAN_MIR_DATAL_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define CAN_MIR_DATAL_DATA2_DEFAULT (_CAN_MIR_DATAL_DATA2_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_DATA3_SHIFT 24 /**< Shift value for CAN_DATA3 */
|
||||
#define _CAN_MIR_DATAL_DATA3_MASK 0xFF000000UL /**< Bit mask for CAN_DATA3 */
|
||||
#define _CAN_MIR_DATAL_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define CAN_MIR_DATAL_DATA3_DEFAULT (_CAN_MIR_DATAL_DATA3_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
|
||||
|
||||
/* Bit fields for CAN MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_DATA4_SHIFT 0 /**< Shift value for CAN_DATA4 */
|
||||
#define _CAN_MIR_DATAH_DATA4_MASK 0xFFUL /**< Bit mask for CAN_DATA4 */
|
||||
#define _CAN_MIR_DATAH_DATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define CAN_MIR_DATAH_DATA4_DEFAULT (_CAN_MIR_DATAH_DATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_DATA5_SHIFT 8 /**< Shift value for CAN_DATA5 */
|
||||
#define _CAN_MIR_DATAH_DATA5_MASK 0xFF00UL /**< Bit mask for CAN_DATA5 */
|
||||
#define _CAN_MIR_DATAH_DATA5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define CAN_MIR_DATAH_DATA5_DEFAULT (_CAN_MIR_DATAH_DATA5_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_DATA6_SHIFT 16 /**< Shift value for CAN_DATA6 */
|
||||
#define _CAN_MIR_DATAH_DATA6_MASK 0xFF0000UL /**< Bit mask for CAN_DATA6 */
|
||||
#define _CAN_MIR_DATAH_DATA6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define CAN_MIR_DATAH_DATA6_DEFAULT (_CAN_MIR_DATAH_DATA6_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_DATA7_SHIFT 24 /**< Shift value for CAN_DATA7 */
|
||||
#define _CAN_MIR_DATAH_DATA7_MASK 0xFF000000UL /**< Bit mask for CAN_DATA7 */
|
||||
#define _CAN_MIR_DATAH_DATA7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define CAN_MIR_DATAH_DATA7_DEFAULT (_CAN_MIR_DATAH_DATA7_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
|
||||
|
||||
/* Bit fields for CAN MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_RESETVALUE 0x00000001UL /**< Default value for CAN_MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_MASK 0x0000803FUL /**< Mask for CAN_MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_MSGNUM_SHIFT 0 /**< Shift value for CAN_MSGNUM */
|
||||
#define _CAN_MIR_CMDREQ_MSGNUM_MASK 0x3FUL /**< Bit mask for CAN_MSGNUM */
|
||||
#define _CAN_MIR_CMDREQ_MSGNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_MSGNUM_DEFAULT (_CAN_MIR_CMDREQ_MSGNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_BUSY (0x1UL << 15) /**< Busy Flag */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_SHIFT 15 /**< Shift value for CAN_BUSY */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_MASK 0x8000UL /**< Bit mask for CAN_BUSY */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_FALSE 0x00000000UL /**< Mode FALSE for CAN_MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_TRUE 0x00000001UL /**< Mode TRUE for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_BUSY_DEFAULT (_CAN_MIR_CMDREQ_BUSY_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_BUSY_FALSE (_CAN_MIR_CMDREQ_BUSY_FALSE << 15) /**< Shifted mode FALSE for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_BUSY_TRUE (_CAN_MIR_CMDREQ_BUSY_TRUE << 15) /**< Shifted mode TRUE for CAN_MIR_CMDREQ */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_CAN */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
65
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can_mir.h
vendored
Normal file
65
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can_mir.h
vendored
Normal file
@ -0,0 +1,65 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_CAN_MIR register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief CAN_MIR CAN MIR Register
|
||||
* @ingroup EFM32GG11B_CAN
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CMDMASK; /**< Interface Command Mask Register */
|
||||
__IOM uint32_t MASK; /**< Interface Mask Register */
|
||||
__IOM uint32_t ARB; /**< Interface Arbitration Register */
|
||||
__IOM uint32_t CTRL; /**< Interface Message Control Register */
|
||||
__IOM uint32_t DATAL; /**< Interface Data a Register */
|
||||
__IOM uint32_t DATAH; /**< Interface Data B Register */
|
||||
__IOM uint32_t CMDREQ; /**< Interface Command Request Register */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved future */
|
||||
} CAN_MIR_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
2698
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cmu.h
vendored
Normal file
2698
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cmu.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
183
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cryotimer.h
vendored
Normal file
183
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cryotimer.h
vendored
Normal file
@ -0,0 +1,183 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_CRYOTIMER register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_CRYOTIMER CRYOTIMER
|
||||
* @{
|
||||
* @brief EFM32GG11B_CRYOTIMER Register Declaration
|
||||
******************************************************************************/
|
||||
/** CRYOTIMER Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t PERIODSEL; /**< Interrupt Duration */
|
||||
__IM uint32_t CNT; /**< Counter Value */
|
||||
__IOM uint32_t EM4WUEN; /**< Wake Up Enable */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} CRYOTIMER_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_CRYOTIMER
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_CRYOTIMER_BitFields CRYOTIMER Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for CRYOTIMER CTRL */
|
||||
#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */
|
||||
#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */
|
||||
#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */
|
||||
#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
|
||||
#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */
|
||||
#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */
|
||||
#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */
|
||||
#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */
|
||||
|
||||
/* Bit fields for CRYOTIMER PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */
|
||||
#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */
|
||||
|
||||
/* Bit fields for CRYOTIMER CNT */
|
||||
#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */
|
||||
#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */
|
||||
#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */
|
||||
#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */
|
||||
#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */
|
||||
#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */
|
||||
|
||||
/* Bit fields for CRYOTIMER EM4WUEN */
|
||||
#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */
|
||||
#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */
|
||||
#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
|
||||
#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */
|
||||
|
||||
/* Bit fields for CRYOTIMER IF */
|
||||
#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */
|
||||
#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */
|
||||
#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup Event/Interrupt */
|
||||
#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */
|
||||
#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */
|
||||
|
||||
/* Bit fields for CRYOTIMER IFS */
|
||||
#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */
|
||||
#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */
|
||||
#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */
|
||||
#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */
|
||||
#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */
|
||||
|
||||
/* Bit fields for CRYOTIMER IFC */
|
||||
#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */
|
||||
#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */
|
||||
#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */
|
||||
#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */
|
||||
#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */
|
||||
|
||||
/* Bit fields for CRYOTIMER IEN */
|
||||
#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */
|
||||
#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */
|
||||
#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */
|
||||
#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */
|
||||
#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_CRYOTIMER */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
1218
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_crypto.h
vendored
Normal file
1218
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_crypto.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1010
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_csen.h
vendored
Normal file
1010
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_csen.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1798
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_devinfo.h
vendored
Normal file
1798
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_devinfo.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
64
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dma_descriptor.h
vendored
Normal file
64
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dma_descriptor.h
vendored
Normal file
@ -0,0 +1,64 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_DMA_DESCRIPTOR register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_DMA_DESCRIPTOR DMA Descriptor
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/** DMA_DESCRIPTOR Register Declaration */
|
||||
typedef struct {
|
||||
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
|
||||
/* pointer and referenced memory are declared volatile. */
|
||||
__IOM uint32_t CTRL; /**< DMA control register */
|
||||
__IOM void * __IOM SRC; /**< DMA source address */
|
||||
__IOM void * __IOM DST; /**< DMA destination address */
|
||||
__IOM void * __IOM LINK; /**< DMA link address */
|
||||
} DMA_DESCRIPTOR_TypeDef; /**< @} */
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
171
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dmareq.h
vendored
Normal file
171
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dmareq.h
vendored
Normal file
@ -0,0 +1,171 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_DMAREQ register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_DMAREQ DMAREQ
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_DMAREQ_BitFields DMAREQ Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
|
||||
#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
|
||||
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
|
||||
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
|
||||
#define DMAREQ_ADC1_SINGLE ((9 << 16) + 0) /**< DMA channel select for ADC1_SINGLE */
|
||||
#define DMAREQ_ADC1_SCAN ((9 << 16) + 1) /**< DMA channel select for ADC1_SCAN */
|
||||
#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */
|
||||
#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */
|
||||
#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
|
||||
#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
|
||||
#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
|
||||
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
|
||||
#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
|
||||
#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
|
||||
#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
|
||||
#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
|
||||
#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
|
||||
#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
|
||||
#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
|
||||
#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */
|
||||
#define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */
|
||||
#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */
|
||||
#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */
|
||||
#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */
|
||||
#define DMAREQ_USART4_RXDATAV ((16 << 16) + 0) /**< DMA channel select for USART4_RXDATAV */
|
||||
#define DMAREQ_USART4_TXBL ((16 << 16) + 1) /**< DMA channel select for USART4_TXBL */
|
||||
#define DMAREQ_USART4_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for USART4_TXEMPTY */
|
||||
#define DMAREQ_USART4_RXDATAVRIGHT ((16 << 16) + 3) /**< DMA channel select for USART4_RXDATAVRIGHT */
|
||||
#define DMAREQ_USART4_TXBLRIGHT ((16 << 16) + 4) /**< DMA channel select for USART4_TXBLRIGHT */
|
||||
#define DMAREQ_USART5_RXDATAV ((17 << 16) + 0) /**< DMA channel select for USART5_RXDATAV */
|
||||
#define DMAREQ_USART5_TXBL ((17 << 16) + 1) /**< DMA channel select for USART5_TXBL */
|
||||
#define DMAREQ_USART5_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for USART5_TXEMPTY */
|
||||
#define DMAREQ_UART0_RXDATAV ((18 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
|
||||
#define DMAREQ_UART0_TXBL ((18 << 16) + 1) /**< DMA channel select for UART0_TXBL */
|
||||
#define DMAREQ_UART0_TXEMPTY ((18 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
|
||||
#define DMAREQ_UART1_RXDATAV ((19 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
|
||||
#define DMAREQ_UART1_TXBL ((19 << 16) + 1) /**< DMA channel select for UART1_TXBL */
|
||||
#define DMAREQ_UART1_TXEMPTY ((19 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
|
||||
#define DMAREQ_LEUART0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
|
||||
#define DMAREQ_LEUART0_TXBL ((20 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
|
||||
#define DMAREQ_LEUART0_TXEMPTY ((20 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
|
||||
#define DMAREQ_LEUART1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
|
||||
#define DMAREQ_LEUART1_TXBL ((21 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
|
||||
#define DMAREQ_LEUART1_TXEMPTY ((21 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
|
||||
#define DMAREQ_I2C0_RXDATAV ((22 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
|
||||
#define DMAREQ_I2C0_TXBL ((22 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
|
||||
#define DMAREQ_I2C1_RXDATAV ((23 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
|
||||
#define DMAREQ_I2C1_TXBL ((23 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
|
||||
#define DMAREQ_I2C2_RXDATAV ((24 << 16) + 0) /**< DMA channel select for I2C2_RXDATAV */
|
||||
#define DMAREQ_I2C2_TXBL ((24 << 16) + 1) /**< DMA channel select for I2C2_TXBL */
|
||||
#define DMAREQ_TIMER0_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
|
||||
#define DMAREQ_TIMER0_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
|
||||
#define DMAREQ_TIMER0_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
|
||||
#define DMAREQ_TIMER0_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
|
||||
#define DMAREQ_TIMER1_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
|
||||
#define DMAREQ_TIMER1_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
|
||||
#define DMAREQ_TIMER1_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
|
||||
#define DMAREQ_TIMER1_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
|
||||
#define DMAREQ_TIMER1_CC3 ((26 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
|
||||
#define DMAREQ_TIMER2_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
|
||||
#define DMAREQ_TIMER2_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
|
||||
#define DMAREQ_TIMER2_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
|
||||
#define DMAREQ_TIMER2_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
|
||||
#define DMAREQ_TIMER3_UFOF ((28 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
|
||||
#define DMAREQ_TIMER3_CC0 ((28 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
|
||||
#define DMAREQ_TIMER3_CC1 ((28 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
|
||||
#define DMAREQ_TIMER3_CC2 ((28 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
|
||||
#define DMAREQ_TIMER4_UFOF ((29 << 16) + 0) /**< DMA channel select for TIMER4_UFOF */
|
||||
#define DMAREQ_TIMER4_CC0 ((29 << 16) + 1) /**< DMA channel select for TIMER4_CC0 */
|
||||
#define DMAREQ_TIMER4_CC1 ((29 << 16) + 2) /**< DMA channel select for TIMER4_CC1 */
|
||||
#define DMAREQ_TIMER4_CC2 ((29 << 16) + 3) /**< DMA channel select for TIMER4_CC2 */
|
||||
#define DMAREQ_TIMER5_UFOF ((30 << 16) + 0) /**< DMA channel select for TIMER5_UFOF */
|
||||
#define DMAREQ_TIMER5_CC0 ((30 << 16) + 1) /**< DMA channel select for TIMER5_CC0 */
|
||||
#define DMAREQ_TIMER5_CC1 ((30 << 16) + 2) /**< DMA channel select for TIMER5_CC1 */
|
||||
#define DMAREQ_TIMER5_CC2 ((30 << 16) + 3) /**< DMA channel select for TIMER5_CC2 */
|
||||
#define DMAREQ_TIMER6_UFOF ((31 << 16) + 0) /**< DMA channel select for TIMER6_UFOF */
|
||||
#define DMAREQ_TIMER6_CC0 ((31 << 16) + 1) /**< DMA channel select for TIMER6_CC0 */
|
||||
#define DMAREQ_TIMER6_CC1 ((31 << 16) + 2) /**< DMA channel select for TIMER6_CC1 */
|
||||
#define DMAREQ_TIMER6_CC2 ((31 << 16) + 3) /**< DMA channel select for TIMER6_CC2 */
|
||||
#define DMAREQ_WTIMER0_UFOF ((32 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */
|
||||
#define DMAREQ_WTIMER0_CC0 ((32 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */
|
||||
#define DMAREQ_WTIMER0_CC1 ((32 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */
|
||||
#define DMAREQ_WTIMER0_CC2 ((32 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */
|
||||
#define DMAREQ_WTIMER1_UFOF ((33 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */
|
||||
#define DMAREQ_WTIMER1_CC0 ((33 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */
|
||||
#define DMAREQ_WTIMER1_CC1 ((33 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */
|
||||
#define DMAREQ_WTIMER1_CC2 ((33 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */
|
||||
#define DMAREQ_WTIMER1_CC3 ((33 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */
|
||||
#define DMAREQ_WTIMER2_UFOF ((34 << 16) + 0) /**< DMA channel select for WTIMER2_UFOF */
|
||||
#define DMAREQ_WTIMER2_CC0 ((34 << 16) + 1) /**< DMA channel select for WTIMER2_CC0 */
|
||||
#define DMAREQ_WTIMER2_CC1 ((34 << 16) + 2) /**< DMA channel select for WTIMER2_CC1 */
|
||||
#define DMAREQ_WTIMER2_CC2 ((34 << 16) + 3) /**< DMA channel select for WTIMER2_CC2 */
|
||||
#define DMAREQ_WTIMER3_UFOF ((35 << 16) + 0) /**< DMA channel select for WTIMER3_UFOF */
|
||||
#define DMAREQ_WTIMER3_CC0 ((35 << 16) + 1) /**< DMA channel select for WTIMER3_CC0 */
|
||||
#define DMAREQ_WTIMER3_CC1 ((35 << 16) + 2) /**< DMA channel select for WTIMER3_CC1 */
|
||||
#define DMAREQ_WTIMER3_CC2 ((35 << 16) + 3) /**< DMA channel select for WTIMER3_CC2 */
|
||||
#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
|
||||
#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */
|
||||
#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */
|
||||
#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */
|
||||
#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */
|
||||
#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */
|
||||
#define DMAREQ_EBI_PXL0EMPTY ((50 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
|
||||
#define DMAREQ_EBI_PXL1EMPTY ((50 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
|
||||
#define DMAREQ_EBI_PXLFULL ((50 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
|
||||
#define DMAREQ_EBI_DDEMPTY ((50 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
|
||||
#define DMAREQ_EBI_VSYNC ((50 << 16) + 4) /**< DMA channel select for EBI_VSYNC */
|
||||
#define DMAREQ_EBI_HSYNC ((50 << 16) + 5) /**< DMA channel select for EBI_HSYNC */
|
||||
#define DMAREQ_CSEN_DATA ((61 << 16) + 0) /**< DMA channel select for CSEN_DATA */
|
||||
#define DMAREQ_CSEN_BSLN ((61 << 16) + 1) /**< DMA channel select for CSEN_BSLN */
|
||||
#define DMAREQ_LESENSE_BUFDATAV ((62 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_DMAREQ */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
1712
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ebi.h
vendored
Normal file
1712
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ebi.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_emu.h
vendored
Normal file
1978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_emu.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
2365
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_eth.h
vendored
Normal file
2365
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_eth.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
797
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_etm.h
vendored
Normal file
797
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_etm.h
vendored
Normal file
@ -0,0 +1,797 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_ETM register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_ETM ETM
|
||||
* @{
|
||||
* @brief EFM32GG11B_ETM Register Declaration
|
||||
******************************************************************************/
|
||||
/** ETM Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t ETMCR; /**< Main Control Register */
|
||||
__IM uint32_t ETMCCR; /**< Configuration Code Register */
|
||||
__IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMSR; /**< ETM Status Register */
|
||||
__IM uint32_t ETMSCR; /**< ETM System Configuration Register */
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
|
||||
__IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
|
||||
uint32_t RESERVED3[68U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
|
||||
uint32_t RESERVED4[39U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
|
||||
__IM uint32_t ETMIDR; /**< ID Register */
|
||||
__IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
|
||||
uint32_t RESERVED5[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
|
||||
uint32_t RESERVED6[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
|
||||
uint32_t RESERVED7[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
|
||||
uint32_t RESERVED8[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
|
||||
uint32_t RESERVED9[66U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
|
||||
uint32_t RESERVED10[754U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
|
||||
uint32_t RESERVED11[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
|
||||
uint32_t RESERVED12[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
|
||||
uint32_t RESERVED13[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
|
||||
uint32_t RESERVED14[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
|
||||
uint32_t RESERVED15[39U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
|
||||
__IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
|
||||
uint32_t RESERVED16[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
|
||||
__IM uint32_t ETMLSR; /**< Lock Status Register */
|
||||
__IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
|
||||
uint32_t RESERVED17[4U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
|
||||
__IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
|
||||
__OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
|
||||
__OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
|
||||
__OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
|
||||
__IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
|
||||
__IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
|
||||
__IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
|
||||
__IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
|
||||
__IM uint32_t ETMCIDR0; /**< Component ID0 Register */
|
||||
__IM uint32_t ETMCIDR1; /**< Component ID1 Register */
|
||||
__IM uint32_t ETMCIDR2; /**< Component ID2 Register */
|
||||
__IM uint32_t ETMCIDR3; /**< Component ID3 Register */
|
||||
} ETM_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_ETM
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_ETM_BitFields ETM Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for ETM ETMCR */
|
||||
#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
|
||||
#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
|
||||
#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
|
||||
#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
|
||||
#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
|
||||
#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
|
||||
#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
|
||||
#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
|
||||
#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
|
||||
#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
|
||||
#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
|
||||
#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
|
||||
#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
|
||||
#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
|
||||
#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
|
||||
#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
|
||||
#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
|
||||
#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
|
||||
#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
|
||||
#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
|
||||
#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
|
||||
#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
|
||||
#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
|
||||
#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
|
||||
#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
|
||||
#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
|
||||
#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
|
||||
#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
|
||||
#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
|
||||
#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
|
||||
/* Bit fields for ETM ETMCCR */
|
||||
#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
|
||||
#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
|
||||
#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
|
||||
#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
|
||||
#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
|
||||
#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
|
||||
#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
|
||||
#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
|
||||
#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
|
||||
#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
|
||||
#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
|
||||
#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
|
||||
#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
|
||||
#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
|
||||
#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
|
||||
#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
|
||||
#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
|
||||
#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
|
||||
#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
|
||||
#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
|
||||
#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
|
||||
#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
|
||||
#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
|
||||
#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
|
||||
#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
|
||||
#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
|
||||
#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
|
||||
#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
|
||||
/* Bit fields for ETM ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
|
||||
#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
|
||||
#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
|
||||
#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
|
||||
#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
|
||||
#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
|
||||
#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
|
||||
|
||||
/* Bit fields for ETM ETMSR */
|
||||
#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
|
||||
#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
|
||||
#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
|
||||
#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
|
||||
#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
|
||||
#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
|
||||
#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
|
||||
#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
|
||||
#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
|
||||
#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
|
||||
#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
|
||||
#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
|
||||
#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
|
||||
#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
|
||||
#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
|
||||
|
||||
/* Bit fields for ETM ETMSCR */
|
||||
#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
|
||||
#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
|
||||
#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
|
||||
#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
|
||||
#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
|
||||
#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
|
||||
#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
|
||||
#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
|
||||
#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
|
||||
#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
|
||||
#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
|
||||
#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
|
||||
#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
|
||||
#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
|
||||
#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
|
||||
#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
|
||||
/* Bit fields for ETM ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
|
||||
#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
|
||||
#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
|
||||
#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
|
||||
#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
|
||||
#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
|
||||
#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
|
||||
|
||||
/* Bit fields for ETM ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
|
||||
#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
|
||||
#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
|
||||
#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
|
||||
#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
|
||||
#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
|
||||
#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
|
||||
#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
|
||||
|
||||
/* Bit fields for ETM ETMFFLR */
|
||||
#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
|
||||
#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
|
||||
#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
|
||||
#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
|
||||
#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
|
||||
#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
|
||||
|
||||
/* Bit fields for ETM ETMCNTRLDVR1 */
|
||||
#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
|
||||
#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
|
||||
#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
|
||||
#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
|
||||
#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
|
||||
#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
|
||||
|
||||
/* Bit fields for ETM ETMSYNCFR */
|
||||
#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
|
||||
#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
|
||||
#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
|
||||
#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
|
||||
#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
|
||||
#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
|
||||
|
||||
/* Bit fields for ETM ETMIDR */
|
||||
#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
|
||||
#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
|
||||
#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
|
||||
#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
|
||||
#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
|
||||
#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
|
||||
#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
|
||||
#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
|
||||
#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
|
||||
#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
|
||||
#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
|
||||
#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
|
||||
#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
|
||||
#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
|
||||
#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
|
||||
#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
|
||||
#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
|
||||
#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
|
||||
#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
|
||||
#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
|
||||
#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
|
||||
#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
|
||||
#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
|
||||
/* Bit fields for ETM ETMCCER */
|
||||
#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
|
||||
#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
|
||||
#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
|
||||
#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
|
||||
#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
|
||||
#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
|
||||
#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
|
||||
#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
|
||||
#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
|
||||
#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
|
||||
#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
|
||||
#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
|
||||
#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
|
||||
#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
|
||||
#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
|
||||
#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
|
||||
#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
|
||||
#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
|
||||
#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
|
||||
#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
|
||||
#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
|
||||
#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
|
||||
#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
|
||||
#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
|
||||
#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
|
||||
#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
|
||||
#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
|
||||
#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
|
||||
#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
|
||||
#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
|
||||
#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
|
||||
#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
|
||||
#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
|
||||
/* Bit fields for ETM ETMTESSEICR */
|
||||
#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
|
||||
#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
|
||||
#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
|
||||
#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
|
||||
#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
|
||||
#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
|
||||
#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
|
||||
#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
|
||||
#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
|
||||
#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
|
||||
|
||||
/* Bit fields for ETM ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
|
||||
#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
|
||||
#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
|
||||
#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
|
||||
#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
|
||||
#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
|
||||
#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
|
||||
|
||||
/* Bit fields for ETM ETMTRACEIDR */
|
||||
#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
|
||||
#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
|
||||
#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
|
||||
#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
|
||||
#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
|
||||
#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
|
||||
|
||||
/* Bit fields for ETM ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
|
||||
#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
|
||||
#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
|
||||
#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
|
||||
#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
|
||||
#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
|
||||
#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
|
||||
|
||||
/* Bit fields for ETM ETMPDSR */
|
||||
#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
|
||||
#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
|
||||
#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
|
||||
#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
|
||||
#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
|
||||
#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
|
||||
#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
|
||||
|
||||
/* Bit fields for ETM ETMISCIN */
|
||||
#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
|
||||
#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
|
||||
#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
|
||||
#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
|
||||
#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
|
||||
#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
|
||||
#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
|
||||
#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
|
||||
#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
|
||||
#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
|
||||
#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
|
||||
|
||||
/* Bit fields for ETM ITTRIGOUT */
|
||||
#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
|
||||
#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
|
||||
#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
|
||||
#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
|
||||
#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
|
||||
#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
|
||||
#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
|
||||
|
||||
/* Bit fields for ETM ETMITATBCTR2 */
|
||||
#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
|
||||
#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
|
||||
#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
|
||||
#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
|
||||
#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
|
||||
#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
|
||||
#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
|
||||
|
||||
/* Bit fields for ETM ETMITATBCTR0 */
|
||||
#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
|
||||
#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
|
||||
#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
|
||||
#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
|
||||
#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
|
||||
#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
|
||||
#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
|
||||
|
||||
/* Bit fields for ETM ETMITCTRL */
|
||||
#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
|
||||
#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
|
||||
#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
|
||||
#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
|
||||
#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
|
||||
#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
|
||||
#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
|
||||
|
||||
/* Bit fields for ETM ETMCLAIMSET */
|
||||
#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
|
||||
#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
|
||||
#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
|
||||
#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
|
||||
#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
|
||||
#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
|
||||
|
||||
/* Bit fields for ETM ETMCLAIMCLR */
|
||||
#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
|
||||
#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
|
||||
#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
|
||||
#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
|
||||
#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
|
||||
#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
|
||||
#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
|
||||
|
||||
/* Bit fields for ETM ETMLAR */
|
||||
#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
|
||||
#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
|
||||
#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
|
||||
#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
|
||||
#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
|
||||
#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
|
||||
#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
|
||||
|
||||
/* Bit fields for ETM ETMLSR */
|
||||
#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
|
||||
#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
|
||||
#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
|
||||
#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
|
||||
#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
|
||||
#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
|
||||
#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
|
||||
#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
|
||||
#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
|
||||
#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
|
||||
#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
|
||||
#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
|
||||
|
||||
/* Bit fields for ETM ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
|
||||
/* Bit fields for ETM ETMDEVTYPE */
|
||||
#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
|
||||
#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
|
||||
#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
|
||||
#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
|
||||
#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
|
||||
#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
|
||||
#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
|
||||
#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
|
||||
#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
|
||||
#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR4 */
|
||||
#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
|
||||
#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
|
||||
#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
|
||||
#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
|
||||
#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
|
||||
#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
|
||||
#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
|
||||
#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
|
||||
#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
|
||||
#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR5 */
|
||||
#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
|
||||
#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR6 */
|
||||
#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
|
||||
#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR7 */
|
||||
#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
|
||||
#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR0 */
|
||||
#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */
|
||||
#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
|
||||
#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
|
||||
#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
|
||||
#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
|
||||
#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR1 */
|
||||
#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
|
||||
#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
|
||||
#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
|
||||
#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
|
||||
#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
|
||||
#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
|
||||
#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
|
||||
#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
|
||||
#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
|
||||
#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR2 */
|
||||
#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */
|
||||
#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
|
||||
#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
|
||||
#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
|
||||
#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
|
||||
#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
|
||||
#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
|
||||
#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
|
||||
#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
|
||||
#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR3 */
|
||||
#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
|
||||
#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
|
||||
#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
|
||||
#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
|
||||
#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
|
||||
#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
|
||||
#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
|
||||
#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
|
||||
#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
|
||||
#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
|
||||
|
||||
/* Bit fields for ETM ETMCIDR0 */
|
||||
#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
|
||||
#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
|
||||
#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
|
||||
#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
|
||||
|
||||
/* Bit fields for ETM ETMCIDR1 */
|
||||
#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
|
||||
#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
|
||||
#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
|
||||
#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
|
||||
|
||||
/* Bit fields for ETM ETMCIDR2 */
|
||||
#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
|
||||
#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
|
||||
#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
|
||||
#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
|
||||
|
||||
/* Bit fields for ETM ETMCIDR3 */
|
||||
#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
|
||||
#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
|
||||
#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
|
||||
#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_ETM */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
208
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_fpueh.h
vendored
Normal file
208
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_fpueh.h
vendored
Normal file
@ -0,0 +1,208 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_FPUEH register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_FPUEH FPUEH
|
||||
* @{
|
||||
* @brief EFM32GG11B_FPUEH Register Declaration
|
||||
******************************************************************************/
|
||||
/** FPUEH Register Declaration */
|
||||
typedef struct {
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} FPUEH_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_FPUEH
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_FPUEH_BitFields FPUEH Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for FPUEH IF */
|
||||
#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
|
||||
#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
|
||||
#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
|
||||
#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
|
||||
#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
|
||||
#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
|
||||
#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
|
||||
#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
|
||||
#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
|
||||
#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
|
||||
#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
|
||||
#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
|
||||
#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
|
||||
#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
|
||||
#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
|
||||
#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
|
||||
#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
|
||||
#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
|
||||
#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
|
||||
#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
|
||||
/* Bit fields for FPUEH IFS */
|
||||
#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
|
||||
#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
|
||||
#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
|
||||
#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
|
||||
#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
|
||||
#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
|
||||
#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
|
||||
#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
|
||||
#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
|
||||
#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
|
||||
#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
|
||||
#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
|
||||
#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
|
||||
#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
|
||||
/* Bit fields for FPUEH IFC */
|
||||
#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
|
||||
#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
|
||||
#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
|
||||
#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
|
||||
#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
|
||||
#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
|
||||
#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
|
||||
#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
|
||||
#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
|
||||
#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
|
||||
#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
|
||||
#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
|
||||
#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
|
||||
#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
|
||||
/* Bit fields for FPUEH IEN */
|
||||
#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
|
||||
#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
|
||||
#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
|
||||
#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
|
||||
#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
|
||||
#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
|
||||
#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
|
||||
#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
|
||||
#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
|
||||
#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
|
||||
#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
|
||||
#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
|
||||
#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
|
||||
#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_FPUEH */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
201
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpcrc.h
vendored
Normal file
201
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpcrc.h
vendored
Normal file
@ -0,0 +1,201 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_GPCRC register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_GPCRC GPCRC
|
||||
* @{
|
||||
* @brief EFM32GG11B_GPCRC Register Declaration
|
||||
******************************************************************************/
|
||||
/** GPCRC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IOM uint32_t INIT; /**< CRC Init Value */
|
||||
__IOM uint32_t POLY; /**< CRC Polynomial Value */
|
||||
__IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */
|
||||
__IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */
|
||||
__IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */
|
||||
__IM uint32_t DATA; /**< CRC Data Register */
|
||||
__IM uint32_t DATAREV; /**< CRC Data Reverse Register */
|
||||
__IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
|
||||
} GPCRC_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_GPCRC
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_GPCRC_BitFields GPCRC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for GPCRC CTRL */
|
||||
#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */
|
||||
#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */
|
||||
#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */
|
||||
#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */
|
||||
#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */
|
||||
#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */
|
||||
#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */
|
||||
#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */
|
||||
#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */
|
||||
#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */
|
||||
#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */
|
||||
#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */
|
||||
#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */
|
||||
#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */
|
||||
#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */
|
||||
#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
|
||||
/* Bit fields for GPCRC CMD */
|
||||
#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */
|
||||
#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */
|
||||
#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */
|
||||
#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
|
||||
#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */
|
||||
#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */
|
||||
#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
|
||||
|
||||
/* Bit fields for GPCRC INIT */
|
||||
#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */
|
||||
#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */
|
||||
#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
|
||||
#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */
|
||||
#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */
|
||||
#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
|
||||
|
||||
/* Bit fields for GPCRC POLY */
|
||||
#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */
|
||||
#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */
|
||||
#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */
|
||||
#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */
|
||||
#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */
|
||||
#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
|
||||
|
||||
/* Bit fields for GPCRC INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */
|
||||
#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
|
||||
|
||||
/* Bit fields for GPCRC INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
|
||||
#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */
|
||||
|
||||
/* Bit fields for GPCRC INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
|
||||
#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */
|
||||
|
||||
/* Bit fields for GPCRC DATA */
|
||||
#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */
|
||||
#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */
|
||||
#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */
|
||||
#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */
|
||||
#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */
|
||||
#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
|
||||
|
||||
/* Bit fields for GPCRC DATAREV */
|
||||
#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */
|
||||
#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */
|
||||
#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */
|
||||
#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */
|
||||
#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */
|
||||
#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
|
||||
|
||||
/* Bit fields for GPCRC DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
|
||||
#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_GPCRC */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
1557
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio.h
vendored
Normal file
1557
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
68
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio_p.h
vendored
Normal file
68
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio_p.h
vendored
Normal file
@ -0,0 +1,68 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_GPIO_P register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief GPIO_P GPIO P Register
|
||||
* @ingroup EFM32GG11B_GPIO
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Port Control Register */
|
||||
__IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
|
||||
__IOM uint32_t MODEH; /**< Port Pin Mode High Register */
|
||||
__IOM uint32_t DOUT; /**< Port Data Out Register */
|
||||
uint32_t RESERVED0[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
|
||||
__IM uint32_t DIN; /**< Port Data in Register */
|
||||
__IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
|
||||
uint32_t RESERVED1[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t OVTDIS; /**< Over Voltage Disable for All Modes */
|
||||
uint32_t RESERVED2[1U]; /**< Reserved future */
|
||||
} GPIO_P_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
841
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_i2c.h
vendored
Normal file
841
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_i2c.h
vendored
Normal file
@ -0,0 +1,841 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_I2C register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_I2C I2C
|
||||
* @{
|
||||
* @brief EFM32GG11B_I2C Register Declaration
|
||||
******************************************************************************/
|
||||
/** I2C Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATE; /**< State Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CLKDIV; /**< Clock Division Register */
|
||||
__IOM uint32_t SADDR; /**< Slave Address Register */
|
||||
__IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
|
||||
__IM uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
|
||||
__IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
|
||||
__IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
|
||||
__IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
} I2C_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_I2C
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_I2C_BitFields I2C Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for I2C CTRL */
|
||||
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
|
||||
#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */
|
||||
#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
|
||||
#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
|
||||
#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
|
||||
#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
|
||||
#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
|
||||
#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
|
||||
#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
|
||||
#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
|
||||
#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
|
||||
#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP When Empty */
|
||||
#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
|
||||
#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
|
||||
#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
|
||||
#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
|
||||
#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
|
||||
#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
|
||||
#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
|
||||
#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
|
||||
#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
|
||||
#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
|
||||
#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
|
||||
#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
|
||||
#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
|
||||
#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
|
||||
#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
|
||||
#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */
|
||||
#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
|
||||
#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
|
||||
#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
|
||||
#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
|
||||
#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
|
||||
#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
|
||||
#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */
|
||||
|
||||
/* Bit fields for I2C CMD */
|
||||
#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
|
||||
#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
|
||||
#define I2C_CMD_START (0x1UL << 0) /**< Send Start Condition */
|
||||
#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_STOP (0x1UL << 1) /**< Send Stop Condition */
|
||||
#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
|
||||
#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
|
||||
#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
|
||||
#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
|
||||
#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CONT (0x1UL << 4) /**< Continue Transmission */
|
||||
#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
|
||||
#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
|
||||
#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort Transmission */
|
||||
#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
|
||||
#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
|
||||
#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
|
||||
#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
|
||||
#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
|
||||
#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
|
||||
#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
|
||||
#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
|
||||
#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
|
||||
/* Bit fields for I2C STATE */
|
||||
#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
|
||||
#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
|
||||
#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
|
||||
#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
|
||||
#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
|
||||
#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
|
||||
#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
|
||||
#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
|
||||
#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
|
||||
#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
|
||||
#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
|
||||
#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
|
||||
#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
|
||||
#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
|
||||
#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
|
||||
#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
|
||||
#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
|
||||
#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
|
||||
#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
|
||||
#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
|
||||
|
||||
/* Bit fields for I2C STATUS */
|
||||
#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
|
||||
#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
|
||||
#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
|
||||
#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
|
||||
#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
|
||||
#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
|
||||
#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
|
||||
#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
|
||||
#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
|
||||
#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
|
||||
#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
|
||||
#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
|
||||
#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
|
||||
#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending Continue */
|
||||
#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
|
||||
#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
|
||||
#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending Abort */
|
||||
#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
|
||||
#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
|
||||
#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
|
||||
#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
|
||||
#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
|
||||
#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
|
||||
#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
|
||||
/* Bit fields for I2C CLKDIV */
|
||||
#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
|
||||
#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
|
||||
#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
|
||||
#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
|
||||
#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
|
||||
#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
|
||||
|
||||
/* Bit fields for I2C SADDR */
|
||||
#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
|
||||
#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
|
||||
#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
|
||||
#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
|
||||
|
||||
/* Bit fields for I2C SADDRMASK */
|
||||
#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
|
||||
#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
|
||||
#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
|
||||
#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
|
||||
#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
|
||||
#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
|
||||
|
||||
/* Bit fields for I2C RXDATA */
|
||||
#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
|
||||
#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
|
||||
|
||||
/* Bit fields for I2C RXDOUBLE */
|
||||
#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
|
||||
#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
|
||||
#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
|
||||
#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
|
||||
#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
|
||||
#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
|
||||
#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
|
||||
#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
|
||||
#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
|
||||
#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
|
||||
|
||||
/* Bit fields for I2C RXDATAP */
|
||||
#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
|
||||
#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
|
||||
|
||||
/* Bit fields for I2C RXDOUBLEP */
|
||||
#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
|
||||
#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
|
||||
#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
|
||||
#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
|
||||
|
||||
/* Bit fields for I2C TXDATA */
|
||||
#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
|
||||
#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
|
||||
|
||||
/* Bit fields for I2C TXDOUBLE */
|
||||
#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
|
||||
#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
|
||||
#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
|
||||
#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
|
||||
#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
|
||||
#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
|
||||
#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
|
||||
#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
|
||||
#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
|
||||
#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
|
||||
|
||||
/* Bit fields for I2C IF */
|
||||
#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
|
||||
#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
|
||||
#define I2C_IF_START (0x1UL << 0) /**< START Condition Interrupt Flag */
|
||||
#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START Condition Interrupt Flag */
|
||||
#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
|
||||
#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
|
||||
#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
|
||||
#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
|
||||
#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
|
||||
#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
|
||||
#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
|
||||
#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
|
||||
#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
|
||||
#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
|
||||
#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
|
||||
#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
|
||||
#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP Condition Interrupt Flag */
|
||||
#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
|
||||
#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
|
||||
#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
|
||||
#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
|
||||
#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
|
||||
/* Bit fields for I2C IFS */
|
||||
#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
|
||||
#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */
|
||||
#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
|
||||
#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */
|
||||
#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */
|
||||
#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */
|
||||
#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */
|
||||
#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */
|
||||
#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
|
||||
#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */
|
||||
#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */
|
||||
#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */
|
||||
#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */
|
||||
#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */
|
||||
#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */
|
||||
#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */
|
||||
#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
|
||||
#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */
|
||||
#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */
|
||||
#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
|
||||
#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
|
||||
#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
|
||||
/* Bit fields for I2C IFC */
|
||||
#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
|
||||
#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */
|
||||
#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
|
||||
#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */
|
||||
#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */
|
||||
#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */
|
||||
#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */
|
||||
#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */
|
||||
#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
|
||||
#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */
|
||||
#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */
|
||||
#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */
|
||||
#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */
|
||||
#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */
|
||||
#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */
|
||||
#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */
|
||||
#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
|
||||
#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */
|
||||
#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */
|
||||
#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
|
||||
#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
|
||||
#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
|
||||
/* Bit fields for I2C IEN */
|
||||
#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
|
||||
#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */
|
||||
#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */
|
||||
#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */
|
||||
#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */
|
||||
#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */
|
||||
#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */
|
||||
#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */
|
||||
#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */
|
||||
#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */
|
||||
#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
|
||||
#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */
|
||||
#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */
|
||||
#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */
|
||||
#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */
|
||||
#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */
|
||||
#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */
|
||||
#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */
|
||||
#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
|
||||
#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */
|
||||
#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */
|
||||
#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
|
||||
#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
|
||||
#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
|
||||
/* Bit fields for I2C ROUTEPEN */
|
||||
#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */
|
||||
#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */
|
||||
#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
|
||||
#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
|
||||
#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
|
||||
#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
|
||||
#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
|
||||
#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
|
||||
#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
|
||||
#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
|
||||
#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
|
||||
#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
|
||||
|
||||
/* Bit fields for I2C ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_MASK 0x00000707UL /**< Mask for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */
|
||||
#define _I2C_ROUTELOC0_SDALOC_MASK 0x7UL /**< Bit mask for I2C_SDALOC */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_MASK 0x700UL /**< Bit mask for I2C_SCLLOC */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_I2C */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
392
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_idac.h
vendored
Normal file
392
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_idac.h
vendored
Normal file
@ -0,0 +1,392 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_IDAC register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_IDAC IDAC
|
||||
* @{
|
||||
* @brief EFM32GG11B_IDAC Register Declaration
|
||||
******************************************************************************/
|
||||
/** IDAC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CURPROG; /**< Current Programming Register */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */
|
||||
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
uint32_t RESERVED3[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
|
||||
__IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
|
||||
} IDAC_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_IDAC
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_IDAC_BitFields IDAC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for IDAC CTRL */
|
||||
#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_MASK 0x01FD7FFFUL /**< Mask for IDAC_CTRL */
|
||||
#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */
|
||||
#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */
|
||||
#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */
|
||||
#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */
|
||||
#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */
|
||||
#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */
|
||||
#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */
|
||||
#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */
|
||||
#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */
|
||||
#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */
|
||||
#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */
|
||||
#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */
|
||||
#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */
|
||||
#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */
|
||||
#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */
|
||||
#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */
|
||||
#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */
|
||||
#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */
|
||||
#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */
|
||||
#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */
|
||||
#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */
|
||||
#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */
|
||||
#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */
|
||||
#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */
|
||||
#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */
|
||||
#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */
|
||||
#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */
|
||||
#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */
|
||||
#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */
|
||||
#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */
|
||||
#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */
|
||||
#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */
|
||||
#define _IDAC_CTRL_PRSSEL_MASK 0x1F00000UL /**< Bit mask for IDAC_PRSSEL */
|
||||
#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH12 (_IDAC_CTRL_PRSSEL_PRSCH12 << 20) /**< Shifted mode PRSCH12 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH13 (_IDAC_CTRL_PRSSEL_PRSCH13 << 20) /**< Shifted mode PRSCH13 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH14 (_IDAC_CTRL_PRSSEL_PRSCH14 << 20) /**< Shifted mode PRSCH14 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH15 (_IDAC_CTRL_PRSSEL_PRSCH15 << 20) /**< Shifted mode PRSCH15 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH16 (_IDAC_CTRL_PRSSEL_PRSCH16 << 20) /**< Shifted mode PRSCH16 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH17 (_IDAC_CTRL_PRSSEL_PRSCH17 << 20) /**< Shifted mode PRSCH17 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH18 (_IDAC_CTRL_PRSSEL_PRSCH18 << 20) /**< Shifted mode PRSCH18 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH19 (_IDAC_CTRL_PRSSEL_PRSCH19 << 20) /**< Shifted mode PRSCH19 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH20 (_IDAC_CTRL_PRSSEL_PRSCH20 << 20) /**< Shifted mode PRSCH20 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH21 (_IDAC_CTRL_PRSSEL_PRSCH21 << 20) /**< Shifted mode PRSCH21 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH22 (_IDAC_CTRL_PRSSEL_PRSCH22 << 20) /**< Shifted mode PRSCH22 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH23 (_IDAC_CTRL_PRSSEL_PRSCH23 << 20) /**< Shifted mode PRSCH23 for IDAC_CTRL */
|
||||
|
||||
/* Bit fields for IDAC CURPROG */
|
||||
#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */
|
||||
#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */
|
||||
#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */
|
||||
#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */
|
||||
#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */
|
||||
#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */
|
||||
#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */
|
||||
|
||||
/* Bit fields for IDAC DUTYCONFIG */
|
||||
#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
|
||||
#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */
|
||||
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
|
||||
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
|
||||
|
||||
/* Bit fields for IDAC STATUS */
|
||||
#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */
|
||||
#define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */
|
||||
#define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */
|
||||
#define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
|
||||
#define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */
|
||||
#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */
|
||||
#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
|
||||
#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */
|
||||
|
||||
/* Bit fields for IDAC IF */
|
||||
#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */
|
||||
#define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */
|
||||
#define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
|
||||
#define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
|
||||
#define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */
|
||||
#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */
|
||||
#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
|
||||
#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */
|
||||
|
||||
/* Bit fields for IDAC IFS */
|
||||
#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */
|
||||
#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */
|
||||
#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */
|
||||
#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
|
||||
#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */
|
||||
#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */
|
||||
#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
|
||||
#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */
|
||||
|
||||
/* Bit fields for IDAC IFC */
|
||||
#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */
|
||||
#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */
|
||||
#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */
|
||||
#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
|
||||
#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */
|
||||
#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */
|
||||
#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
|
||||
#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */
|
||||
|
||||
/* Bit fields for IDAC IEN */
|
||||
#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */
|
||||
#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */
|
||||
#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */
|
||||
#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
|
||||
#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */
|
||||
#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */
|
||||
#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
|
||||
#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */
|
||||
|
||||
/* Bit fields for IDAC APORTREQ */
|
||||
#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */
|
||||
#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the APORT Bus Connected to APORT1X is Requested */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
|
||||
|
||||
/* Bit fields for IDAC APORTCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_IDAC */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
636
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lcd.h
vendored
Normal file
636
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lcd.h
vendored
Normal file
@ -0,0 +1,636 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LCD register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_LCD LCD
|
||||
* @{
|
||||
* @brief EFM32GG11B_LCD Register Declaration
|
||||
******************************************************************************/
|
||||
/** LCD Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t DISPCTRL; /**< Display Control Register */
|
||||
__IOM uint32_t SEGEN; /**< Segment Enable Register */
|
||||
__IOM uint32_t BACTRL; /**< Blink and Animation Control Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t AREGA; /**< Animation Register a */
|
||||
__IOM uint32_t AREGB; /**< Animation Register B */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t BIASCTRL; /**< Analog BIAS Control */
|
||||
|
||||
uint32_t RESERVED1[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t SEGD0L; /**< Segment Data Low Register 0 */
|
||||
__IOM uint32_t SEGD1L; /**< Segment Data Low Register 1 */
|
||||
__IOM uint32_t SEGD2L; /**< Segment Data Low Register 2 */
|
||||
__IOM uint32_t SEGD3L; /**< Segment Data Low Register 3 */
|
||||
__IOM uint32_t SEGD0H; /**< Segment Data High Register 0 */
|
||||
__IOM uint32_t SEGD1H; /**< Segment Data High Register 1 */
|
||||
__IOM uint32_t SEGD2H; /**< Segment Data High Register 2 */
|
||||
__IOM uint32_t SEGD3H; /**< Segment Data High Register 3 */
|
||||
__IOM uint32_t SEGD4L; /**< Segment Data Low Register 4 */
|
||||
__IOM uint32_t SEGD5L; /**< Segment Data Low Register 5 */
|
||||
__IOM uint32_t SEGD6L; /**< Segment Data Low Register 6 */
|
||||
__IOM uint32_t SEGD7L; /**< Segment Data Low Register 7 */
|
||||
__IOM uint32_t SEGD4H; /**< Segment Data High Register 4 */
|
||||
__IOM uint32_t SEGD5H; /**< Segment Data High Register 5 */
|
||||
__IOM uint32_t SEGD6H; /**< Segment Data High Register 6 */
|
||||
__IOM uint32_t SEGD7H; /**< Segment Data High Register 7 */
|
||||
uint32_t RESERVED2[16U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
uint32_t RESERVED3[10U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t FRAMERATE; /**< Frame Rate */
|
||||
__IOM uint32_t SEGEN2; /**< Segment Enable (32 to 39) */
|
||||
} LCD_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_LCD
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_LCD_BitFields LCD Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LCD CTRL */
|
||||
#define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */
|
||||
#define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */
|
||||
#define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */
|
||||
#define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */
|
||||
#define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */
|
||||
#define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
|
||||
#define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */
|
||||
#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */
|
||||
#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */
|
||||
#define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */
|
||||
#define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */
|
||||
#define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */
|
||||
#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
|
||||
#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */
|
||||
|
||||
/* Bit fields for LCD DISPCTRL */
|
||||
#define _LCD_DISPCTRL_RESETVALUE 0x00103F00UL /**< Default value for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MASK 0x33703F17UL /**< Mask for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */
|
||||
#define _LCD_DISPCTRL_MUX_MASK 0x7UL /**< Bit mask for LCD_MUX */
|
||||
#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_SEXTAPLEX 0x00000005UL /**< Mode SEXTAPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_OCTAPLEX 0x00000007UL /**< Mode OCTAPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_SEXTAPLEX (_LCD_DISPCTRL_MUX_SEXTAPLEX << 0) /**< Shifted mode SEXTAPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_OCTAPLEX (_LCD_DISPCTRL_MUX_OCTAPLEX << 0) /**< Shifted mode OCTAPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */
|
||||
#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */
|
||||
#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */
|
||||
#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CONTRAST_SHIFT 8 /**< Shift value for LCD_CONTRAST */
|
||||
#define _LCD_DISPCTRL_CONTRAST_MASK 0x3F00UL /**< Bit mask for LCD_CONTRAST */
|
||||
#define _LCD_DISPCTRL_CONTRAST_DEFAULT 0x0000003FUL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONTRAST_DEFAULT (_LCD_DISPCTRL_CONTRAST_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_SHIFT 20 /**< Shift value for LCD_CHGRDST */
|
||||
#define _LCD_DISPCTRL_CHGRDST_MASK 0x700000UL /**< Bit mask for LCD_CHGRDST */
|
||||
#define _LCD_DISPCTRL_CHGRDST_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_ONE 0x00000001UL /**< Mode ONE for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_TWO 0x00000002UL /**< Mode TWO for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_THREE 0x00000003UL /**< Mode THREE for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_FOUR 0x00000004UL /**< Mode FOUR for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_DISABLE (_LCD_DISPCTRL_CHGRDST_DISABLE << 20) /**< Shifted mode DISABLE for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_DEFAULT (_LCD_DISPCTRL_CHGRDST_DEFAULT << 20) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_ONE (_LCD_DISPCTRL_CHGRDST_ONE << 20) /**< Shifted mode ONE for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_TWO (_LCD_DISPCTRL_CHGRDST_TWO << 20) /**< Shifted mode TWO for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_THREE (_LCD_DISPCTRL_CHGRDST_THREE << 20) /**< Shifted mode THREE for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_FOUR (_LCD_DISPCTRL_CHGRDST_FOUR << 20) /**< Shifted mode FOUR for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_SHIFT 24 /**< Shift value for LCD_BIAS */
|
||||
#define _LCD_DISPCTRL_BIAS_MASK 0x3000000UL /**< Bit mask for LCD_BIAS */
|
||||
#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 24) /**< Shifted mode STATIC for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 24) /**< Shifted mode ONEHALF for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 24) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 24) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MODE_SHIFT 28 /**< Shift value for LCD_MODE */
|
||||
#define _LCD_DISPCTRL_MODE_MASK 0x30000000UL /**< Bit mask for LCD_MODE */
|
||||
#define _LCD_DISPCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MODE_NOEXTCAP 0x00000000UL /**< Mode NOEXTCAP for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MODE_STEPDOWN 0x00000001UL /**< Mode STEPDOWN for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MODE_CPINTOSC 0x00000002UL /**< Mode CPINTOSC for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MODE_DEFAULT (_LCD_DISPCTRL_MODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MODE_NOEXTCAP (_LCD_DISPCTRL_MODE_NOEXTCAP << 28) /**< Shifted mode NOEXTCAP for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MODE_STEPDOWN (_LCD_DISPCTRL_MODE_STEPDOWN << 28) /**< Shifted mode STEPDOWN for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MODE_CPINTOSC (_LCD_DISPCTRL_MODE_CPINTOSC << 28) /**< Shifted mode CPINTOSC for LCD_DISPCTRL */
|
||||
|
||||
/* Bit fields for LCD SEGEN */
|
||||
#define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */
|
||||
#define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */
|
||||
|
||||
/* Bit fields for LCD BACTRL */
|
||||
#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */
|
||||
#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */
|
||||
#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */
|
||||
#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */
|
||||
#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */
|
||||
#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */
|
||||
#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */
|
||||
#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */
|
||||
#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */
|
||||
#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */
|
||||
#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */
|
||||
#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */
|
||||
#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */
|
||||
#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */
|
||||
#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */
|
||||
#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */
|
||||
#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */
|
||||
#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */
|
||||
#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */
|
||||
#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */
|
||||
#define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */
|
||||
#define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */
|
||||
#define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */
|
||||
#define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */
|
||||
#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */
|
||||
#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */
|
||||
#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */
|
||||
|
||||
/* Bit fields for LCD STATUS */
|
||||
#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */
|
||||
#define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */
|
||||
#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */
|
||||
#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */
|
||||
#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */
|
||||
#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */
|
||||
#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */
|
||||
#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */
|
||||
|
||||
/* Bit fields for LCD AREGA */
|
||||
#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */
|
||||
#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */
|
||||
#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */
|
||||
|
||||
/* Bit fields for LCD AREGB */
|
||||
#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */
|
||||
#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */
|
||||
#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */
|
||||
|
||||
/* Bit fields for LCD IF */
|
||||
#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */
|
||||
#define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */
|
||||
#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */
|
||||
#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
|
||||
#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */
|
||||
|
||||
/* Bit fields for LCD IFS */
|
||||
#define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */
|
||||
#define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */
|
||||
#define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */
|
||||
#define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */
|
||||
#define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */
|
||||
|
||||
/* Bit fields for LCD IFC */
|
||||
#define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */
|
||||
#define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */
|
||||
#define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */
|
||||
#define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */
|
||||
#define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */
|
||||
|
||||
/* Bit fields for LCD IEN */
|
||||
#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */
|
||||
#define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */
|
||||
#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */
|
||||
#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
|
||||
#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */
|
||||
|
||||
/* Bit fields for LCD BIASCTRL */
|
||||
#define _LCD_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BIASCTRL */
|
||||
#define _LCD_BIASCTRL_MASK 0x00001CF7UL /**< Mask for LCD_BIASCTRL */
|
||||
#define _LCD_BIASCTRL_SPEED_SHIFT 0 /**< Shift value for LCD_SPEED */
|
||||
#define _LCD_BIASCTRL_SPEED_MASK 0x7UL /**< Bit mask for LCD_SPEED */
|
||||
#define _LCD_BIASCTRL_SPEED_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
|
||||
#define LCD_BIASCTRL_SPEED_DEFAULT (_LCD_BIASCTRL_SPEED_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
|
||||
#define _LCD_BIASCTRL_BUFDRV_SHIFT 4 /**< Shift value for LCD_BUFDRV */
|
||||
#define _LCD_BIASCTRL_BUFDRV_MASK 0xF0UL /**< Bit mask for LCD_BUFDRV */
|
||||
#define _LCD_BIASCTRL_BUFDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
|
||||
#define LCD_BIASCTRL_BUFDRV_DEFAULT (_LCD_BIASCTRL_BUFDRV_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
|
||||
#define _LCD_BIASCTRL_BUFBIAS_SHIFT 10 /**< Shift value for LCD_BUFBIAS */
|
||||
#define _LCD_BIASCTRL_BUFBIAS_MASK 0x1C00UL /**< Bit mask for LCD_BUFBIAS */
|
||||
#define _LCD_BIASCTRL_BUFBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
|
||||
#define LCD_BIASCTRL_BUFBIAS_DEFAULT (_LCD_BIASCTRL_BUFBIAS_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
|
||||
|
||||
/* Bit fields for LCD SEGD0L */
|
||||
#define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */
|
||||
#define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */
|
||||
|
||||
/* Bit fields for LCD SEGD1L */
|
||||
#define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */
|
||||
#define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */
|
||||
|
||||
/* Bit fields for LCD SEGD2L */
|
||||
#define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */
|
||||
#define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */
|
||||
|
||||
/* Bit fields for LCD SEGD3L */
|
||||
#define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */
|
||||
#define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */
|
||||
|
||||
/* Bit fields for LCD SEGD0H */
|
||||
#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */
|
||||
#define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */
|
||||
|
||||
/* Bit fields for LCD SEGD1H */
|
||||
#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */
|
||||
#define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */
|
||||
|
||||
/* Bit fields for LCD SEGD2H */
|
||||
#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */
|
||||
#define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */
|
||||
|
||||
/* Bit fields for LCD SEGD3H */
|
||||
#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */
|
||||
#define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */
|
||||
|
||||
/* Bit fields for LCD SEGD4L */
|
||||
#define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */
|
||||
#define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */
|
||||
#define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */
|
||||
#define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */
|
||||
#define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */
|
||||
#define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */
|
||||
|
||||
/* Bit fields for LCD SEGD5L */
|
||||
#define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */
|
||||
#define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */
|
||||
#define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */
|
||||
#define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */
|
||||
#define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */
|
||||
#define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */
|
||||
|
||||
/* Bit fields for LCD SEGD6L */
|
||||
#define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */
|
||||
#define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */
|
||||
#define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */
|
||||
#define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */
|
||||
#define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */
|
||||
#define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */
|
||||
|
||||
/* Bit fields for LCD SEGD7L */
|
||||
#define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */
|
||||
#define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */
|
||||
#define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */
|
||||
#define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */
|
||||
#define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */
|
||||
#define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
|
||||
|
||||
/* Bit fields for LCD SEGD4H */
|
||||
#define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */
|
||||
#define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */
|
||||
#define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */
|
||||
#define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */
|
||||
#define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */
|
||||
#define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */
|
||||
|
||||
/* Bit fields for LCD SEGD5H */
|
||||
#define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */
|
||||
#define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */
|
||||
#define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */
|
||||
#define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */
|
||||
#define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */
|
||||
#define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */
|
||||
|
||||
/* Bit fields for LCD SEGD6H */
|
||||
#define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */
|
||||
#define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */
|
||||
#define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */
|
||||
#define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */
|
||||
#define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */
|
||||
#define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */
|
||||
|
||||
/* Bit fields for LCD SEGD7H */
|
||||
#define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */
|
||||
#define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */
|
||||
#define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */
|
||||
#define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */
|
||||
#define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */
|
||||
#define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */
|
||||
|
||||
/* Bit fields for LCD FREEZE */
|
||||
#define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_MASK 0x00000003UL /**< Mask for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_LCDGATE (0x1UL << 1) /**< LCD Gate */
|
||||
#define _LCD_FREEZE_LCDGATE_SHIFT 1 /**< Shift value for LCD_LCDGATE */
|
||||
#define _LCD_FREEZE_LCDGATE_MASK 0x2UL /**< Bit mask for LCD_LCDGATE */
|
||||
#define _LCD_FREEZE_LCDGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_LCDGATE_UNGATE 0x00000000UL /**< Mode UNGATE for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_LCDGATE_GATE 0x00000001UL /**< Mode GATE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_LCDGATE_DEFAULT (_LCD_FREEZE_LCDGATE_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_FREEZE */
|
||||
#define LCD_FREEZE_LCDGATE_UNGATE (_LCD_FREEZE_LCDGATE_UNGATE << 1) /**< Shifted mode UNGATE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_LCDGATE_GATE (_LCD_FREEZE_LCDGATE_GATE << 1) /**< Shifted mode GATE for LCD_FREEZE */
|
||||
|
||||
/* Bit fields for LCD SYNCBUSY */
|
||||
#define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */
|
||||
#define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
|
||||
#define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */
|
||||
#define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */
|
||||
#define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */
|
||||
#define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */
|
||||
#define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */
|
||||
#define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */
|
||||
#define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */
|
||||
#define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */
|
||||
#define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */
|
||||
#define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */
|
||||
#define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */
|
||||
#define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD4L (0x1UL << 12) /**< SEGD4L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD4L_SHIFT 12 /**< Shift value for LCD_SEGD4L */
|
||||
#define _LCD_SYNCBUSY_SEGD4L_MASK 0x1000UL /**< Bit mask for LCD_SEGD4L */
|
||||
#define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD5L (0x1UL << 13) /**< SEGD5L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD5L_SHIFT 13 /**< Shift value for LCD_SEGD5L */
|
||||
#define _LCD_SYNCBUSY_SEGD5L_MASK 0x2000UL /**< Bit mask for LCD_SEGD5L */
|
||||
#define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD6L (0x1UL << 14) /**< SEGD6L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD6L_SHIFT 14 /**< Shift value for LCD_SEGD6L */
|
||||
#define _LCD_SYNCBUSY_SEGD6L_MASK 0x4000UL /**< Bit mask for LCD_SEGD6L */
|
||||
#define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD7L (0x1UL << 15) /**< SEGD7L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD7L_SHIFT 15 /**< Shift value for LCD_SEGD7L */
|
||||
#define _LCD_SYNCBUSY_SEGD7L_MASK 0x8000UL /**< Bit mask for LCD_SEGD7L */
|
||||
#define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD4H (0x1UL << 16) /**< SEGD4H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD4H_SHIFT 16 /**< Shift value for LCD_SEGD4H */
|
||||
#define _LCD_SYNCBUSY_SEGD4H_MASK 0x10000UL /**< Bit mask for LCD_SEGD4H */
|
||||
#define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD5H (0x1UL << 17) /**< SEGD5H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD5H_SHIFT 17 /**< Shift value for LCD_SEGD5H */
|
||||
#define _LCD_SYNCBUSY_SEGD5H_MASK 0x20000UL /**< Bit mask for LCD_SEGD5H */
|
||||
#define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD6H (0x1UL << 18) /**< SEGD6H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD6H_SHIFT 18 /**< Shift value for LCD_SEGD6H */
|
||||
#define _LCD_SYNCBUSY_SEGD6H_MASK 0x40000UL /**< Bit mask for LCD_SEGD6H */
|
||||
#define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD7H (0x1UL << 19) /**< SEGD7H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD7H_SHIFT 19 /**< Shift value for LCD_SEGD7H */
|
||||
#define _LCD_SYNCBUSY_SEGD7H_MASK 0x80000UL /**< Bit mask for LCD_SEGD7H */
|
||||
#define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
|
||||
/* Bit fields for LCD FRAMERATE */
|
||||
#define _LCD_FRAMERATE_RESETVALUE 0x00000000UL /**< Default value for LCD_FRAMERATE */
|
||||
#define _LCD_FRAMERATE_MASK 0x000001FFUL /**< Mask for LCD_FRAMERATE */
|
||||
#define _LCD_FRAMERATE_FRDIV_SHIFT 0 /**< Shift value for LCD_FRDIV */
|
||||
#define _LCD_FRAMERATE_FRDIV_MASK 0x1FFUL /**< Bit mask for LCD_FRDIV */
|
||||
#define _LCD_FRAMERATE_FRDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FRAMERATE */
|
||||
#define LCD_FRAMERATE_FRDIV_DEFAULT (_LCD_FRAMERATE_FRDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FRAMERATE */
|
||||
|
||||
/* Bit fields for LCD SEGEN2 */
|
||||
#define _LCD_SEGEN2_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN2 */
|
||||
#define _LCD_SEGEN2_MASK 0x000000FFUL /**< Mask for LCD_SEGEN2 */
|
||||
#define _LCD_SEGEN2_SEGEN2_SHIFT 0 /**< Shift value for LCD_SEGEN2 */
|
||||
#define _LCD_SEGEN2_SEGEN2_MASK 0xFFUL /**< Bit mask for LCD_SEGEN2 */
|
||||
#define _LCD_SEGEN2_SEGEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN2 */
|
||||
#define LCD_SEGEN2_SEGEN2_DEFAULT (_LCD_SEGEN2_SEGEN2_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN2 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_LCD */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
781
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma.h
vendored
Normal file
781
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma.h
vendored
Normal file
@ -0,0 +1,781 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LDMA register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_LDMA LDMA
|
||||
* @{
|
||||
* @brief EFM32GG11B_LDMA Register Declaration
|
||||
******************************************************************************/
|
||||
/** LDMA Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< DMA Control Register */
|
||||
__IM uint32_t STATUS; /**< DMA Status Register */
|
||||
__IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
|
||||
uint32_t RESERVED0[5U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
|
||||
__IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
|
||||
__IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
|
||||
__IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
|
||||
__IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
|
||||
__IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
|
||||
__IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
|
||||
__IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
|
||||
__IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
|
||||
uint32_t RESERVED1[7U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED2[4U]; /**< Reserved registers */
|
||||
LDMA_CH_TypeDef CH[24U]; /**< DMA Channel Registers */
|
||||
} LDMA_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_LDMA
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_LDMA_BitFields LDMA Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LDMA CTRL */
|
||||
#define _LDMA_CTRL_RESETVALUE 0x17000000UL /**< Default value for LDMA_CTRL */
|
||||
#define _LDMA_CTRL_MASK 0x1F00FFFFUL /**< Mask for LDMA_CTRL */
|
||||
#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */
|
||||
#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */
|
||||
#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
|
||||
#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */
|
||||
#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */
|
||||
#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */
|
||||
#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
|
||||
#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */
|
||||
#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
|
||||
#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */
|
||||
#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000017UL /**< Mode DEFAULT for LDMA_CTRL */
|
||||
#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
|
||||
|
||||
/* Bit fields for LDMA STATUS */
|
||||
#define _LDMA_STATUS_RESETVALUE 0x18100000UL /**< Default value for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */
|
||||
#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
|
||||
#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
|
||||
#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
|
||||
#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
|
||||
#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
|
||||
#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
|
||||
#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
|
||||
#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */
|
||||
#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
|
||||
#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */
|
||||
#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
|
||||
#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
|
||||
#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
|
||||
#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
|
||||
#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000018UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
|
||||
/* Bit fields for LDMA SYNC */
|
||||
#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */
|
||||
#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */
|
||||
#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
|
||||
#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
|
||||
#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */
|
||||
#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */
|
||||
|
||||
/* Bit fields for LDMA CHEN */
|
||||
#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
|
||||
#define _LDMA_CHEN_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHEN */
|
||||
#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
|
||||
#define _LDMA_CHEN_CHEN_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHEN */
|
||||
#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
|
||||
#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
|
||||
|
||||
/* Bit fields for LDMA CHBUSY */
|
||||
#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
|
||||
#define _LDMA_CHBUSY_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHBUSY */
|
||||
#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
|
||||
#define _LDMA_CHBUSY_BUSY_MASK 0xFFFFFFUL /**< Bit mask for LDMA_BUSY */
|
||||
#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
|
||||
#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
|
||||
|
||||
/* Bit fields for LDMA CHDONE */
|
||||
#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
|
||||
#define _LDMA_CHDONE_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHDONE */
|
||||
#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
|
||||
#define _LDMA_CHDONE_CHDONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHDONE */
|
||||
#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
|
||||
#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
|
||||
|
||||
/* Bit fields for LDMA DBGHALT */
|
||||
#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
|
||||
#define _LDMA_DBGHALT_MASK 0x00FFFFFFUL /**< Mask for LDMA_DBGHALT */
|
||||
#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
|
||||
#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DBGHALT */
|
||||
#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
|
||||
#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
|
||||
|
||||
/* Bit fields for LDMA SWREQ */
|
||||
#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
|
||||
#define _LDMA_SWREQ_MASK 0x00FFFFFFUL /**< Mask for LDMA_SWREQ */
|
||||
#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
|
||||
#define _LDMA_SWREQ_SWREQ_MASK 0xFFFFFFUL /**< Bit mask for LDMA_SWREQ */
|
||||
#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
|
||||
#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
|
||||
|
||||
/* Bit fields for LDMA REQDIS */
|
||||
#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
|
||||
#define _LDMA_REQDIS_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQDIS */
|
||||
#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
|
||||
#define _LDMA_REQDIS_REQDIS_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQDIS */
|
||||
#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
|
||||
#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
|
||||
|
||||
/* Bit fields for LDMA REQPEND */
|
||||
#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
|
||||
#define _LDMA_REQPEND_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQPEND */
|
||||
#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
|
||||
#define _LDMA_REQPEND_REQPEND_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQPEND */
|
||||
#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
|
||||
#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
|
||||
|
||||
/* Bit fields for LDMA LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_MASK 0x00FFFFFFUL /**< Mask for LDMA_LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFFFFFUL /**< Bit mask for LDMA_LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
|
||||
#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
|
||||
|
||||
/* Bit fields for LDMA REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
|
||||
#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
|
||||
|
||||
/* Bit fields for LDMA IF */
|
||||
#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
|
||||
#define _LDMA_IF_MASK 0x80FFFFFFUL /**< Mask for LDMA_IF */
|
||||
#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
|
||||
#define _LDMA_IF_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
|
||||
#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
|
||||
#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
|
||||
#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */
|
||||
#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
|
||||
#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
|
||||
#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
|
||||
#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
|
||||
|
||||
/* Bit fields for LDMA IFS */
|
||||
#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */
|
||||
#define _LDMA_IFS_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFS */
|
||||
#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
|
||||
#define _LDMA_IFS_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
|
||||
#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
|
||||
#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */
|
||||
#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */
|
||||
#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
|
||||
#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
|
||||
#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
|
||||
#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */
|
||||
|
||||
/* Bit fields for LDMA IFC */
|
||||
#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */
|
||||
#define _LDMA_IFC_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFC */
|
||||
#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
|
||||
#define _LDMA_IFC_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
|
||||
#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
|
||||
#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */
|
||||
#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */
|
||||
#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
|
||||
#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
|
||||
#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
|
||||
#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */
|
||||
|
||||
/* Bit fields for LDMA IEN */
|
||||
#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
|
||||
#define _LDMA_IEN_MASK 0x80FFFFFFUL /**< Mask for LDMA_IEN */
|
||||
#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
|
||||
#define _LDMA_IEN_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
|
||||
#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
|
||||
#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
|
||||
#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */
|
||||
#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
|
||||
#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
|
||||
#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
|
||||
#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
|
||||
|
||||
/* Bit fields for LDMA CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV 0x00000000UL /**< Mode USART4RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV 0x00000000UL /**< Mode USART5RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV 0x00000000UL /**< Mode UART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV 0x00000000UL /**< Mode I2C2RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000000UL /**< Mode TIMER4UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF 0x00000000UL /**< Mode TIMER5UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF 0x00000000UL /**< Mode TIMER6UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF 0x00000000UL /**< Mode WTIMER2UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF 0x00000000UL /**< Mode WTIMER3UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /**< Mode EBIPXL0EMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART4TXBL 0x00000001UL /**< Mode USART4TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART5TXBL 0x00000001UL /**< Mode USART5TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART1TXBL 0x00000001UL /**< Mode UART1TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C2TXBL 0x00000001UL /**< Mode I2C2TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000001UL /**< Mode TIMER4CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 0x00000001UL /**< Mode TIMER5CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 0x00000001UL /**< Mode TIMER6CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 0x00000001UL /**< Mode WTIMER2CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 0x00000001UL /**< Mode WTIMER3CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /**< Mode EBIPXL1EMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY 0x00000002UL /**< Mode USART4TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY 0x00000002UL /**< Mode USART5TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY 0x00000002UL /**< Mode UART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000002UL /**< Mode TIMER4CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 0x00000002UL /**< Mode TIMER5CC1 for LDMA_CH_REQSEL */
|
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 0x00000002UL /**< Mode TIMER6CC1 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 0x00000002UL /**< Mode WTIMER2CC1 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 0x00000002UL /**< Mode WTIMER3CC1 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL 0x00000002UL /**< Mode EBIPXLFULL for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT 0x00000003UL /**< Mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000003UL /**< Mode TIMER4CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 0x00000003UL /**< Mode TIMER5CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 0x00000003UL /**< Mode TIMER6CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 0x00000003UL /**< Mode WTIMER2CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 0x00000003UL /**< Mode WTIMER3CC2 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY 0x00000003UL /**< Mode EBIDDEMPTY for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT 0x00000004UL /**< Mode USART4TXBLRIGHT for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_EBIVSYNC 0x00000004UL /**< Mode EBIVSYNC for LDMA_CH_REQSEL */
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#define _LDMA_CH_REQSEL_SIGSEL_EBIHSYNC 0x00000005UL /**< Mode EBIHSYNC for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV << 0) /**< Shifted mode I2C2RXDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /**< Shifted mode TIMER4UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF << 0) /**< Shifted mode TIMER5UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF << 0) /**< Shifted mode TIMER6UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF << 0) /**< Shifted mode WTIMER2UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF << 0) /**< Shifted mode WTIMER3UFOF for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY << 0) /**< Shifted mode EBIPXL0EMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_ADC1SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART4TXBL (_LDMA_CH_REQSEL_SIGSEL_USART4TXBL << 0) /**< Shifted mode USART4TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART5TXBL (_LDMA_CH_REQSEL_SIGSEL_USART5TXBL << 0) /**< Shifted mode USART5TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_UART0TXBL (_LDMA_CH_REQSEL_SIGSEL_UART0TXBL << 0) /**< Shifted mode UART0TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_UART1TXBL (_LDMA_CH_REQSEL_SIGSEL_UART1TXBL << 0) /**< Shifted mode UART1TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_I2C2TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C2TXBL << 0) /**< Shifted mode I2C2TXBL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY << 0) /**< Shifted mode EBIPXL1EMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY << 0) /**< Shifted mode USART4TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY << 0) /**< Shifted mode USART5TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY << 0) /**< Shifted mode UART0TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY << 0) /**< Shifted mode UART1TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL (_LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL << 0) /**< Shifted mode EBIPXLFULL for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT << 0) /**< Shifted mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for LDMA_CH_REQSEL */
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#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for LDMA_CH_REQSEL */
|
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#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY << 0) /**< Shifted mode EBIDDEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT << 0) /**< Shifted mode USART4TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIVSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIVSYNC << 0) /**< Shifted mode EBIVSYNC for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIHSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIHSYNC << 0) /**< Shifted mode EBIHSYNC for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_ADC1 0x00000009UL /**< Mode ADC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART4 0x00000010UL /**< Mode USART4 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART5 0x00000011UL /**< Mode USART5 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_UART0 0x00000012UL /**< Mode UART0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_UART1 0x00000013UL /**< Mode UART1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000014UL /**< Mode LEUART0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_LEUART1 0x00000015UL /**< Mode LEUART1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000016UL /**< Mode I2C0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000017UL /**< Mode I2C1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_I2C2 0x00000018UL /**< Mode I2C2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000019UL /**< Mode TIMER0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x0000001AUL /**< Mode TIMER1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER2 0x0000001BUL /**< Mode TIMER2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER3 0x0000001CUL /**< Mode TIMER3 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER4 0x0000001DUL /**< Mode TIMER4 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER5 0x0000001EUL /**< Mode TIMER5 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER6 0x0000001FUL /**< Mode TIMER6 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x00000020UL /**< Mode WTIMER0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x00000021UL /**< Mode WTIMER1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER2 0x00000022UL /**< Mode WTIMER2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER3 0x00000023UL /**< Mode WTIMER3 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_EBI 0x00000032UL /**< Mode EBI for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x0000003DUL /**< Mode CSEN for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x0000003EUL /**< Mode LESENSE for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_ADC1 (_LDMA_CH_REQSEL_SOURCESEL_ADC1 << 16) /**< Shifted mode ADC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART4 (_LDMA_CH_REQSEL_SOURCESEL_USART4 << 16) /**< Shifted mode USART4 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART5 (_LDMA_CH_REQSEL_SOURCESEL_USART5 << 16) /**< Shifted mode USART5 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_UART0 (_LDMA_CH_REQSEL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_UART1 (_LDMA_CH_REQSEL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_LEUART1 (_LDMA_CH_REQSEL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_I2C2 (_LDMA_CH_REQSEL_SOURCESEL_I2C2 << 16) /**< Shifted mode I2C2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER2 (_LDMA_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER3 (_LDMA_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER4 (_LDMA_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted mode TIMER4 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER5 (_LDMA_CH_REQSEL_SOURCESEL_TIMER5 << 16) /**< Shifted mode TIMER5 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER6 (_LDMA_CH_REQSEL_SOURCESEL_TIMER6 << 16) /**< Shifted mode TIMER6 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER2 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER2 << 16) /**< Shifted mode WTIMER2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER3 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER3 << 16) /**< Shifted mode WTIMER3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_EBI (_LDMA_CH_REQSEL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */
|
||||
|
||||
/* Bit fields for LDMA CH_CFG */
|
||||
#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
|
||||
|
||||
/* Bit fields for LDMA CH_LOOP */
|
||||
#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
|
||||
#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
|
||||
#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
|
||||
#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
|
||||
#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
|
||||
#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
|
||||
|
||||
/* Bit fields for LDMA CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
|
||||
#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
|
||||
#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
|
||||
#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
|
||||
#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
|
||||
#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
|
||||
#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
|
||||
#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
|
||||
#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */
|
||||
#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */
|
||||
#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */
|
||||
#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
|
||||
#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
|
||||
#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
|
||||
#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
|
||||
#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
|
||||
#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
|
||||
#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
|
||||
#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
|
||||
#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
|
||||
#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
|
||||
#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
|
||||
#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
|
||||
#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
|
||||
#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
|
||||
#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
|
||||
#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
|
||||
|
||||
/* Bit fields for LDMA CH_SRC */
|
||||
#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
|
||||
#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
|
||||
#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
|
||||
#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
|
||||
#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
|
||||
#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
|
||||
|
||||
/* Bit fields for LDMA CH_DST */
|
||||
#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
|
||||
#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
|
||||
#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
|
||||
#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
|
||||
#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
|
||||
#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
|
||||
|
||||
/* Bit fields for LDMA CH_LINK */
|
||||
#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
|
||||
#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
|
||||
#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
|
||||
#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
|
||||
#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
|
||||
#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
|
||||
#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
|
||||
#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
|
||||
#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
|
||||
#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
|
||||
#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
|
||||
#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
|
||||
#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_LDMA */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
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Reference in New Issue
Block a user