Merge pull request #18755 from gschorcht/boards/sltb009a

boards: add support for EFM32GG12 Thunderboard Kit (SLTB009A)
2025-01-17 10:52:44 +01:00 · 2022-10-18 11:12:28 +02:00 · 2022-10-18 11:12:28 +02:00 · da5cd8fa88
commit da5cd8fa88
parent a98a706112 7a6847edc7
155 changed files with 433061 additions and 3 deletions
--- a/boards/sltb009a/Kconfig
+++ b/boards/sltb009a/Kconfig
@ -0,0 +1,25 @@
+# Copyright (c) 2020 HAW Hamburg
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+
+config BOARD
+    default "sltb009a" if BOARD_SLTB009A
+
+config BOARD_SLTB009A
+    bool
+    default y
+    select BOARD_COMMON_SILABS
+    select CPU_MODEL_EFM32GG12B810F1024GM64
+    select HAS_PERIPH_ADC
+    select HAS_PERIPH_I2C
+    select HAS_PERIPH_RTC
+    select HAS_PERIPH_RTT
+    select HAS_PERIPH_SPI
+    select HAS_PERIPH_TIMER
+    select HAS_PERIPH_UART
+    select HAS_PERIPH_UART_MODECFG
+    select HAVE_SAUL_GPIO
+
+source "$(RIOTBOARD)/common/silabs/Kconfig"
--- a/boards/sltb009a/Makefile
+++ b/boards/sltb009a/Makefile
@ -0,0 +1,5 @@
+MODULE = board
+
+DIRS = $(RIOTBOARD)/common/silabs
+
+include $(RIOTBASE)/Makefile.base
--- a/boards/sltb009a/Makefile.dep
+++ b/boards/sltb009a/Makefile.dep
@ -0,0 +1,10 @@
+ifneq (,$(filter saul_default,$(USEMODULE)))
+  USEMODULE += efm32_coretemp
+  USEMODULE += saul_gpio
+endif
+
+# add board common drivers
+USEMODULE += boards_common_silabs
+
+# include board common dependencies
+include $(RIOTBOARD)/common/silabs/Makefile.dep
--- a/boards/sltb009a/Makefile.features
+++ b/boards/sltb009a/Makefile.features
@ -0,0 +1,14 @@
+CPU = efm32
+CPU_FAM = efm32gg12b
+CPU_MODEL = efm32gg12b810f1024gm64
+
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_adc
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_rtc
+FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart periph_uart_modecfg
+
+include $(RIOTBOARD)/common/silabs/Makefile.features
--- a/boards/sltb009a/Makefile.include
+++ b/boards/sltb009a/Makefile.include
@ -0,0 +1,12 @@
+# set default port depending on operating system
+PORT_LINUX ?= /dev/ttyACM0
+PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
+
+# setup serial terminal
+include $(RIOTMAKE)/tools/serial.inc.mk
+
+# setup JLink for flashing
+JLINK_PRE_FLASH = r
+
+# include board common
+include $(RIOTBOARD)/common/silabs/Makefile.include
--- a/boards/sltb009a/board.c
+++ b/boards/sltb009a/board.c
@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2015-2020 Freie Universität Berlin
+ *               2022      Gunar Schorcht
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_sltb009a
+ * @{
+ *
+ * @file
+ * @brief       Board specific implementations SLTB009A board
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author      Bas Stottelaar <basstottelaar@gmail.com>
+ * @author      Gunar Schorcht <gunar@schorcht.net>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "board_common.h"
+
+void board_init(void)
+{
+#ifndef RIOTBOOT
+    /* perform common board initialization */
+    board_common_init();
+#endif
+    /* enable the virtual COM port */
+    gpio_init(VCOM_EN_PIN, GPIO_OUT);
+    gpio_set(VCOM_EN_PIN);
+}
--- a/boards/sltb009a/doc.txt
+++ b/boards/sltb009a/doc.txt
@ -0,0 +1,232 @@
+/**
+ * @defgroup    boards_sltb009a Silicon Labs SLTB009A starter kit
+ * @ingroup     boards
+ * @brief       Support for Silicon Labs SLTB009A starter kit
+
+## Overview
+Silicon Labs Thunderboard GG12 is equipped with the EFM32 microcontroller.
+It is specifically designed for low-power applications, having energy-saving
+peripherals, different energy modes and short wake-up times.
+
+The starter kit is equipped with an Advanced Energy Monitor. This allows you to
+actively measure the power consumption of your hardware and code, in real-time.
+
+## Hardware
+
+### MCU
+| MCU             | EFM32GG12B810F1024GM64                               |
+|-----------------|------------------------------------------------------|
+| Family          | ARM Cortex-M4F                                       |
+| Vendor          | Silicon Labs                                         |
+| Vendor Family   | EFM32 Giant Gecko 12B                                |
+| RAM             | 192.0 KiB                                            |
+| Flash           | 1024.0 KiB                                           |
+| EEPROM          | no                                                   |
+| Frequency       | up to 50 MHz                                         |
+| FPU             | yes                                                  |
+| MPU             | yes                                                  |
+| DMA             | 12 channels                                          |
+| Timers          | 4x 32-bit, 7x 16-bit + 1x 16-bit (low power)         |
+| ADCs            | 12-bit ADC                                           |
+| UARTs           | 2x UART, 5x USART, 1x LEUART                         |
+| SPIs            | 5x USART                                             |
+| I2Cs            | 2x                                                   |
+| Vcc             | 1.8 V - 3.8 V                                        |
+| Datasheet       | [Datasheet](https://www.silabs.com/documents/public/data-sheets/efm32gg12-datasheet.pdf)                                 |
+| Manual          | [Manual](https://www.silabs.com/documents/public/reference-manuals/efm32gg12-rm.pdf)                                     |
+| Board Manual    | [Board Manual](https://www.silabs.com/documents/public/user-guides/ug371-sltb009a-user-guide.pdf)                        |
+| Board Schematic | Can be downloaded using Silicon Labs' Simplicity Studio         |
+
+### Pinout
+This is the pinout of the expansion header on the right side of the board.
+PIN 1 is the bottom-left contact when the header faces  you horizontally.
+
+|      | PIN | PIN |      |
+|------|-----|-----|------|
+| GND  | 1   | 2   | VMCU |
+| PD0  | 3   | 4   | PA0  |
+| PD1  | 5   | 6   | PA1  |
+| PA4  | 7   | 8   | PA2  |
+| PA5  | 9   | 10  | PA3  |
+| PA6  | 11  | 12  | PC4  |
+| PE15 | 13  | 14  | PC5  |
+| PE5  | 15  | 16  | PE4  |
+|      | 17  | 18  | 5V   |
+|      | 19  | 20  | 3V3  |
+| PB12 | 21  | 22  | PE8  |
+| PB11 | 23  | 24  | PE9  |
+| PB3  | 25  | 26  | PE10 |
+| PB4  | 27  | 28  | PE11 |
+| PD2  | 29  | 30  | PE13 |
+| PD3  | 31  | 32  | PE14 |
+| PD4  | 33  | 34  | PF5  |
+
+**Note**: not all starter kits by Silicon Labs share the same pinout!
+
+### Peripheral mapping
+| Peripheral | Number  | Hardware          | Pins                              | Comments                                                  |
+|------------|---------|-------------------|-----------------------------------|-----------------------------------------------------------|
+
+### User interface
+| Peripheral | Mapped to | Pin  | Comments   |
+|------------|-----------|------|------------|
+| Button     | PB0_PIN   | PD5  |            |
+|            | PB1_PIN   | PD8  |            |
+| LED        | LED0R_PIN | PA12 |            |
+|            | LED0G_PIN | PA13 |            |
+|            | LED0B_PIN | PA14 |            |
+|            | LED1R_PIN | PD6  |            |
+|            | LED1G_PIN | PF12 |            |
+|            | LED1B_PIN | PE12 |            |
+|            | LED0_PIN  | LED0R_PIN |            |
+|            | LED1_PIN  | LED1R_PIN |            |
+
+## Implementation Status
+| Device                        | ID                                  | Supported | Comments                                                       |
+|-------------------------------|-------------------------------------|-----------|----------------------------------------------------------------|
+| MCU                           | EFM32GG12B                          | yes       | Power modes supported                                          |
+| Low-level driver              | ADC                                 | yes       |                                                                |
+|                               | Flash                               | yes       |                                                                |
+|                               | GPIO                                | yes       | Interrupts are shared across pins (see reference manual)       |
+|                               | HW Crypto                           | yes       |                                                                |
+|                               | I2C                                 | yes       |                                                                |
+|                               | PWM                                 | yes       |                                                                |
+|                               | RTCC                                | yes       | As RTT or RTC                                                  |
+|                               | SPI                                 | partially | Only master mode                                               |
+|                               | Timer                               | yes       |                                                                |
+|                               | UART                                | yes       | USART is shared with SPI. LEUART baud rate limited (see below) |
+|                               | USB                                 | no        |                                                                |
+
+## Board configuration
+
+### Board controller
+The starter kit is equipped with a Board Controller. This controller provides
+a virtual serial port.
+
+**Note:** the board controller *always* configures the virtual serial port at
+115200 baud with 8 bits, no parity and one stop bit. This also means that it
+expects data from the MCU with the same settings.
+
+### Clock selection
+There are several clock sources that are available for the different
+peripherals. You are advised to read [AN0004.0](https://www.silabs.com/documents/public/application-notes/an0004.0-efm32-cmu.pdf)
+to get familiar with the different clocks.
+
+| Source | Internal | Speed      | Comments                           |
+|--------|----------|------------|------------------------------------|
+| HFRCO  | Yes      | 19 MHz     | Enabled during startup, changeable |
+| HFXO   | No       | 50 MHz     |                                    |
+| LFRCO  | Yes      | 32.768 kHz |                                    |
+| LFXO   | No       | 32.768 kHz |                                    |
+| ULFRCO | No       | 1 kHz      | Not very reliable as a time source |
+
+The sources can be used to clock following branches:
+
+| Branch | Sources                 | Comments                     |
+|--------|-------------------------|------------------------------|
+| HF     | HFRCO, HFXO             | Core, peripherals            |
+| LFA    | LFRCO, LFXO             | Low-power timers             |
+| LFB    | LFRCO, LFXO, CORELEDIV2 | Low-power UART               |
+| LFE    | LFRCO, LFXO             | Real-time Clock and Calendar |
+
+CORELEDIV2 is a source that depends on the clock source that powers the core.
+It is divided by 2 or 4 to not exceed maximum clock frequencies (EMLIB takes
+care of this).
+
+The frequencies mentioned in the tables above are specific for this starter
+kit.
+
+It is important that the clock speeds are known to the code, for proper
+calculations of speeds and baud rates. If the HFXO or LFXO are different from
+the speeds above, ensure to pass `EFM32_HFXO_FREQ=freq_in_hz` and
+`EFM32_LFXO_FREQ=freq_in_hz` to your compiler.
+
+You can override the branch's clock source by adding `CLOCK_LFA=source` to your
+compiler defines, e.g. `CLOCK_LFA=cmuSelect_LFRCO`.
+
+### Low-power peripherals
+The low-power UART is capable of providing an UART peripheral using a low-speed
+clock. When the LFB clock source is the LFRCO or LFXO, it can still be used in
+EM2. However, this limits the baud rate to 9600 baud. If a higher baud rate is
+desired, set the clock source to CORELEDIV2.
+
+**Note:** peripheral mappings in your board definitions will not be affected by
+this setting. Ensure you do not refer to any low-power peripherals.
+
+### RTC or RTT
+RIOT-OS has support for *Real-Time Tickers* and *Real-Time Clocks*.
+
+However, this board MCU family has support for a 32-bit *Real-Time Clock and
+Calendar*, which can be configured in ticker mode **or** calendar mode.
+Therefore, only one of both peripherals can be enabled at the same time.
+
+Configured at 1 Hz interval, the RTCC will overflow each 136 years.
+
+### Hardware crypto
+This MCU is equipped with a hardware-accelerated crypto peripheral that can
+speed up AES128, AES256, SHA1, SHA256 and several other cryptographic
+computations.
+
+A peripheral driver interface is proposed, but not yet implemented.
+
+### Usage of EMLIB
+This port makes uses of EMLIB by Silicon Labs to abstract peripheral registers.
+While some overhead is to be expected, it ensures proper setup of devices,
+provides chip errata and simplifies development. The exact overhead depends on
+the application and peripheral usage, but the largest overhead is expected
+during peripheral setup. A lot of read/write/get/set methods are implemented as
+inline methods or macros (which have no overhead).
+
+Another advantage of EMLIB are the included assertions. These assertions ensure
+that peripherals are used properly. To enable this, pass `DEBUG_EFM` to your
+compiler.
+
+### Pin locations
+The EFM32 platform supports peripherals to be mapped to different pins
+(predefined locations). The definitions in `periph_conf.h` mostly consist of a
+location number and the actual pins. The actual pins are required to configure
+the pins via GPIO driver, while the location is used to map the peripheral to
+these pins.
+
+In other words, these definitions must match. Refer to the data sheet for more
+information.
+
+This MCU has extended pin mapping support. Each pin of a peripheral can be
+connected separately to one of the predefined pins for that peripheral.
+
+## Flashing the device
+To flash, [SEGGER JLink](https://www.segger.com/jlink-software.html) is
+required.
+
+Flashing is supported by RIOT-OS using the command below:
+
+```
+make flash
+```
+
+To run the GDB debugger, use the command:
+
+```
+make debug
+```
+
+Or, to connect with your own debugger:
+
+```
+make debug-server
+```
+
+Some boards have (limited) support for emulation, which can be started with:
+
+```
+make emulate
+```
+
+## Supported Toolchains
+For using the Silicon Labs SLTB009A starter kit we strongly recommend
+the usage of the [GNU Tools for ARM Embedded Processors](https://developer.arm.com/open-source/gnu-toolchain/gnu-rm)
+toolchain.
+
+## License information
+* Silicon Labs' EMLIB: zlib-style license (permits distribution of source).
+ */
--- a/boards/sltb009a/include/board.h
+++ b/boards/sltb009a/include/board.h
@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2015-2020 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_sltb009a
+ * @{
+ *
+ * @file
+ * @brief       Board specific definitions for the SLTB009A starter kit
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author      Bas Stottelaar <basstottelaar@gmail.com>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include "cpu.h"
+#include "periph_conf.h"
+#include "periph/gpio.h"
+#include "periph/spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    Xtimer configuration
+ *
+ * The timer runs at 250 kHz to increase accuracy, or at 32.768 kHz if
+ * LETIMER is used.
+ * @{
+ */
+#if IS_ACTIVE(CONFIG_EFM32_XTIMER_USE_LETIMER)
+#define XTIMER_DEV          (TIMER_DEV(1))
+#define XTIMER_HZ           (32768UL)
+#define XTIMER_WIDTH        (16)
+#else
+#define XTIMER_DEV          (TIMER_DEV(0))
+#define XTIMER_HZ           (250000UL)
+#define XTIMER_WIDTH        (16)
+#endif
+#define XTIMER_CHAN         (0)
+/** @} */
+
+/**
+ * @name    VCOM interface enable pin definition
+ * @{
+ */
+#define VCOM_EN_PIN         GPIO_PIN(PA, 15)
+/** @} */
+
+/**
+ * @name    Push button pin definitions
+ * @{
+ */
+#define PB0_PIN             GPIO_PIN(PD, 5)
+#define PB1_PIN             GPIO_PIN(PD, 8)
+/** @} */
+
+/**
+ * @name    LED pin definitions
+ * @{
+ */
+#define LED0R_PIN           GPIO_PIN(PA, 12)
+#define LED0G_PIN           GPIO_PIN(PA, 13)
+#define LED0B_PIN           GPIO_PIN(PA, 14)
+#define LED1R_PIN           GPIO_PIN(PD, 6)
+#define LED1G_PIN           GPIO_PIN(PF, 12)
+#define LED1B_PIN           GPIO_PIN(PE, 12)
+#define LED0_PIN            LED0R_PIN
+#define LED1_PIN            LED1R_PIN
+/** @} */
+
+/**
+ * @name    Macros for controlling the on-board LEDs
+ * @{
+ */
+#define LED0_ON             gpio_set(LED0_PIN)
+#define LED0_OFF            gpio_clear(LED0_PIN)
+#define LED0_TOGGLE         gpio_toggle(LED0_PIN)
+#define LED1_ON             gpio_set(LED1_PIN)
+#define LED1_OFF            gpio_clear(LED1_PIN)
+#define LED1_TOGGLE         gpio_toggle(LED1_PIN)
+/** @} */
+
+/**
+ * @name    Core temperature sensor configuration
+ *
+ * Connection to the on-chip temperature sensor.
+ * @{
+ */
+#define CORETEMP_ADC        ADC_LINE(0)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */
--- a/boards/sltb009a/include/gpio_params.h
+++ b/boards/sltb009a/include/gpio_params.h
@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2016-2020 Bas Stottelaar <basstottelaar@gmail.com>
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_sltb009a
+ * @{
+ *
+ * @file
+ * @brief       Board specific configuration of direct mapped GPIOs
+ *
+ * @author      Bas Stottelaar <basstottelaar@gmail.com>
+ */
+
+#ifndef GPIO_PARAMS_H
+#define GPIO_PARAMS_H
+
+#include "board.h"
+#include "saul/periph.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief    GPIO pin configuration
+ */
+static const  saul_gpio_params_t saul_gpio_params[] =
+{
+    {
+        .name = "LED 0",
+        .pin = LED0_PIN,
+        .mode = GPIO_OUT
+    },
+    {
+        .name = "LED 1",
+        .pin = LED1_PIN,
+        .mode = GPIO_OUT
+    },
+    {
+        .name = "Button 1",
+        .pin = PB0_PIN,
+        .mode = GPIO_IN_PU,
+        .flags = SAUL_GPIO_INVERTED
+    },
+    {
+        .name = "Button 2",
+        .pin = PB1_PIN,
+        .mode = GPIO_IN_PU,
+        .flags = SAUL_GPIO_INVERTED
+    }
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIO_PARAMS_H */
+/** @} */
--- a/boards/sltb009a/include/periph_conf.h
+++ b/boards/sltb009a/include/periph_conf.h
@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2015-2020 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_sltb009a
+ * @{
+ *
+ * @file
+ * @brief       Configuration of CPU peripherals for the SLTB009A starter kit
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author      Bas Stottelaar <basstottelaar@gmail.com>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "cpu.h"
+#include "periph_cpu.h"
+#include "em_cmu.h"
+#include "usbdev_synopsys_dwc2.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    Clock configuration
+ * @{
+ */
+#ifndef CLOCK_HF
+#define CLOCK_HF            cmuSelect_HFXO
+#endif
+#ifndef CLOCK_CORE_DIV
+#define CLOCK_CORE_DIV      cmuClkDiv_1
+#endif
+#ifndef CLOCK_LFA
+#define CLOCK_LFA           cmuSelect_LFXO
+#endif
+#ifndef CLOCK_LFB
+#define CLOCK_LFB           cmuSelect_LFXO
+#endif
+#ifndef CLOCK_LFE
+#define CLOCK_LFE           cmuSelect_LFXO
+#endif
+/** @} */
+
+/**
+ * @name    ADC configuration
+ * @{
+ */
+static const adc_conf_t adc_config[] = {
+    {
+        .dev = ADC0,
+        .cmu = cmuClock_ADC0,
+    }
+};
+
+static const adc_chan_conf_t adc_channel_config[] = {
+    {
+        .dev = 0,
+        .input = adcPosSelTEMP,
+        .reference = adcRef1V25,
+        .acq_time = adcAcqTime8
+    },
+    {
+        .dev = 0,
+        .input = adcPosSelAVDD,
+        .reference = adcRef5V,
+        .acq_time = adcAcqTime8
+    }
+};
+
+#define ADC_DEV_NUMOF       ARRAY_SIZE(adc_config)
+#define ADC_NUMOF           ARRAY_SIZE(adc_channel_config)
+/** @} */
+
+/**
+ * @name    I2C configuration
+ * @{
+ */
+static const i2c_conf_t i2c_config[] = {
+    {
+        .dev = I2C0,
+        .sda_pin = GPIO_PIN(PE, 4),
+        .scl_pin = GPIO_PIN(PE, 5),
+        .loc = I2C_ROUTELOC0_SDALOC_LOC7 |
+               I2C_ROUTELOC0_SCLLOC_LOC7,
+        .cmu = cmuClock_I2C0,
+        .irq = I2C0_IRQn,
+        .speed = I2C_SPEED_NORMAL
+    }
+};
+
+#define I2C_NUMOF           ARRAY_SIZE(i2c_config)
+#define I2C_0_ISR           isr_i2c0
+/** @} */
+
+/**
+ * @name    RTT configuration
+ * @{
+ */
+#ifndef RTT_FREQUENCY
+#define RTT_FREQUENCY       (1U)              /* in Hz */
+#endif
+/** @} */
+
+/**
+ * @name    SPI configuration
+ * @{
+ */
+static const spi_dev_t spi_config[] = {
+    {
+        .dev = USART3,
+        .mosi_pin = GPIO_PIN(PA, 0),
+        .miso_pin = GPIO_PIN(PA, 1),
+        .clk_pin = GPIO_PIN(PA, 2),
+        .loc = USART_ROUTELOC0_RXLOC_LOC0 |
+               USART_ROUTELOC0_TXLOC_LOC0 |
+               USART_ROUTELOC0_CLKLOC_LOC0,
+        .cmu = cmuClock_USART3,
+        .irq = USART3_RX_IRQn
+    }
+};
+
+#define SPI_NUMOF           ARRAY_SIZE(spi_config)
+/** @} */
+
+/**
+ * @name    Timer configuration
+ *
+ * The implementation uses two timers in cascade mode.
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+    {
+        .prescaler = {
+            .dev = TIMER0,
+            .cmu = cmuClock_TIMER0
+        },
+        .timer = {
+            .dev = TIMER1,
+            .cmu = cmuClock_TIMER1
+        },
+        .irq = TIMER1_IRQn,
+        .channel_numof = 3
+    },
+    {
+        .prescaler = {
+            .dev = NULL,
+            .cmu = cmuClock_LETIMER0
+        },
+        .timer = {
+            .dev = LETIMER0,
+            .cmu = cmuClock_LETIMER0
+        },
+        .irq = LETIMER0_IRQn,
+        .channel_numof = 2
+    }
+};
+
+#define TIMER_NUMOF         ARRAY_SIZE(timer_config)
+#define TIMER_0_ISR         isr_timer1
+#define TIMER_1_ISR         isr_letimer0
+/** @} */
+
+/**
+ * @name    UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+    {
+        .dev = USART0,
+        .rx_pin = GPIO_PIN(PE, 6),
+        .tx_pin = GPIO_PIN(PE, 7),
+        .loc = USART_ROUTELOC0_RXLOC_LOC1 |
+               USART_ROUTELOC0_TXLOC_LOC1,
+        .cmu = cmuClock_USART0,
+        .irq = USART0_RX_IRQn
+    },
+    {
+        .dev = LEUART0,
+        .rx_pin = GPIO_PIN(PD, 11),
+        .tx_pin = GPIO_PIN(PD, 10),
+        .loc = LEUART_ROUTELOC0_RXLOC_LOC0 |
+               LEUART_ROUTELOC0_TXLOC_LOC0,
+        .cmu = cmuClock_LEUART0,
+        .irq = LEUART0_IRQn
+    }
+};
+
+#define UART_NUMOF          ARRAY_SIZE(uart_config)
+#define UART_0_ISR_RX       isr_usart0_rx
+#define UART_1_ISR_RX       isr_leuart0
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */
--- a/cpu/efm32/Makefile
+++ b/cpu/efm32/Makefile
@ -7,6 +7,9 @@ DIRS += $(RIOTCPU)/cortexm_common
 ifneq (,$(filter cpu_efm32gg,$(USEMODULE)))
  DIRS += families/efm32gg
 endif
+ifneq (,$(filter cpu_efm32gg12b,$(USEMODULE)))
+  DIRS += families/efm32gg12b
+endif
 ifneq (,$(filter cpu_efm32hg,$(USEMODULE)))
  DIRS += families/efm32hg
 endif
--- a/cpu/efm32/families/efm32gg12b/Kconfig
+++ b/cpu/efm32/families/efm32gg12b/Kconfig
@ -0,0 +1,398 @@
+# Copyright (c) 2020 HAW Hamburg
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+
+config CPU_FAM_EFM32GG12B
+    bool
+    select CPU_CORE_CORTEX_M4F
+    select CPU_COMMON_EFM32
+    select CPU_EFM32_SERIES1
+    select HAS_PERIPH_HWRNG
+    select HAS_CORTEXM_MPU
+
+config MODULE_CPU_EFM32GG12B
+    bool
+    depends on CPU_FAM_EFM32GG12B
+    depends on TEST_KCONFIG
+    default y
+    help
+        EFM32GG12B family-specific code.
+
+## CPU Models
+config CPU_MODEL_EFM32GG12B810F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B390F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B130F512IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B130F512GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B110F1024IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B110F1024GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B310F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B310F1024GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B390F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B130F512GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B130F512IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B330F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B330F512GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B110F1024GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B110F1024IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+## Common CPU symbols
+config CPU_FAM
+    default "efm32gg12b" if CPU_FAM_EFM32GG12B
+
+config CPU_MODEL
+    default "efm32gg12b810f1024gl112" if CPU_MODEL_EFM32GG12B810F1024GL112
+    default "efm32gg12b830f512gm64"   if CPU_MODEL_EFM32GG12B830F512GM64
+    default "efm32gg12b430f512iq100"  if CPU_MODEL_EFM32GG12B430F512IQ100
+    default "efm32gg12b830f512iq64"   if CPU_MODEL_EFM32GG12B830F512IQ64
+    default "efm32gg12b830f512il120"  if CPU_MODEL_EFM32GG12B830F512IL120
+    default "efm32gg12b390f1024gl112" if CPU_MODEL_EFM32GG12B390F1024GL112
+    default "efm32gg12b410f1024im64"  if CPU_MODEL_EFM32GG12B410F1024IM64
+    default "efm32gg12b410f1024gq64"  if CPU_MODEL_EFM32GG12B410F1024GQ64
+    default "efm32gg12b130f512iq64"   if CPU_MODEL_EFM32GG12B130F512IQ64
+    default "efm32gg12b130f512gm64"   if CPU_MODEL_EFM32GG12B130F512GM64
+    default "efm32gg12b530f512il112"  if CPU_MODEL_EFM32GG12B530F512IL112
+    default "efm32gg12b110f1024iq64"  if CPU_MODEL_EFM32GG12B110F1024IQ64
+    default "efm32gg12b110f1024gm64"  if CPU_MODEL_EFM32GG12B110F1024GM64
+    default "efm32gg12b530f512iq100"  if CPU_MODEL_EFM32GG12B530F512IQ100
+    default "efm32gg12b410f1024il120" if CPU_MODEL_EFM32GG12B410F1024IL120
+    default "efm32gg12b510f1024gl120" if CPU_MODEL_EFM32GG12B510F1024GL120
+    default "efm32gg12b430f512gm64"   if CPU_MODEL_EFM32GG12B430F512GM64
+    default "efm32gg12b430f512iq64"   if CPU_MODEL_EFM32GG12B430F512IQ64
+    default "efm32gg12b510f1024gq64"  if CPU_MODEL_EFM32GG12B510F1024GQ64
+    default "efm32gg12b510f1024im64"  if CPU_MODEL_EFM32GG12B510F1024IM64
+    default "efm32gg12b430f512il112"  if CPU_MODEL_EFM32GG12B430F512IL112
+    default "efm32gg12b810f1024gq100" if CPU_MODEL_EFM32GG12B810F1024GQ100
+    default "efm32gg12b510f1024gl112" if CPU_MODEL_EFM32GG12B510F1024GL112
+    default "efm32gg12b530f512gq64"   if CPU_MODEL_EFM32GG12B530F512GQ64
+    default "efm32gg12b530f512im64"   if CPU_MODEL_EFM32GG12B530F512IM64
+    default "efm32gg12b410f1024il112" if CPU_MODEL_EFM32GG12B410F1024IL112
+    default "efm32gg12b810f1024im64"  if CPU_MODEL_EFM32GG12B810F1024IM64
+    default "efm32gg12b810f1024gq64"  if CPU_MODEL_EFM32GG12B810F1024GQ64
+    default "efm32gg12b830f512iq100"  if CPU_MODEL_EFM32GG12B830F512IQ100
+    default "efm32gg12b430f512il120"  if CPU_MODEL_EFM32GG12B430F512IL120
+    default "efm32gg12b830f512il112"  if CPU_MODEL_EFM32GG12B830F512IL112
+    default "efm32gg12b810f1024gl120" if CPU_MODEL_EFM32GG12B810F1024GL120
+    default "efm32gg12b530f512il120"  if CPU_MODEL_EFM32GG12B530F512IL120
+    default "efm32gg12b410f1024iq100" if CPU_MODEL_EFM32GG12B410F1024IQ100
+    default "efm32gg12b510f1024gq100" if CPU_MODEL_EFM32GG12B510F1024GQ100
+    default "efm32gg12b830f512gl112"  if CPU_MODEL_EFM32GG12B830F512GL112
+    default "efm32gg12b810f1024il120" if CPU_MODEL_EFM32GG12B810F1024IL120
+    default "efm32gg12b530f512gl120"  if CPU_MODEL_EFM32GG12B530F512GL120
+    default "efm32gg12b310f1024gl112" if CPU_MODEL_EFM32GG12B310F1024GL112
+    default "efm32gg12b810f1024gm64"  if CPU_MODEL_EFM32GG12B810F1024GM64
+    default "efm32gg12b810f1024iq64"  if CPU_MODEL_EFM32GG12B810F1024IQ64
+    default "efm32gg12b530f512iq64"   if CPU_MODEL_EFM32GG12B530F512IQ64
+    default "efm32gg12b530f512gm64"   if CPU_MODEL_EFM32GG12B530F512GM64
+    default "efm32gg12b410f1024gq100" if CPU_MODEL_EFM32GG12B410F1024GQ100
+    default "efm32gg12b510f1024iq100" if CPU_MODEL_EFM32GG12B510F1024IQ100
+    default "efm32gg12b510f1024il112" if CPU_MODEL_EFM32GG12B510F1024IL112
+    default "efm32gg12b410f1024gl112" if CPU_MODEL_EFM32GG12B410F1024GL112
+    default "efm32gg12b310f1024gq100" if CPU_MODEL_EFM32GG12B310F1024GQ100
+    default "efm32gg12b390f512gl112"  if CPU_MODEL_EFM32GG12B390F512GL112
+    default "efm32gg12b430f512gl120"  if CPU_MODEL_EFM32GG12B430F512GL120
+    default "efm32gg12b830f512gq100"  if CPU_MODEL_EFM32GG12B830F512GQ100
+    default "efm32gg12b530f512gq100"  if CPU_MODEL_EFM32GG12B530F512GQ100
+    default "efm32gg12b130f512gq64"   if CPU_MODEL_EFM32GG12B130F512GQ64
+    default "efm32gg12b410f1024gl120" if CPU_MODEL_EFM32GG12B410F1024GL120
+    default "efm32gg12b130f512im64"   if CPU_MODEL_EFM32GG12B130F512IM64
+    default "efm32gg12b410f1024gm64"  if CPU_MODEL_EFM32GG12B410F1024GM64
+    default "efm32gg12b410f1024iq64"  if CPU_MODEL_EFM32GG12B410F1024IQ64
+    default "efm32gg12b510f1024il120" if CPU_MODEL_EFM32GG12B510F1024IL120
+    default "efm32gg12b430f512gl112"  if CPU_MODEL_EFM32GG12B430F512GL112
+    default "efm32gg12b830f512im64"   if CPU_MODEL_EFM32GG12B830F512IM64
+    default "efm32gg12b330f512gl112"  if CPU_MODEL_EFM32GG12B330F512GL112
+    default "efm32gg12b830f512gq64"   if CPU_MODEL_EFM32GG12B830F512GQ64
+    default "efm32gg12b810f1024iq100" if CPU_MODEL_EFM32GG12B810F1024IQ100
+    default "efm32gg12b810f1024il112" if CPU_MODEL_EFM32GG12B810F1024IL112
+    default "efm32gg12b830f512gl120"  if CPU_MODEL_EFM32GG12B830F512GL120
+    default "efm32gg12b430f512gq100"  if CPU_MODEL_EFM32GG12B430F512GQ100
+    default "efm32gg12b330f512gq100"  if CPU_MODEL_EFM32GG12B330F512GQ100
+    default "efm32gg12b510f1024iq64"  if CPU_MODEL_EFM32GG12B510F1024IQ64
+    default "efm32gg12b510f1024gm64"  if CPU_MODEL_EFM32GG12B510F1024GM64
+    default "efm32gg12b430f512im64"   if CPU_MODEL_EFM32GG12B430F512IM64
+    default "efm32gg12b430f512gq64"   if CPU_MODEL_EFM32GG12B430F512GQ64
+    default "efm32gg12b110f1024gq64"  if CPU_MODEL_EFM32GG12B110F1024GQ64
+    default "efm32gg12b110f1024im64"  if CPU_MODEL_EFM32GG12B110F1024IM64
+    default "efm32gg12b530f512gl112"  if CPU_MODEL_EFM32GG12B530F512GL112
--- a/cpu/efm32/families/efm32gg12b/Makefile
+++ b/cpu/efm32/families/efm32gg12b/Makefile
@ -0,0 +1,6 @@
+MODULE = cpu_efm32gg12b
+
+# (file triggers compiler bug. see #5775)
+SRC_NOLTO += vectors.c
+
+include $(RIOTBASE)/Makefile.base
--- a/cpu/efm32/families/efm32gg12b/Makefile.include
+++ b/cpu/efm32/families/efm32gg12b/Makefile.include
@ -0,0 +1,7 @@
+# Find the header file that should exist if the CPU is supported. Only headers
+# for supported boards are included, but to support another CPU, it should be
+# as easy as adding the header file only.
+EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efm32gg12b/include/vendor/$(CPU_MODEL).h)
+
+# include vendor device headers
+INCLUDES += -I$(RIOTCPU)/efm32/families/efm32gg12b/include/vendor
--- a/cpu/efm32/families/efm32gg12b/efm32-info.mk
+++ b/cpu/efm32/families/efm32gg12b/efm32-info.mk
@ -0,0 +1,79 @@
+# This file is automatically generated, and should not be changed. There is
+# probably little reason to edit this file anyway, since it should already
+# contain all information for the EFM32GG12B family of CPUs.
+
+# Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio?
+EFM32_INFO_efm32gg12b810f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gm64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512iq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512iq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512il120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b390f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024im64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b130f512iq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b130f512gm64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512il112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b110f1024iq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b110f1024gm64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512iq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gm64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512iq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024im64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512il112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512im64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024il112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024im64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024gq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512iq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512il120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512il112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512il120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gl120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b310f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024gm64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024iq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512iq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gm64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024il112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b310f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b390f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gl120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b130f512gq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b130f512im64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gm64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024iq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512im64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b330f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024il112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gl120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b330f512gq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024iq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gm64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512im64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b110f1024gq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b110f1024im64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b110f1024gm64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b110f1024gm64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b110f1024gq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b110f1024gq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b110f1024im64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b110f1024im64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b110f1024iq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b110f1024iq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b130f512gm64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b130f512gm64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b130f512gq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b130f512gq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b130f512im64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b130f512im64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b130f512iq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b130f512iq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b310f1024gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b310f1024gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b310f1024gq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b310f1024gq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b330f512gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b330f512gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b330f512gq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b330f512gq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b390f1024gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b390f1024gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b390f512gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b390f512gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gl120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gl120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gm64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gm64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024gq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024il112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024il112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024il120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024il120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024im64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024im64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024iq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024iq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024iq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b410f1024iq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gl120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gl120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gm64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gm64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512gq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512il112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512il112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512il120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512il120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512im64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512im64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512iq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512iq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512iq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b430f512iq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gl120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gl120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gm64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gm64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024gq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024il112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024il112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024il120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024il120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024im64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024im64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024iq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024iq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024iq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b510f1024iq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gl120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gl120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gm64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gm64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512gq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512il112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512il112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512il120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512il120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512im64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512im64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512iq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512iq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512iq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b530f512iq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gl120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gl120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gm64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gm64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024gq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024il112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024il112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024il120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024il120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024im64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024im64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024iq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024iq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024iq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b810f1024iq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gl112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gl112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gl120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gl120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gm64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gm64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512gq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512il112.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512il112.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512il120.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512il120.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512im64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512im64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512iq100.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512iq100.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512iq64.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b830f512iq64.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_acmp.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_acmp.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_adc.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_adc.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_af_pins.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_af_pins.h
@ -0,0 +1,325 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_AF_PINS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_Alternate_Function Alternate Function
+ * @{
+ * @defgroup EFM32GG12B_AF_Pins Alternate Function Pins
+ * @{
+ ******************************************************************************/
+
+#define AF_CMU_CLK0_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 12 :  -1)                                /**< Pin number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? -1 : (i) == 4 ? 3 : (i) == 5 ? 11 :  -1)                                /**< Pin number for AF_CMU_CLK1 location number i */
+#define AF_CMU_CLK2_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? -1 : (i) == 4 ? 3 : (i) == 5 ? 10 :  -1)                                 /**< Pin number for AF_CMU_CLK2 location number i */
+#define AF_CMU_CLKI0_PIN(i)         ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 :  -1) /**< Pin number for AF_CMU_CLKI0 location number i */
+#define AF_CMU_DIGEXTCLK_PIN(i)     ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_CMU_DIGEXTCLK location number i */
+#define AF_CMU_IOPOVR_PIN(i)        ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_CMU_IOPOVR location number i */
+#define AF_CMU_IONOVR_PIN(i)        ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_CMU_IONOVR location number i */
+#define AF_LESENSE_CH0_PIN(i)       ((i) == 0 ? 0 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH0 location number i */
+#define AF_LESENSE_CH1_PIN(i)       ((i) == 0 ? 1 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH1 location number i */
+#define AF_LESENSE_CH2_PIN(i)       ((i) == 0 ? 2 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH2 location number i */
+#define AF_LESENSE_CH3_PIN(i)       ((i) == 0 ? 3 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH3 location number i */
+#define AF_LESENSE_CH4_PIN(i)       ((i) == 0 ? 4 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH4 location number i */
+#define AF_LESENSE_CH5_PIN(i)       ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH5 location number i */
+#define AF_LESENSE_CH6_PIN(i)       ((i) == 0 ? 6 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH6 location number i */
+#define AF_LESENSE_CH7_PIN(i)       ((i) == 0 ? 7 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH7 location number i */
+#define AF_LESENSE_CH8_PIN(i)       ((i) == 0 ? 8 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH8 location number i */
+#define AF_LESENSE_CH9_PIN(i)       ((i) == 0 ? 9 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH9 location number i */
+#define AF_LESENSE_CH10_PIN(i)      ((i) == 0 ? 10 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH10 location number i */
+#define AF_LESENSE_CH11_PIN(i)      ((i) == 0 ? 11 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH11 location number i */
+#define AF_LESENSE_CH12_PIN(i)      ((i) == 0 ? 12 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH12 location number i */
+#define AF_LESENSE_CH13_PIN(i)      ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH13 location number i */
+#define AF_LESENSE_CH14_PIN(i)      ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH14 location number i */
+#define AF_LESENSE_CH15_PIN(i)      ((i) == 0 ? 15 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH15 location number i */
+#define AF_LESENSE_ALTEX0_PIN(i)    ((i) == 0 ? 6 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX0 location number i */
+#define AF_LESENSE_ALTEX1_PIN(i)    ((i) == 0 ? 7 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX1 location number i */
+#define AF_LESENSE_ALTEX2_PIN(i)    ((i) == 0 ? 3 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX2 location number i */
+#define AF_LESENSE_ALTEX3_PIN(i)    ((i) == 0 ? 4 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX3 location number i */
+#define AF_LESENSE_ALTEX4_PIN(i)    ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX4 location number i */
+#define AF_LESENSE_ALTEX5_PIN(i)    ((i) == 0 ? 11 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX5 location number i */
+#define AF_LESENSE_ALTEX6_PIN(i)    ((i) == 0 ? 12 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX6 location number i */
+#define AF_LESENSE_ALTEX7_PIN(i)    ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX7 location number i */
+#define AF_EBI_AD00_PIN(i)          ((i) == 0 ? 8 : (i) == 1 ? 0 :  -1)                                                                                               /**< Pin number for AF_EBI_AD00 location number i */
+#define AF_EBI_AD01_PIN(i)          ((i) == 0 ? 9 : (i) == 1 ? 1 :  -1)                                                                                               /**< Pin number for AF_EBI_AD01 location number i */
+#define AF_EBI_AD02_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 2 :  -1)                                                                                              /**< Pin number for AF_EBI_AD02 location number i */
+#define AF_EBI_AD03_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_EBI_AD03 location number i */
+#define AF_EBI_AD04_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 4 :  -1)                                                                                              /**< Pin number for AF_EBI_AD04 location number i */
+#define AF_EBI_AD05_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_EBI_AD05 location number i */
+#define AF_EBI_AD06_PIN(i)          ((i) == 0 ? 14 : (i) == 1 ? 6 :  -1)                                                                                              /**< Pin number for AF_EBI_AD06 location number i */
+#define AF_EBI_AD07_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 0 :  -1)                                                                                              /**< Pin number for AF_EBI_AD07 location number i */
+#define AF_EBI_AD08_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 1 :  -1)                                                                                              /**< Pin number for AF_EBI_AD08 location number i */
+#define AF_EBI_AD09_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                               /**< Pin number for AF_EBI_AD09 location number i */
+#define AF_EBI_AD10_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                               /**< Pin number for AF_EBI_AD10 location number i */
+#define AF_EBI_AD11_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 4 :  -1)                                                                                               /**< Pin number for AF_EBI_AD11 location number i */
+#define AF_EBI_AD12_PIN(i)          ((i) == 0 ? 3 : (i) == 1 ? 5 :  -1)                                                                                               /**< Pin number for AF_EBI_AD12 location number i */
+#define AF_EBI_AD13_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 7 :  -1)                                                                                               /**< Pin number for AF_EBI_AD13 location number i */
+#define AF_EBI_AD14_PIN(i)          ((i) == 0 ? 5 : (i) == 1 ? 8 :  -1)                                                                                               /**< Pin number for AF_EBI_AD14 location number i */
+#define AF_EBI_AD15_PIN(i)          ((i) == 0 ? 6 : (i) == 1 ? 9 :  -1)                                                                                               /**< Pin number for AF_EBI_AD15 location number i */
+#define AF_EBI_CS0_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 :  -1)                                                 /**< Pin number for AF_EBI_CS0 location number i */
+#define AF_EBI_CS1_PIN(i)           ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 :  -1)                                                /**< Pin number for AF_EBI_CS1 location number i */
+#define AF_EBI_CS2_PIN(i)           ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 :  -1)                                               /**< Pin number for AF_EBI_CS2 location number i */
+#define AF_EBI_CS3_PIN(i)           ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 :  -1)                                               /**< Pin number for AF_EBI_CS3 location number i */
+#define AF_EBI_ARDY_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 :  -1)                               /**< Pin number for AF_EBI_ARDY location number i */
+#define AF_EBI_ALE_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 :  -1)                                 /**< Pin number for AF_EBI_ALE location number i */
+#define AF_EBI_WEn_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 :  -1)                                  /**< Pin number for AF_EBI_WEn location number i */
+#define AF_EBI_REn_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 :  -1)                                 /**< Pin number for AF_EBI_REn location number i */
+#define AF_EBI_BL0_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 :  -1)                                  /**< Pin number for AF_EBI_BL0 location number i */
+#define AF_EBI_BL1_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 :  -1)                                  /**< Pin number for AF_EBI_BL1 location number i */
+#define AF_EBI_NANDWEn_PIN(i)       ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 :  -1)                               /**< Pin number for AF_EBI_NANDWEn location number i */
+#define AF_EBI_NANDREn_PIN(i)       ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 :  -1)                                /**< Pin number for AF_EBI_NANDREn location number i */
+#define AF_EBI_A00_PIN(i)           ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                               /**< Pin number for AF_EBI_A00 location number i */
+#define AF_EBI_A01_PIN(i)           ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                              /**< Pin number for AF_EBI_A01 location number i */
+#define AF_EBI_A02_PIN(i)           ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 8 :  -1)                                                              /**< Pin number for AF_EBI_A02 location number i */
+#define AF_EBI_A03_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                               /**< Pin number for AF_EBI_A03 location number i */
+#define AF_EBI_A04_PIN(i)           ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? 10 :  -1)                                                              /**< Pin number for AF_EBI_A04 location number i */
+#define AF_EBI_A05_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 11 :  -1)                                                               /**< Pin number for AF_EBI_A05 location number i */
+#define AF_EBI_A06_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_EBI_A06 location number i */
+#define AF_EBI_A07_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 13 :  -1)                                                               /**< Pin number for AF_EBI_A07 location number i */
+#define AF_EBI_A08_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 14 :  -1)                                                               /**< Pin number for AF_EBI_A08 location number i */
+#define AF_EBI_A09_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                                /**< Pin number for AF_EBI_A09 location number i */
+#define AF_EBI_A10_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 10 :  -1)                                                               /**< Pin number for AF_EBI_A10 location number i */
+#define AF_EBI_A11_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 11 :  -1)                                                               /**< Pin number for AF_EBI_A11 location number i */
+#define AF_EBI_A12_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? -1 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_EBI_A12 location number i */
+#define AF_EBI_A13_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_EBI_A13 location number i */
+#define AF_EBI_A14_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                                /**< Pin number for AF_EBI_A14 location number i */
+#define AF_EBI_A15_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_EBI_A15 location number i */
+#define AF_EBI_A16_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                                /**< Pin number for AF_EBI_A16 location number i */
+#define AF_EBI_A17_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                                /**< Pin number for AF_EBI_A17 location number i */
+#define AF_EBI_A18_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                                /**< Pin number for AF_EBI_A18 location number i */
+#define AF_EBI_A19_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 6 :  -1)                                                                /**< Pin number for AF_EBI_A19 location number i */
+#define AF_EBI_A20_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A20 location number i */
+#define AF_EBI_A21_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A21 location number i */
+#define AF_EBI_A22_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                               /**< Pin number for AF_EBI_A22 location number i */
+#define AF_EBI_A23_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                               /**< Pin number for AF_EBI_A23 location number i */
+#define AF_EBI_A24_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? 6 :  -1)                                                                /**< Pin number for AF_EBI_A24 location number i */
+#define AF_EBI_A25_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A25 location number i */
+#define AF_EBI_A26_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 8 :  -1)                                                                /**< Pin number for AF_EBI_A26 location number i */
+#define AF_EBI_A27_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                                /**< Pin number for AF_EBI_A27 location number i */
+#define AF_EBI_CSTFT_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_EBI_CSTFT location number i */
+#define AF_EBI_DCLK_PIN(i)          ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                                /**< Pin number for AF_EBI_DCLK location number i */
+#define AF_EBI_DTEN_PIN(i)          ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_EBI_DTEN location number i */
+#define AF_EBI_VSNC_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Pin number for AF_EBI_VSNC location number i */
+#define AF_EBI_HSNC_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Pin number for AF_EBI_HSNC location number i */
+#define AF_SDIO_CLK_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 14 :  -1)                                                                                             /**< Pin number for AF_SDIO_CLK location number i */
+#define AF_SDIO_CMD_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 15 :  -1)                                                                                             /**< Pin number for AF_SDIO_CMD location number i */
+#define AF_SDIO_DAT0_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 0 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT0 location number i */
+#define AF_SDIO_DAT1_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 1 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT1 location number i */
+#define AF_SDIO_DAT2_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 2 :  -1)                                                                                               /**< Pin number for AF_SDIO_DAT2 location number i */
+#define AF_SDIO_DAT3_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 3 :  -1)                                                                                               /**< Pin number for AF_SDIO_DAT3 location number i */
+#define AF_SDIO_DAT4_PIN(i)         ((i) == 0 ? 12 : (i) == 1 ? 4 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT4 location number i */
+#define AF_SDIO_DAT5_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT5 location number i */
+#define AF_SDIO_DAT6_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT6 location number i */
+#define AF_SDIO_DAT7_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 4 :  -1)                                                                                               /**< Pin number for AF_SDIO_DAT7 location number i */
+#define AF_SDIO_CD_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 4 : (i) == 2 ? 6 : (i) == 3 ? 10 :  -1)                                                                /**< Pin number for AF_SDIO_CD location number i */
+#define AF_SDIO_WP_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 :  -1)                                                                /**< Pin number for AF_SDIO_WP location number i */
+#define AF_PDM_CLK_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 0 :  -1)                                                 /**< Pin number for AF_PDM_CLK location number i */
+#define AF_PDM_DAT0_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 11 : (i) == 4 ? 1 :  -1)                                                 /**< Pin number for AF_PDM_DAT0 location number i */
+#define AF_PDM_DAT1_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 8 : (i) == 3 ? 10 : (i) == 4 ? 2 :  -1)                                                /**< Pin number for AF_PDM_DAT1 location number i */
+#define AF_PDM_DAT2_PIN(i)          ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 9 : (i) == 3 ? 9 : (i) == 4 ? 3 :  -1)                                                 /**< Pin number for AF_PDM_DAT2 location number i */
+#define AF_PDM_DAT3_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 13 : (i) == 4 ? 4 :  -1)                                                /**< Pin number for AF_PDM_DAT3 location number i */
+#define AF_PRS_CH0_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 :  -1)                                                               /**< Pin number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_PRS_CH3 location number i */
+#define AF_PRS_CH4_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                                /**< Pin number for AF_PRS_CH4 location number i */
+#define AF_PRS_CH5_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 :  -1)                                                                                /**< Pin number for AF_PRS_CH5 location number i */
+#define AF_PRS_CH6_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 :  -1)                                                                               /**< Pin number for AF_PRS_CH6 location number i */
+#define AF_PRS_CH7_PIN(i)           ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 :  -1)                                                                               /**< Pin number for AF_PRS_CH7 location number i */
+#define AF_PRS_CH8_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 :  -1)                                                                                /**< Pin number for AF_PRS_CH8 location number i */
+#define AF_PRS_CH9_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 :  -1)                                                                               /**< Pin number for AF_PRS_CH9 location number i */
+#define AF_PRS_CH10_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 :  -1)                                                                               /**< Pin number for AF_PRS_CH10 location number i */
+#define AF_PRS_CH11_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 :  -1)                                                                               /**< Pin number for AF_PRS_CH11 location number i */
+#define AF_PRS_CH12_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 :  -1)                                                                               /**< Pin number for AF_PRS_CH12 location number i */
+#define AF_PRS_CH13_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 :  -1)                                                                              /**< Pin number for AF_PRS_CH13 location number i */
+#define AF_PRS_CH14_PIN(i)          ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 :  -1)                                                                              /**< Pin number for AF_PRS_CH14 location number i */
+#define AF_PRS_CH15_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 :  -1)                                                                               /**< Pin number for AF_PRS_CH15 location number i */
+#define AF_CAN0_RX_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? -1 : (i) == 5 ? 14 : (i) == 6 ? 0 :  -1)                  /**< Pin number for AF_CAN0_RX location number i */
+#define AF_CAN0_TX_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? -1 : (i) == 5 ? 15 : (i) == 6 ? 1 :  -1)                 /**< Pin number for AF_CAN0_TX location number i */
+#define AF_CAN1_RX_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 :  -1)                                 /**< Pin number for AF_CAN1_RX location number i */
+#define AF_CAN1_TX_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 :  -1)                                /**< Pin number for AF_CAN1_TX location number i */
+#define AF_TIMER0_CC0_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 :  -1)     /**< Pin number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 :  -1)     /**< Pin number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PIN(i)        ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 :  -1)   /**< Pin number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER0_CC3 location number i */
+#define AF_TIMER0_CDTI0_PIN(i)      ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 :  -1)                                                 /**< Pin number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PIN(i)      ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 :  -1)                                                 /**< Pin number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PIN(i)      ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 :  -1)                                                /**< Pin number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER0_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER0_CDTI3 location number i */
+#define AF_TIMER1_CC0_PIN(i)        ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 :  -1)                 /**< Pin number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 :  -1)                 /**< Pin number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 :  -1)                               /**< Pin number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CC3_PIN(i)        ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 :  -1)               /**< Pin number for AF_TIMER1_CC3 location number i */
+#define AF_TIMER1_CDTI0_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER1_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI3 location number i */
+#define AF_TIMER2_CC0_PIN(i)        ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 :  -1)                                  /**< Pin number for AF_TIMER2_CC0 location number i */
+#define AF_TIMER2_CC1_PIN(i)        ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 :  -1)                                 /**< Pin number for AF_TIMER2_CC1 location number i */
+#define AF_TIMER2_CC2_PIN(i)        ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 :  -1)                               /**< Pin number for AF_TIMER2_CC2 location number i */
+#define AF_TIMER2_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER2_CC3 location number i */
+#define AF_TIMER2_CDTI0_PIN(i)      ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 :  -1)                                                                               /**< Pin number for AF_TIMER2_CDTI0 location number i */
+#define AF_TIMER2_CDTI1_PIN(i)      ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 :  -1)                                                                              /**< Pin number for AF_TIMER2_CDTI1 location number i */
+#define AF_TIMER2_CDTI2_PIN(i)      ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 :  -1)                                                                              /**< Pin number for AF_TIMER2_CDTI2 location number i */
+#define AF_TIMER2_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER2_CDTI3 location number i */
+#define AF_TIMER3_CC0_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 :  -1)   /**< Pin number for AF_TIMER3_CC0 location number i */
+#define AF_TIMER3_CC1_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 :  -1)  /**< Pin number for AF_TIMER3_CC1 location number i */
+#define AF_TIMER3_CC2_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 :  -1)   /**< Pin number for AF_TIMER3_CC2 location number i */
+#define AF_TIMER3_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CC3 location number i */
+#define AF_TIMER3_CDTI0_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI0 location number i */
+#define AF_TIMER3_CDTI1_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI1 location number i */
+#define AF_TIMER3_CDTI2_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI2 location number i */
+#define AF_TIMER3_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI3 location number i */
+#define AF_WTIMER0_CC0_PIN(i)       ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)  /**< Pin number for AF_WTIMER0_CC0 location number i */
+#define AF_WTIMER0_CC1_PIN(i)       ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 :  -1)  /**< Pin number for AF_WTIMER0_CC1 location number i */
+#define AF_WTIMER0_CC2_PIN(i)       ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 :  -1)  /**< Pin number for AF_WTIMER0_CC2 location number i */
+#define AF_WTIMER0_CC3_PIN(i)       (-1)                                                                                                                              /**< Pin number for AF_WTIMER0_CC3 location number i */
+#define AF_WTIMER0_CDTI0_PIN(i)     ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? -1 : (i) == 4 ? 4 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI0 location number i */
+#define AF_WTIMER0_CDTI1_PIN(i)     ((i) == 0 ? 11 : (i) == 1 ? -1 : (i) == 2 ? 13 : (i) == 3 ? -1 : (i) == 4 ? 5 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI1 location number i */
+#define AF_WTIMER0_CDTI2_PIN(i)     ((i) == 0 ? 12 : (i) == 1 ? -1 : (i) == 2 ? 14 : (i) == 3 ? -1 : (i) == 4 ? 6 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI2 location number i */
+#define AF_WTIMER0_CDTI3_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER0_CDTI3 location number i */
+#define AF_WTIMER1_CC0_PIN(i)       ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 :  -1)                                  /**< Pin number for AF_WTIMER1_CC0 location number i */
+#define AF_WTIMER1_CC1_PIN(i)       ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                 /**< Pin number for AF_WTIMER1_CC1 location number i */
+#define AF_WTIMER1_CC2_PIN(i)       ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 :  -1)                                                  /**< Pin number for AF_WTIMER1_CC2 location number i */
+#define AF_WTIMER1_CC3_PIN(i)       ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 :  -1)                                                  /**< Pin number for AF_WTIMER1_CC3 location number i */
+#define AF_WTIMER1_CDTI0_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI0 location number i */
+#define AF_WTIMER1_CDTI1_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI1 location number i */
+#define AF_WTIMER1_CDTI2_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI2 location number i */
+#define AF_WTIMER1_CDTI3_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI3 location number i */
+#define AF_USART0_TX_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 :  -1)                                /**< Pin number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 :  -1)                                /**< Pin number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PIN(i)        ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 :  -1)                               /**< Pin number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PIN(i)         ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 :  -1)                               /**< Pin number for AF_USART0_CS location number i */
+#define AF_USART0_CTS_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 :  -1)                                /**< Pin number for AF_USART0_CTS location number i */
+#define AF_USART0_RTS_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 :  -1)                                 /**< Pin number for AF_USART0_RTS location number i */
+#define AF_USART1_TX_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 :  -1)                   /**< Pin number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 :  -1)                    /**< Pin number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 :  -1)                  /**< Pin number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 :  -1)                   /**< Pin number for AF_USART1_CS location number i */
+#define AF_USART1_CTS_PIN(i)        ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 :  -1)                                 /**< Pin number for AF_USART1_CTS location number i */
+#define AF_USART1_RTS_PIN(i)        ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 :  -1)                                /**< Pin number for AF_USART1_RTS location number i */
+#define AF_USART2_TX_PIN(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 :  -1)                                  /**< Pin number for AF_USART2_TX location number i */
+#define AF_USART2_RX_PIN(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 :  -1)                                  /**< Pin number for AF_USART2_RX location number i */
+#define AF_USART2_CLK_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 :  -1)                                  /**< Pin number for AF_USART2_CLK location number i */
+#define AF_USART2_CS_PIN(i)         ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 :  -1)                                 /**< Pin number for AF_USART2_CS location number i */
+#define AF_USART2_CTS_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 :  -1)                               /**< Pin number for AF_USART2_CTS location number i */
+#define AF_USART2_RTS_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 :  -1)                               /**< Pin number for AF_USART2_RTS location number i */
+#define AF_USART3_TX_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 :  -1)                                                                                /**< Pin number for AF_USART3_TX location number i */
+#define AF_USART3_RX_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 :  -1)                                                                                /**< Pin number for AF_USART3_RX location number i */
+#define AF_USART3_CLK_PIN(i)        ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 :  -1)                                                                                /**< Pin number for AF_USART3_CLK location number i */
+#define AF_USART3_CS_PIN(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_USART3_CS location number i */
+#define AF_USART3_CTS_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 :  -1)                                                                                /**< Pin number for AF_USART3_CTS location number i */
+#define AF_USART3_RTS_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 :  -1)                                                               /**< Pin number for AF_USART3_RTS location number i */
+#define AF_USART4_TX_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 9 :  -1)                                                                                               /**< Pin number for AF_USART4_TX location number i */
+#define AF_USART4_RX_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 10 :  -1)                                                                                              /**< Pin number for AF_USART4_RX location number i */
+#define AF_USART4_CLK_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 11 :  -1)                                                                                              /**< Pin number for AF_USART4_CLK location number i */
+#define AF_USART4_CS_PIN(i)         ((i) == 0 ? 5 : (i) == 1 ? 12 :  -1)                                                                                              /**< Pin number for AF_USART4_CS location number i */
+#define AF_USART4_CTS_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 13 :  -1)                                                                                              /**< Pin number for AF_USART4_CTS location number i */
+#define AF_USART4_RTS_PIN(i)        ((i) == 0 ? 8 : (i) == 1 ? 14 :  -1)                                                                                              /**< Pin number for AF_USART4_RTS location number i */
+#define AF_UART0_TX_PIN(i)          ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 :  -1)                   /**< Pin number for AF_UART0_TX location number i */
+#define AF_UART0_RX_PIN(i)          ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 :  -1)                   /**< Pin number for AF_UART0_RX location number i */
+#define AF_UART0_CLK_PIN(i)         (-1)                                                                                                                              /**< Pin number for AF_UART0_CLK location number i */
+#define AF_UART0_CS_PIN(i)          (-1)                                                                                                                              /**< Pin number for AF_UART0_CS location number i */
+#define AF_UART0_CTS_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 :  -1)                                  /**< Pin number for AF_UART0_CTS location number i */
+#define AF_UART0_RTS_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 :  -1)                                  /**< Pin number for AF_UART0_RTS location number i */
+#define AF_UART1_TX_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 :  -1)                                               /**< Pin number for AF_UART1_TX location number i */
+#define AF_UART1_RX_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 :  -1)                                              /**< Pin number for AF_UART1_RX location number i */
+#define AF_UART1_CLK_PIN(i)         (-1)                                                                                                                              /**< Pin number for AF_UART1_CLK location number i */
+#define AF_UART1_CS_PIN(i)          (-1)                                                                                                                              /**< Pin number for AF_UART1_CS location number i */
+#define AF_UART1_CTS_PIN(i)         ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Pin number for AF_UART1_CTS location number i */
+#define AF_UART1_RTS_PIN(i)         ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 :  -1)                                                /**< Pin number for AF_UART1_RTS location number i */
+#define AF_QSPI0_SCLK_PIN(i)        ((i) == 0 ? 6 : (i) == 1 ? 14 :  -1)                                                                                              /**< Pin number for AF_QSPI0_SCLK location number i */
+#define AF_QSPI0_DQ0_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 2 :  -1)                                                                                               /**< Pin number for AF_QSPI0_DQ0 location number i */
+#define AF_QSPI0_DQ1_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ1 location number i */
+#define AF_QSPI0_DQ2_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 4 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ2 location number i */
+#define AF_QSPI0_DQ3_PIN(i)         ((i) == 0 ? 12 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ3 location number i */
+#define AF_QSPI0_DQ4_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 3 :  -1)                                                                                               /**< Pin number for AF_QSPI0_DQ4 location number i */
+#define AF_QSPI0_DQ5_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 4 :  -1)                                                                                               /**< Pin number for AF_QSPI0_DQ5 location number i */
+#define AF_QSPI0_DQ6_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ6 location number i */
+#define AF_QSPI0_DQ7_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 6 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ7 location number i */
+#define AF_QSPI0_CS0_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 0 :  -1)                                                                                               /**< Pin number for AF_QSPI0_CS0 location number i */
+#define AF_QSPI0_CS1_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 1 :  -1)                                                                                               /**< Pin number for AF_QSPI0_CS1 location number i */
+#define AF_QSPI0_DQS_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 15 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQS location number i */
+#define AF_QSPI0_RST0_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 2 :  -1)                                                                                              /**< Pin number for AF_QSPI0_RST0 location number i */
+#define AF_QSPI0_RST1_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_QSPI0_RST1 location number i */
+#define AF_LEUART0_TX_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 :  -1)                                /**< Pin number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 :  -1)                                /**< Pin number for AF_LEUART0_RX location number i */
+#define AF_LEUART1_TX_PIN(i)        ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                  /**< Pin number for AF_LEUART1_TX location number i */
+#define AF_LEUART1_RX_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 :  -1)                                                  /**< Pin number for AF_LEUART1_RX location number i */
+#define AF_LETIMER0_OUT0_PIN(i)     ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 :  -1)  /**< Pin number for AF_LETIMER0_OUT0 location number i */
+#define AF_LETIMER0_OUT1_PIN(i)     ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 :  -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
+#define AF_LETIMER1_OUT0_PIN(i)     ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 :  -1)                                 /**< Pin number for AF_LETIMER1_OUT0 location number i */
+#define AF_LETIMER1_OUT1_PIN(i)     ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 :  -1)                                 /**< Pin number for AF_LETIMER1_OUT1 location number i */
+#define AF_PCNT0_S0IN_PIN(i)        ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 :  -1)   /**< Pin number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 :  -1)   /**< Pin number for AF_PCNT0_S1IN location number i */
+#define AF_PCNT1_S0IN_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 :  -1)                 /**< Pin number for AF_PCNT1_S0IN location number i */
+#define AF_PCNT1_S1IN_PIN(i)        ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 :  -1)                  /**< Pin number for AF_PCNT1_S1IN location number i */
+#define AF_PCNT2_S0IN_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 :  -1)                                               /**< Pin number for AF_PCNT2_S0IN location number i */
+#define AF_PCNT2_S1IN_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 :  -1)                                               /**< Pin number for AF_PCNT2_S1IN location number i */
+#define AF_I2C0_SDA_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 :  -1)   /**< Pin number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 :  -1)   /**< Pin number for AF_I2C0_SCL location number i */
+#define AF_I2C1_SDA_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 :  -1)                                                /**< Pin number for AF_I2C1_SDA location number i */
+#define AF_I2C1_SCL_PIN(i)          ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                 /**< Pin number for AF_I2C1_SCL location number i */
+#define AF_ACMP0_OUT_PIN(i)         ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 :  -1)   /**< Pin number for AF_ACMP0_OUT location number i */
+#define AF_ACMP1_OUT_PIN(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 :  -1)  /**< Pin number for AF_ACMP1_OUT location number i */
+#define AF_ACMP2_OUT_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                                /**< Pin number for AF_ACMP2_OUT location number i */
+#define AF_USB_VBUSEN_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 :  -1)                                                                                /**< Pin number for AF_USB_VBUSEN location number i */
+#define AF_DBG_TDI_PIN(i)           ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_DBG_TDI location number i */
+#define AF_DBG_TDO_PIN(i)           ((i) == 0 ? 2 :  -1)                                                                                                              /**< Pin number for AF_DBG_TDO location number i */
+#define AF_DBG_SWV_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_DBG_SWV location number i */
+#define AF_DBG_SWDIOTMS_PIN(i)      ((i) == 0 ? 1 :  -1)                                                                                                              /**< Pin number for AF_DBG_SWDIOTMS location number i */
+#define AF_DBG_SWCLKTCK_PIN(i)      ((i) == 0 ? 0 :  -1)                                                                                                              /**< Pin number for AF_DBG_SWCLKTCK location number i */
+#define AF_ETM_TCLK_PIN(i)          ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 :  -1)                                                 /**< Pin number for AF_ETM_TCLK location number i */
+#define AF_ETM_TD0_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 :  -1)                                                 /**< Pin number for AF_ETM_TD0 location number i */
+#define AF_ETM_TD1_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 :  -1)                                                /**< Pin number for AF_ETM_TD1 location number i */
+#define AF_ETM_TD2_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 :  -1)                                                /**< Pin number for AF_ETM_TD2 location number i */
+#define AF_ETM_TD3_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 :  -1)                                                 /**< Pin number for AF_ETM_TD3 location number i */
+
+/** @} */
+/** @} End of group EFM32GG12B_AF_Pins */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_af_ports.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_af_ports.h
@ -0,0 +1,325 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_AF_PORTS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_Alternate_Function Alternate Function
+ * @{
+ * @defgroup EFM32GG12B_AF_Ports Alternate Function Ports
+ * @{
+ ******************************************************************************/
+
+#define AF_CMU_CLK0_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 0 :  -1)                                /**< Port number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 :  -1)                                /**< Port number for AF_CMU_CLK1 location number i */
+#define AF_CMU_CLK2_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 3 :  -1)                                /**< Port number for AF_CMU_CLK2 location number i */
+#define AF_CMU_CLKI0_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_CMU_CLKI0 location number i */
+#define AF_CMU_DIGEXTCLK_PORT(i)     ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_DIGEXTCLK location number i */
+#define AF_CMU_IOPOVR_PORT(i)        ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_IOPOVR location number i */
+#define AF_CMU_IONOVR_PORT(i)        ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_IONOVR location number i */
+#define AF_LESENSE_CH0_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH0 location number i */
+#define AF_LESENSE_CH1_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH1 location number i */
+#define AF_LESENSE_CH2_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH2 location number i */
+#define AF_LESENSE_CH3_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH3 location number i */
+#define AF_LESENSE_CH4_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH4 location number i */
+#define AF_LESENSE_CH5_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH5 location number i */
+#define AF_LESENSE_CH6_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH6 location number i */
+#define AF_LESENSE_CH7_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH7 location number i */
+#define AF_LESENSE_CH8_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH8 location number i */
+#define AF_LESENSE_CH9_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH9 location number i */
+#define AF_LESENSE_CH10_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH10 location number i */
+#define AF_LESENSE_CH11_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH11 location number i */
+#define AF_LESENSE_CH12_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH12 location number i */
+#define AF_LESENSE_CH13_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH13 location number i */
+#define AF_LESENSE_CH14_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH14 location number i */
+#define AF_LESENSE_CH15_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH15 location number i */
+#define AF_LESENSE_ALTEX0_PORT(i)    ((i) == 0 ? 3 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX0 location number i */
+#define AF_LESENSE_ALTEX1_PORT(i)    ((i) == 0 ? 3 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX1 location number i */
+#define AF_LESENSE_ALTEX2_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX2 location number i */
+#define AF_LESENSE_ALTEX3_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX3 location number i */
+#define AF_LESENSE_ALTEX4_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX4 location number i */
+#define AF_LESENSE_ALTEX5_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX5 location number i */
+#define AF_LESENSE_ALTEX6_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX6 location number i */
+#define AF_LESENSE_ALTEX7_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX7 location number i */
+#define AF_EBI_AD00_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD00 location number i */
+#define AF_EBI_AD01_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD01 location number i */
+#define AF_EBI_AD02_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD02 location number i */
+#define AF_EBI_AD03_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD03 location number i */
+#define AF_EBI_AD04_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD04 location number i */
+#define AF_EBI_AD05_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD05 location number i */
+#define AF_EBI_AD06_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD06 location number i */
+#define AF_EBI_AD07_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD07 location number i */
+#define AF_EBI_AD08_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD08 location number i */
+#define AF_EBI_AD09_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD09 location number i */
+#define AF_EBI_AD10_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD10 location number i */
+#define AF_EBI_AD11_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD11 location number i */
+#define AF_EBI_AD12_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD12 location number i */
+#define AF_EBI_AD13_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD13 location number i */
+#define AF_EBI_AD14_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD14 location number i */
+#define AF_EBI_AD15_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD15 location number i */
+#define AF_EBI_CS0_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS0 location number i */
+#define AF_EBI_CS1_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS1 location number i */
+#define AF_EBI_CS2_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS2 location number i */
+#define AF_EBI_CS3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS3 location number i */
+#define AF_EBI_ARDY_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_ARDY location number i */
+#define AF_EBI_ALE_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_EBI_ALE location number i */
+#define AF_EBI_WEn_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_WEn location number i */
+#define AF_EBI_REn_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_REn location number i */
+#define AF_EBI_BL0_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_BL0 location number i */
+#define AF_EBI_BL1_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_BL1 location number i */
+#define AF_EBI_NANDWEn_PORT(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_NANDWEn location number i */
+#define AF_EBI_NANDREn_PORT(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_NANDREn location number i */
+#define AF_EBI_A00_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A00 location number i */
+#define AF_EBI_A01_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A01 location number i */
+#define AF_EBI_A02_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A02 location number i */
+#define AF_EBI_A03_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A03 location number i */
+#define AF_EBI_A04_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A04 location number i */
+#define AF_EBI_A05_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A05 location number i */
+#define AF_EBI_A06_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A06 location number i */
+#define AF_EBI_A07_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A07 location number i */
+#define AF_EBI_A08_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A08 location number i */
+#define AF_EBI_A09_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A09 location number i */
+#define AF_EBI_A10_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A10 location number i */
+#define AF_EBI_A11_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A11 location number i */
+#define AF_EBI_A12_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A12 location number i */
+#define AF_EBI_A13_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A13 location number i */
+#define AF_EBI_A14_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A14 location number i */
+#define AF_EBI_A15_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A15 location number i */
+#define AF_EBI_A16_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A16 location number i */
+#define AF_EBI_A17_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A17 location number i */
+#define AF_EBI_A18_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A18 location number i */
+#define AF_EBI_A19_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A19 location number i */
+#define AF_EBI_A20_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A20 location number i */
+#define AF_EBI_A21_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A21 location number i */
+#define AF_EBI_A22_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A22 location number i */
+#define AF_EBI_A23_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A23 location number i */
+#define AF_EBI_A24_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A24 location number i */
+#define AF_EBI_A25_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A25 location number i */
+#define AF_EBI_A26_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A26 location number i */
+#define AF_EBI_A27_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A27 location number i */
+#define AF_EBI_CSTFT_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_CSTFT location number i */
+#define AF_EBI_DCLK_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_DCLK location number i */
+#define AF_EBI_DTEN_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_DTEN location number i */
+#define AF_EBI_VSNC_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_VSNC location number i */
+#define AF_EBI_HSNC_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_HSNC location number i */
+#define AF_SDIO_CLK_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 4 :  -1)                                                                                             /**< Port number for AF_SDIO_CLK location number i */
+#define AF_SDIO_CMD_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 4 :  -1)                                                                                             /**< Port number for AF_SDIO_CMD location number i */
+#define AF_SDIO_DAT0_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT0 location number i */
+#define AF_SDIO_DAT1_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT1 location number i */
+#define AF_SDIO_DAT2_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT2 location number i */
+#define AF_SDIO_DAT3_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT3 location number i */
+#define AF_SDIO_DAT4_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT4 location number i */
+#define AF_SDIO_DAT5_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT5 location number i */
+#define AF_SDIO_DAT6_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT6 location number i */
+#define AF_SDIO_DAT7_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT7 location number i */
+#define AF_SDIO_CD_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 1 :  -1)                                                               /**< Port number for AF_SDIO_CD location number i */
+#define AF_SDIO_WP_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 1 :  -1)                                                               /**< Port number for AF_SDIO_WP location number i */
+#define AF_PDM_CLK_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_CLK location number i */
+#define AF_PDM_DAT0_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT0 location number i */
+#define AF_PDM_DAT1_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT1 location number i */
+#define AF_PDM_DAT2_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT2 location number i */
+#define AF_PDM_DAT3_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT3 location number i */
+#define AF_PRS_CH0_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 :  -1)                                                               /**< Port number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 :  -1)                                                               /**< Port number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 :  -1)                                                               /**< Port number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 :  -1)                                                               /**< Port number for AF_PRS_CH3 location number i */
+#define AF_PRS_CH4_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 :  -1)                                                                              /**< Port number for AF_PRS_CH4 location number i */
+#define AF_PRS_CH5_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH5 location number i */
+#define AF_PRS_CH6_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH6 location number i */
+#define AF_PRS_CH7_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH7 location number i */
+#define AF_PRS_CH8_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH8 location number i */
+#define AF_PRS_CH9_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_PRS_CH9 location number i */
+#define AF_PRS_CH10_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH10 location number i */
+#define AF_PRS_CH11_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH11 location number i */
+#define AF_PRS_CH12_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH12 location number i */
+#define AF_PRS_CH13_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH13 location number i */
+#define AF_PRS_CH14_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH14 location number i */
+#define AF_PRS_CH15_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 :  -1)                                                                              /**< Port number for AF_PRS_CH15 location number i */
+#define AF_CAN0_RX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? -1 : (i) == 5 ? 3 : (i) == 6 ? 4 :  -1)                 /**< Port number for AF_CAN0_RX location number i */
+#define AF_CAN0_TX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? -1 : (i) == 5 ? 3 : (i) == 6 ? 4 :  -1)                 /**< Port number for AF_CAN0_TX location number i */
+#define AF_CAN1_RX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_CAN1_RX location number i */
+#define AF_CAN1_TX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_CAN1_TX location number i */
+#define AF_TIMER0_CC0_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER0_CC3 location number i */
+#define AF_TIMER0_CDTI0_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER0_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER0_CDTI3 location number i */
+#define AF_TIMER1_CC0_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CC3_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC3 location number i */
+#define AF_TIMER1_CDTI0_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER1_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI3 location number i */
+#define AF_TIMER2_CC0_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC0 location number i */
+#define AF_TIMER2_CC1_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC1 location number i */
+#define AF_TIMER2_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC2 location number i */
+#define AF_TIMER2_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER2_CC3 location number i */
+#define AF_TIMER2_CDTI0_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI0 location number i */
+#define AF_TIMER2_CDTI1_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI1 location number i */
+#define AF_TIMER2_CDTI2_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI2 location number i */
+#define AF_TIMER2_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER2_CDTI3 location number i */
+#define AF_TIMER3_CC0_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 :  -1)   /**< Port number for AF_TIMER3_CC0 location number i */
+#define AF_TIMER3_CC1_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_TIMER3_CC1 location number i */
+#define AF_TIMER3_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_TIMER3_CC2 location number i */
+#define AF_TIMER3_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER3_CC3 location number i */
+#define AF_TIMER3_CDTI0_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI0 location number i */
+#define AF_TIMER3_CDTI1_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI1 location number i */
+#define AF_TIMER3_CDTI2_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI2 location number i */
+#define AF_TIMER3_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI3 location number i */
+#define AF_WTIMER0_CC0_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC0 location number i */
+#define AF_WTIMER0_CC1_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC1 location number i */
+#define AF_WTIMER0_CC2_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC2 location number i */
+#define AF_WTIMER0_CC3_PORT(i)       (-1)                                                                                                                            /**< Port number for AF_WTIMER0_CC3 location number i */
+#define AF_WTIMER0_CDTI0_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                               /**< Port number for AF_WTIMER0_CDTI0 location number i */
+#define AF_WTIMER0_CDTI1_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                              /**< Port number for AF_WTIMER0_CDTI1 location number i */
+#define AF_WTIMER0_CDTI2_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                              /**< Port number for AF_WTIMER0_CDTI2 location number i */
+#define AF_WTIMER0_CDTI3_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER0_CDTI3 location number i */
+#define AF_WTIMER1_CC0_PORT(i)       ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 :  -1)                                 /**< Port number for AF_WTIMER1_CC0 location number i */
+#define AF_WTIMER1_CC1_PORT(i)       ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC1 location number i */
+#define AF_WTIMER1_CC2_PORT(i)       ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC2 location number i */
+#define AF_WTIMER1_CC3_PORT(i)       ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC3 location number i */
+#define AF_WTIMER1_CDTI0_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI0 location number i */
+#define AF_WTIMER1_CDTI1_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI1 location number i */
+#define AF_WTIMER1_CDTI2_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI2 location number i */
+#define AF_WTIMER1_CDTI3_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI3 location number i */
+#define AF_USART0_TX_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_USART0_CS location number i */
+#define AF_USART0_CTS_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART0_CTS location number i */
+#define AF_USART0_RTS_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART0_RTS location number i */
+#define AF_USART1_TX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 :  -1)                  /**< Port number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 :  -1)                  /**< Port number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 :  -1)                  /**< Port number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_USART1_CS location number i */
+#define AF_USART1_CTS_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART1_CTS location number i */
+#define AF_USART1_RTS_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART1_RTS location number i */
+#define AF_USART2_TX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_TX location number i */
+#define AF_USART2_RX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_RX location number i */
+#define AF_USART2_CLK_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_CLK location number i */
+#define AF_USART2_CS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_CS location number i */
+#define AF_USART2_CTS_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART2_CTS location number i */
+#define AF_USART2_RTS_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART2_RTS location number i */
+#define AF_USART3_TX_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_USART3_TX location number i */
+#define AF_USART3_RX_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_USART3_RX location number i */
+#define AF_USART3_CLK_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_USART3_CLK location number i */
+#define AF_USART3_CS_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 :  -1)                                                               /**< Port number for AF_USART3_CS location number i */
+#define AF_USART3_CTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_USART3_CTS location number i */
+#define AF_USART3_RTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 :  -1)                                                               /**< Port number for AF_USART3_RTS location number i */
+#define AF_USART4_TX_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_TX location number i */
+#define AF_USART4_RX_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_RX location number i */
+#define AF_USART4_CLK_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CLK location number i */
+#define AF_USART4_CS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CS location number i */
+#define AF_USART4_CTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CTS location number i */
+#define AF_USART4_RTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_RTS location number i */
+#define AF_UART0_TX_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 :  -1)                  /**< Port number for AF_UART0_TX location number i */
+#define AF_UART0_RX_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 :  -1)                  /**< Port number for AF_UART0_RX location number i */
+#define AF_UART0_CLK_PORT(i)         (-1)                                                                                                                            /**< Port number for AF_UART0_CLK location number i */
+#define AF_UART0_CS_PORT(i)          (-1)                                                                                                                            /**< Port number for AF_UART0_CS location number i */
+#define AF_UART0_CTS_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_UART0_CTS location number i */
+#define AF_UART0_RTS_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_UART0_RTS location number i */
+#define AF_UART1_TX_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_UART1_TX location number i */
+#define AF_UART1_RX_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_UART1_RX location number i */
+#define AF_UART1_CLK_PORT(i)         (-1)                                                                                                                            /**< Port number for AF_UART1_CLK location number i */
+#define AF_UART1_CS_PORT(i)          (-1)                                                                                                                            /**< Port number for AF_UART1_CS location number i */
+#define AF_UART1_CTS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_UART1_CTS location number i */
+#define AF_UART1_RTS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_UART1_RTS location number i */
+#define AF_QSPI0_SCLK_PORT(i)        ((i) == 0 ? 5 : (i) == 1 ? 4 :  -1)                                                                                             /**< Port number for AF_QSPI0_SCLK location number i */
+#define AF_QSPI0_DQ0_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ0 location number i */
+#define AF_QSPI0_DQ1_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ1 location number i */
+#define AF_QSPI0_DQ2_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ2 location number i */
+#define AF_QSPI0_DQ3_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ3 location number i */
+#define AF_QSPI0_DQ4_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ4 location number i */
+#define AF_QSPI0_DQ5_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ5 location number i */
+#define AF_QSPI0_DQ6_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ6 location number i */
+#define AF_QSPI0_DQ7_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ7 location number i */
+#define AF_QSPI0_CS0_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_CS0 location number i */
+#define AF_QSPI0_CS1_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_CS1 location number i */
+#define AF_QSPI0_DQS_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQS location number i */
+#define AF_QSPI0_RST0_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_QSPI0_RST0 location number i */
+#define AF_QSPI0_RST1_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_QSPI0_RST1 location number i */
+#define AF_LEUART0_TX_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_LEUART0_RX location number i */
+#define AF_LEUART1_TX_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_LEUART1_TX location number i */
+#define AF_LEUART1_RX_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_LEUART1_RX location number i */
+#define AF_LETIMER0_OUT0_PORT(i)     ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_LETIMER0_OUT0 location number i */
+#define AF_LETIMER0_OUT1_PORT(i)     ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_LETIMER0_OUT1 location number i */
+#define AF_LETIMER1_OUT0_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_LETIMER1_OUT0 location number i */
+#define AF_LETIMER1_OUT1_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_LETIMER1_OUT1 location number i */
+#define AF_PCNT0_S0IN_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_PCNT0_S1IN location number i */
+#define AF_PCNT1_S0IN_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_PCNT1_S0IN location number i */
+#define AF_PCNT1_S1IN_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_PCNT1_S1IN location number i */
+#define AF_PCNT2_S0IN_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_PCNT2_S0IN location number i */
+#define AF_PCNT2_S1IN_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_PCNT2_S1IN location number i */
+#define AF_I2C0_SDA_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 :  -1)   /**< Port number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 :  -1)   /**< Port number for AF_I2C0_SCL location number i */
+#define AF_I2C1_SDA_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_I2C1_SDA location number i */
+#define AF_I2C1_SCL_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 :  -1)                                                /**< Port number for AF_I2C1_SCL location number i */
+#define AF_ACMP0_OUT_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_ACMP0_OUT location number i */
+#define AF_ACMP1_OUT_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_ACMP1_OUT location number i */
+#define AF_ACMP2_OUT_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_ACMP2_OUT location number i */
+#define AF_USB_VBUSEN_PORT(i)        ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_USB_VBUSEN location number i */
+#define AF_DBG_TDI_PORT(i)           ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_TDI location number i */
+#define AF_DBG_TDO_PORT(i)           ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_TDO location number i */
+#define AF_DBG_SWV_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 :  -1)                                                               /**< Port number for AF_DBG_SWV location number i */
+#define AF_DBG_SWDIOTMS_PORT(i)      ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_SWDIOTMS location number i */
+#define AF_DBG_SWCLKTCK_PORT(i)      ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_SWCLKTCK location number i */
+#define AF_ETM_TCLK_PORT(i)          ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TCLK location number i */
+#define AF_ETM_TD0_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD0 location number i */
+#define AF_ETM_TD1_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD1 location number i */
+#define AF_ETM_TD2_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD2 location number i */
+#define AF_ETM_TD3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD3 location number i */
+
+/** @} */
+/** @} End of group EFM32GG12B_AF_Ports */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_can.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_can.h
@ -0,0 +1,648 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_CAN register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_CAN CAN
+ * @{
+ * @brief EFM32GG12B_CAN Register Declaration
+ ******************************************************************************/
+/** CAN Register Declaration */
+typedef struct {
+  __IOM uint32_t  CTRL;          /**< Control Register  */
+  __IOM uint32_t  STATUS;        /**< Status Register  */
+  __IM uint32_t   ERRCNT;        /**< Error Count Register  */
+  __IOM uint32_t  BITTIMING;     /**< Bit Timing Register  */
+  __IM uint32_t   INTID;         /**< Interrupt Identification Register  */
+  __IOM uint32_t  TEST;          /**< Test Register  */
+  __IOM uint32_t  BRPE;          /**< BRP Extension Register  */
+  __IM uint32_t   TRANSREQ;      /**< Transmission Request Register  */
+  __IM uint32_t   MESSAGEDATA;   /**< New Data Register  */
+
+  uint32_t        RESERVED0[1U]; /**< Reserved for future use **/
+  __IM uint32_t   MESSAGESTATE;  /**< Message Valid Register  */
+  __IOM uint32_t  CONFIG;        /**< Configuration Register  */
+  __IM uint32_t   IF0IF;         /**< Message Object Interrupt Flag Register  */
+  __IOM uint32_t  IF0IFS;        /**< Message Object Interrupt Flag Set Register  */
+  __IOM uint32_t  IF0IFC;        /**< Message Object Interrupt Flag Clear Register  */
+  __IOM uint32_t  IF0IEN;        /**< Message Object Interrupt Enable Register  */
+  __IM uint32_t   IF1IF;         /**< Status Interrupt Flag Register  */
+  __IOM uint32_t  IF1IFS;        /**< Message Object Interrupt Flag Set Register  */
+  __IOM uint32_t  IF1IFC;        /**< Message Object Interrupt Flag Clear Register  */
+  __IOM uint32_t  IF1IEN;        /**< Status Interrupt Enable Register  */
+  __IOM uint32_t  ROUTE;         /**< I/O Routing Register  */
+
+  uint32_t        RESERVED1[3U]; /**< Reserved registers */
+  CAN_MIR_TypeDef MIR[2U];       /**< Interface Registers */
+} CAN_TypeDef;                   /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_CAN
+ * @{
+ * @defgroup EFM32GG12B_CAN_BitFields  CAN Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CAN CTRL */
+#define _CAN_CTRL_RESETVALUE                     0x00000001UL                  /**< Default value for CAN_CTRL */
+#define _CAN_CTRL_MASK                           0x000000EFUL                  /**< Mask for CAN_CTRL */
+#define CAN_CTRL_INIT                            (0x1UL << 0)                  /**< Initialize */
+#define _CAN_CTRL_INIT_SHIFT                     0                             /**< Shift value for CAN_INIT */
+#define _CAN_CTRL_INIT_MASK                      0x1UL                         /**< Bit mask for CAN_INIT */
+#define _CAN_CTRL_INIT_DEFAULT                   0x00000001UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_INIT_DEFAULT                    (_CAN_CTRL_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_IE                              (0x1UL << 1)                  /**< Module Interrupt Enable */
+#define _CAN_CTRL_IE_SHIFT                       1                             /**< Shift value for CAN_IE */
+#define _CAN_CTRL_IE_MASK                        0x2UL                         /**< Bit mask for CAN_IE */
+#define _CAN_CTRL_IE_DEFAULT                     0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_IE_DEFAULT                      (_CAN_CTRL_IE_DEFAULT << 1)   /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_SIE                             (0x1UL << 2)                  /**< Status Change Interrupt Enable */
+#define _CAN_CTRL_SIE_SHIFT                      2                             /**< Shift value for CAN_SIE */
+#define _CAN_CTRL_SIE_MASK                       0x4UL                         /**< Bit mask for CAN_SIE */
+#define _CAN_CTRL_SIE_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_SIE_DEFAULT                     (_CAN_CTRL_SIE_DEFAULT << 2)  /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_EIE                             (0x1UL << 3)                  /**< Error Interrupt Enable */
+#define _CAN_CTRL_EIE_SHIFT                      3                             /**< Shift value for CAN_EIE */
+#define _CAN_CTRL_EIE_MASK                       0x8UL                         /**< Bit mask for CAN_EIE */
+#define _CAN_CTRL_EIE_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_EIE_DEFAULT                     (_CAN_CTRL_EIE_DEFAULT << 3)  /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_DAR                             (0x1UL << 5)                  /**< Disable Automatic Retransmission */
+#define _CAN_CTRL_DAR_SHIFT                      5                             /**< Shift value for CAN_DAR */
+#define _CAN_CTRL_DAR_MASK                       0x20UL                        /**< Bit mask for CAN_DAR */
+#define _CAN_CTRL_DAR_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_DAR_DEFAULT                     (_CAN_CTRL_DAR_DEFAULT << 5)  /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_CCE                             (0x1UL << 6)                  /**< Configuration Change Enable */
+#define _CAN_CTRL_CCE_SHIFT                      6                             /**< Shift value for CAN_CCE */
+#define _CAN_CTRL_CCE_MASK                       0x40UL                        /**< Bit mask for CAN_CCE */
+#define _CAN_CTRL_CCE_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_CCE_DEFAULT                     (_CAN_CTRL_CCE_DEFAULT << 6)  /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_TEST                            (0x1UL << 7)                  /**< Test Mode Enable Write */
+#define _CAN_CTRL_TEST_SHIFT                     7                             /**< Shift value for CAN_TEST */
+#define _CAN_CTRL_TEST_MASK                      0x80UL                        /**< Bit mask for CAN_TEST */
+#define _CAN_CTRL_TEST_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_TEST_DEFAULT                    (_CAN_CTRL_TEST_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_CTRL */
+
+/* Bit fields for CAN STATUS */
+#define _CAN_STATUS_RESETVALUE                   0x00000000UL                     /**< Default value for CAN_STATUS */
+#define _CAN_STATUS_MASK                         0x000000FFUL                     /**< Mask for CAN_STATUS */
+#define _CAN_STATUS_LEC_SHIFT                    0                                /**< Shift value for CAN_LEC */
+#define _CAN_STATUS_LEC_MASK                     0x7UL                            /**< Bit mask for CAN_LEC */
+#define _CAN_STATUS_LEC_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define _CAN_STATUS_LEC_NONE                     0x00000000UL                     /**< Mode NONE for CAN_STATUS */
+#define _CAN_STATUS_LEC_STUFF                    0x00000001UL                     /**< Mode STUFF for CAN_STATUS */
+#define _CAN_STATUS_LEC_FORM                     0x00000002UL                     /**< Mode FORM for CAN_STATUS */
+#define _CAN_STATUS_LEC_ACK                      0x00000003UL                     /**< Mode ACK for CAN_STATUS */
+#define _CAN_STATUS_LEC_BIT1                     0x00000004UL                     /**< Mode BIT1 for CAN_STATUS */
+#define _CAN_STATUS_LEC_BIT0                     0x00000005UL                     /**< Mode BIT0 for CAN_STATUS */
+#define _CAN_STATUS_LEC_CRC                      0x00000006UL                     /**< Mode CRC for CAN_STATUS */
+#define _CAN_STATUS_LEC_UNUSED                   0x00000007UL                     /**< Mode UNUSED for CAN_STATUS */
+#define CAN_STATUS_LEC_DEFAULT                   (_CAN_STATUS_LEC_DEFAULT << 0)   /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_LEC_NONE                      (_CAN_STATUS_LEC_NONE << 0)      /**< Shifted mode NONE for CAN_STATUS */
+#define CAN_STATUS_LEC_STUFF                     (_CAN_STATUS_LEC_STUFF << 0)     /**< Shifted mode STUFF for CAN_STATUS */
+#define CAN_STATUS_LEC_FORM                      (_CAN_STATUS_LEC_FORM << 0)      /**< Shifted mode FORM for CAN_STATUS */
+#define CAN_STATUS_LEC_ACK                       (_CAN_STATUS_LEC_ACK << 0)       /**< Shifted mode ACK for CAN_STATUS */
+#define CAN_STATUS_LEC_BIT1                      (_CAN_STATUS_LEC_BIT1 << 0)      /**< Shifted mode BIT1 for CAN_STATUS */
+#define CAN_STATUS_LEC_BIT0                      (_CAN_STATUS_LEC_BIT0 << 0)      /**< Shifted mode BIT0 for CAN_STATUS */
+#define CAN_STATUS_LEC_CRC                       (_CAN_STATUS_LEC_CRC << 0)       /**< Shifted mode CRC for CAN_STATUS */
+#define CAN_STATUS_LEC_UNUSED                    (_CAN_STATUS_LEC_UNUSED << 0)    /**< Shifted mode UNUSED for CAN_STATUS */
+#define CAN_STATUS_TXOK                          (0x1UL << 3)                     /**< Transmitted a Message Successfully */
+#define _CAN_STATUS_TXOK_SHIFT                   3                                /**< Shift value for CAN_TXOK */
+#define _CAN_STATUS_TXOK_MASK                    0x8UL                            /**< Bit mask for CAN_TXOK */
+#define _CAN_STATUS_TXOK_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_TXOK_DEFAULT                  (_CAN_STATUS_TXOK_DEFAULT << 3)  /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_RXOK                          (0x1UL << 4)                     /**< Received a Message Successfully */
+#define _CAN_STATUS_RXOK_SHIFT                   4                                /**< Shift value for CAN_RXOK */
+#define _CAN_STATUS_RXOK_MASK                    0x10UL                           /**< Bit mask for CAN_RXOK */
+#define _CAN_STATUS_RXOK_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_RXOK_DEFAULT                  (_CAN_STATUS_RXOK_DEFAULT << 4)  /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_EPASS                         (0x1UL << 5)                     /**< Error Passive */
+#define _CAN_STATUS_EPASS_SHIFT                  5                                /**< Shift value for CAN_EPASS */
+#define _CAN_STATUS_EPASS_MASK                   0x20UL                           /**< Bit mask for CAN_EPASS */
+#define _CAN_STATUS_EPASS_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_EPASS_DEFAULT                 (_CAN_STATUS_EPASS_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_EWARN                         (0x1UL << 6)                     /**< Warning Status */
+#define _CAN_STATUS_EWARN_SHIFT                  6                                /**< Shift value for CAN_EWARN */
+#define _CAN_STATUS_EWARN_MASK                   0x40UL                           /**< Bit mask for CAN_EWARN */
+#define _CAN_STATUS_EWARN_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_EWARN_DEFAULT                 (_CAN_STATUS_EWARN_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_BOFF                          (0x1UL << 7)                     /**< Bus Off Status */
+#define _CAN_STATUS_BOFF_SHIFT                   7                                /**< Shift value for CAN_BOFF */
+#define _CAN_STATUS_BOFF_MASK                    0x80UL                           /**< Bit mask for CAN_BOFF */
+#define _CAN_STATUS_BOFF_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_BOFF_DEFAULT                  (_CAN_STATUS_BOFF_DEFAULT << 7)  /**< Shifted mode DEFAULT for CAN_STATUS */
+
+/* Bit fields for CAN ERRCNT */
+#define _CAN_ERRCNT_RESETVALUE                   0x00000000UL                        /**< Default value for CAN_ERRCNT */
+#define _CAN_ERRCNT_MASK                         0x0000FFFFUL                        /**< Mask for CAN_ERRCNT */
+#define _CAN_ERRCNT_TEC_SHIFT                    0                                   /**< Shift value for CAN_TEC */
+#define _CAN_ERRCNT_TEC_MASK                     0xFFUL                              /**< Bit mask for CAN_TEC */
+#define _CAN_ERRCNT_TEC_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CAN_ERRCNT */
+#define CAN_ERRCNT_TEC_DEFAULT                   (_CAN_ERRCNT_TEC_DEFAULT << 0)      /**< Shifted mode DEFAULT for CAN_ERRCNT */
+#define _CAN_ERRCNT_REC_SHIFT                    8                                   /**< Shift value for CAN_REC */
+#define _CAN_ERRCNT_REC_MASK                     0x7F00UL                            /**< Bit mask for CAN_REC */
+#define _CAN_ERRCNT_REC_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CAN_ERRCNT */
+#define CAN_ERRCNT_REC_DEFAULT                   (_CAN_ERRCNT_REC_DEFAULT << 8)      /**< Shifted mode DEFAULT for CAN_ERRCNT */
+#define CAN_ERRCNT_RECERRP                       (0x1UL << 15)                       /**< Receive Error Passive */
+#define _CAN_ERRCNT_RECERRP_SHIFT                15                                  /**< Shift value for CAN_RECERRP */
+#define _CAN_ERRCNT_RECERRP_MASK                 0x8000UL                            /**< Bit mask for CAN_RECERRP */
+#define _CAN_ERRCNT_RECERRP_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CAN_ERRCNT */
+#define _CAN_ERRCNT_RECERRP_FALSE                0x00000000UL                        /**< Mode FALSE for CAN_ERRCNT */
+#define _CAN_ERRCNT_RECERRP_TRUE                 0x00000001UL                        /**< Mode TRUE for CAN_ERRCNT */
+#define CAN_ERRCNT_RECERRP_DEFAULT               (_CAN_ERRCNT_RECERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_ERRCNT */
+#define CAN_ERRCNT_RECERRP_FALSE                 (_CAN_ERRCNT_RECERRP_FALSE << 15)   /**< Shifted mode FALSE for CAN_ERRCNT */
+#define CAN_ERRCNT_RECERRP_TRUE                  (_CAN_ERRCNT_RECERRP_TRUE << 15)    /**< Shifted mode TRUE for CAN_ERRCNT */
+
+/* Bit fields for CAN BITTIMING */
+#define _CAN_BITTIMING_RESETVALUE                0x00002301UL                         /**< Default value for CAN_BITTIMING */
+#define _CAN_BITTIMING_MASK                      0x00007FFFUL                         /**< Mask for CAN_BITTIMING */
+#define _CAN_BITTIMING_BRP_SHIFT                 0                                    /**< Shift value for CAN_BRP */
+#define _CAN_BITTIMING_BRP_MASK                  0x3FUL                               /**< Bit mask for CAN_BRP */
+#define _CAN_BITTIMING_BRP_DEFAULT               0x00000001UL                         /**< Mode DEFAULT for CAN_BITTIMING */
+#define CAN_BITTIMING_BRP_DEFAULT                (_CAN_BITTIMING_BRP_DEFAULT << 0)    /**< Shifted mode DEFAULT for CAN_BITTIMING */
+#define _CAN_BITTIMING_SJW_SHIFT                 6                                    /**< Shift value for CAN_SJW */
+#define _CAN_BITTIMING_SJW_MASK                  0xC0UL                               /**< Bit mask for CAN_SJW */
+#define _CAN_BITTIMING_SJW_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CAN_BITTIMING */
+#define CAN_BITTIMING_SJW_DEFAULT                (_CAN_BITTIMING_SJW_DEFAULT << 6)    /**< Shifted mode DEFAULT for CAN_BITTIMING */
+#define _CAN_BITTIMING_TSEG1_SHIFT               8                                    /**< Shift value for CAN_TSEG1 */
+#define _CAN_BITTIMING_TSEG1_MASK                0xF00UL                              /**< Bit mask for CAN_TSEG1 */
+#define _CAN_BITTIMING_TSEG1_DEFAULT             0x00000003UL                         /**< Mode DEFAULT for CAN_BITTIMING */
+#define CAN_BITTIMING_TSEG1_DEFAULT              (_CAN_BITTIMING_TSEG1_DEFAULT << 8)  /**< Shifted mode DEFAULT for CAN_BITTIMING */
+#define _CAN_BITTIMING_TSEG2_SHIFT               12                                   /**< Shift value for CAN_TSEG2 */
+#define _CAN_BITTIMING_TSEG2_MASK                0x7000UL                             /**< Bit mask for CAN_TSEG2 */
+#define _CAN_BITTIMING_TSEG2_DEFAULT             0x00000002UL                         /**< Mode DEFAULT for CAN_BITTIMING */
+#define CAN_BITTIMING_TSEG2_DEFAULT              (_CAN_BITTIMING_TSEG2_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_BITTIMING */
+
+/* Bit fields for CAN INTID */
+#define _CAN_INTID_RESETVALUE                    0x00000000UL                       /**< Default value for CAN_INTID */
+#define _CAN_INTID_MASK                          0x0000803FUL                       /**< Mask for CAN_INTID */
+#define _CAN_INTID_INTID_SHIFT                   0                                  /**< Shift value for CAN_INTID */
+#define _CAN_INTID_INTID_MASK                    0x3FUL                             /**< Bit mask for CAN_INTID */
+#define _CAN_INTID_INTID_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for CAN_INTID */
+#define CAN_INTID_INTID_DEFAULT                  (_CAN_INTID_INTID_DEFAULT << 0)    /**< Shifted mode DEFAULT for CAN_INTID */
+#define CAN_INTID_INTSTAT                        (0x1UL << 15)                      /**< Status Interupt */
+#define _CAN_INTID_INTSTAT_SHIFT                 15                                 /**< Shift value for CAN_INTSTAT */
+#define _CAN_INTID_INTSTAT_MASK                  0x8000UL                           /**< Bit mask for CAN_INTSTAT */
+#define _CAN_INTID_INTSTAT_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for CAN_INTID */
+#define _CAN_INTID_INTSTAT_FALSE                 0x00000000UL                       /**< Mode FALSE for CAN_INTID */
+#define _CAN_INTID_INTSTAT_TRUE                  0x00000001UL                       /**< Mode TRUE for CAN_INTID */
+#define CAN_INTID_INTSTAT_DEFAULT                (_CAN_INTID_INTSTAT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_INTID */
+#define CAN_INTID_INTSTAT_FALSE                  (_CAN_INTID_INTSTAT_FALSE << 15)   /**< Shifted mode FALSE for CAN_INTID */
+#define CAN_INTID_INTSTAT_TRUE                   (_CAN_INTID_INTSTAT_TRUE << 15)    /**< Shifted mode TRUE for CAN_INTID */
+
+/* Bit fields for CAN TEST */
+#define _CAN_TEST_RESETVALUE                     0x00000000UL                    /**< Default value for CAN_TEST */
+#define _CAN_TEST_MASK                           0x000000FCUL                    /**< Mask for CAN_TEST */
+#define CAN_TEST_BASIC                           (0x1UL << 2)                    /**< Basic Mode */
+#define _CAN_TEST_BASIC_SHIFT                    2                               /**< Shift value for CAN_BASIC */
+#define _CAN_TEST_BASIC_MASK                     0x4UL                           /**< Bit mask for CAN_BASIC */
+#define _CAN_TEST_BASIC_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define CAN_TEST_BASIC_DEFAULT                   (_CAN_TEST_BASIC_DEFAULT << 2)  /**< Shifted mode DEFAULT for CAN_TEST */
+#define CAN_TEST_SILENT                          (0x1UL << 3)                    /**< Silent Mode */
+#define _CAN_TEST_SILENT_SHIFT                   3                               /**< Shift value for CAN_SILENT */
+#define _CAN_TEST_SILENT_MASK                    0x8UL                           /**< Bit mask for CAN_SILENT */
+#define _CAN_TEST_SILENT_DEFAULT                 0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define CAN_TEST_SILENT_DEFAULT                  (_CAN_TEST_SILENT_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_TEST */
+#define CAN_TEST_LBACK                           (0x1UL << 4)                    /**< Loopback Mode */
+#define _CAN_TEST_LBACK_SHIFT                    4                               /**< Shift value for CAN_LBACK */
+#define _CAN_TEST_LBACK_MASK                     0x10UL                          /**< Bit mask for CAN_LBACK */
+#define _CAN_TEST_LBACK_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define CAN_TEST_LBACK_DEFAULT                   (_CAN_TEST_LBACK_DEFAULT << 4)  /**< Shifted mode DEFAULT for CAN_TEST */
+#define _CAN_TEST_TX_SHIFT                       5                               /**< Shift value for CAN_TX */
+#define _CAN_TEST_TX_MASK                        0x60UL                          /**< Bit mask for CAN_TX */
+#define _CAN_TEST_TX_DEFAULT                     0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define _CAN_TEST_TX_CORE                        0x00000000UL                    /**< Mode CORE for CAN_TEST */
+#define _CAN_TEST_TX_SAMPT                       0x00000001UL                    /**< Mode SAMPT for CAN_TEST */
+#define _CAN_TEST_TX_LOW                         0x00000002UL                    /**< Mode LOW for CAN_TEST */
+#define _CAN_TEST_TX_HIGH                        0x00000003UL                    /**< Mode HIGH for CAN_TEST */
+#define CAN_TEST_TX_DEFAULT                      (_CAN_TEST_TX_DEFAULT << 5)     /**< Shifted mode DEFAULT for CAN_TEST */
+#define CAN_TEST_TX_CORE                         (_CAN_TEST_TX_CORE << 5)        /**< Shifted mode CORE for CAN_TEST */
+#define CAN_TEST_TX_SAMPT                        (_CAN_TEST_TX_SAMPT << 5)       /**< Shifted mode SAMPT for CAN_TEST */
+#define CAN_TEST_TX_LOW                          (_CAN_TEST_TX_LOW << 5)         /**< Shifted mode LOW for CAN_TEST */
+#define CAN_TEST_TX_HIGH                         (_CAN_TEST_TX_HIGH << 5)        /**< Shifted mode HIGH for CAN_TEST */
+#define CAN_TEST_RX                              (0x1UL << 7)                    /**< Monitors the Actual Value of CAN_RX Pin */
+#define _CAN_TEST_RX_SHIFT                       7                               /**< Shift value for CAN_RX */
+#define _CAN_TEST_RX_MASK                        0x80UL                          /**< Bit mask for CAN_RX */
+#define _CAN_TEST_RX_DEFAULT                     0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define _CAN_TEST_RX_LOW                         0x00000000UL                    /**< Mode LOW for CAN_TEST */
+#define _CAN_TEST_RX_HIGH                        0x00000001UL                    /**< Mode HIGH for CAN_TEST */
+#define CAN_TEST_RX_DEFAULT                      (_CAN_TEST_RX_DEFAULT << 7)     /**< Shifted mode DEFAULT for CAN_TEST */
+#define CAN_TEST_RX_LOW                          (_CAN_TEST_RX_LOW << 7)         /**< Shifted mode LOW for CAN_TEST */
+#define CAN_TEST_RX_HIGH                         (_CAN_TEST_RX_HIGH << 7)        /**< Shifted mode HIGH for CAN_TEST */
+
+/* Bit fields for CAN BRPE */
+#define _CAN_BRPE_RESETVALUE                     0x00000000UL                  /**< Default value for CAN_BRPE */
+#define _CAN_BRPE_MASK                           0x0000000FUL                  /**< Mask for CAN_BRPE */
+#define _CAN_BRPE_BRPE_SHIFT                     0                             /**< Shift value for CAN_BRPE */
+#define _CAN_BRPE_BRPE_MASK                      0xFUL                         /**< Bit mask for CAN_BRPE */
+#define _CAN_BRPE_BRPE_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for CAN_BRPE */
+#define CAN_BRPE_BRPE_DEFAULT                    (_CAN_BRPE_BRPE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BRPE */
+
+/* Bit fields for CAN TRANSREQ */
+#define _CAN_TRANSREQ_RESETVALUE                 0x00000000UL                           /**< Default value for CAN_TRANSREQ */
+#define _CAN_TRANSREQ_MASK                       0xFFFFFFFFUL                           /**< Mask for CAN_TRANSREQ */
+#define _CAN_TRANSREQ_TXRQSTOUT_SHIFT            0                                      /**< Shift value for CAN_TXRQSTOUT */
+#define _CAN_TRANSREQ_TXRQSTOUT_MASK             0xFFFFFFFFUL                           /**< Bit mask for CAN_TXRQSTOUT */
+#define _CAN_TRANSREQ_TXRQSTOUT_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for CAN_TRANSREQ */
+#define _CAN_TRANSREQ_TXRQSTOUT_FALSE            0x00000000UL                           /**< Mode FALSE for CAN_TRANSREQ */
+#define _CAN_TRANSREQ_TXRQSTOUT_TRUE             0x00000001UL                           /**< Mode TRUE for CAN_TRANSREQ */
+#define CAN_TRANSREQ_TXRQSTOUT_DEFAULT           (_CAN_TRANSREQ_TXRQSTOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_TRANSREQ */
+#define CAN_TRANSREQ_TXRQSTOUT_FALSE             (_CAN_TRANSREQ_TXRQSTOUT_FALSE << 0)   /**< Shifted mode FALSE for CAN_TRANSREQ */
+#define CAN_TRANSREQ_TXRQSTOUT_TRUE              (_CAN_TRANSREQ_TXRQSTOUT_TRUE << 0)    /**< Shifted mode TRUE for CAN_TRANSREQ */
+
+/* Bit fields for CAN MESSAGEDATA */
+#define _CAN_MESSAGEDATA_RESETVALUE              0x00000000UL                          /**< Default value for CAN_MESSAGEDATA */
+#define _CAN_MESSAGEDATA_MASK                    0xFFFFFFFFUL                          /**< Mask for CAN_MESSAGEDATA */
+#define _CAN_MESSAGEDATA_VALID_SHIFT             0                                     /**< Shift value for CAN_VALID */
+#define _CAN_MESSAGEDATA_VALID_MASK              0xFFFFFFFFUL                          /**< Bit mask for CAN_VALID */
+#define _CAN_MESSAGEDATA_VALID_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for CAN_MESSAGEDATA */
+#define CAN_MESSAGEDATA_VALID_DEFAULT            (_CAN_MESSAGEDATA_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGEDATA */
+
+/* Bit fields for CAN MESSAGESTATE */
+#define _CAN_MESSAGESTATE_RESETVALUE             0x00000000UL                           /**< Default value for CAN_MESSAGESTATE */
+#define _CAN_MESSAGESTATE_MASK                   0xFFFFFFFFUL                           /**< Mask for CAN_MESSAGESTATE */
+#define _CAN_MESSAGESTATE_VALID_SHIFT            0                                      /**< Shift value for CAN_VALID */
+#define _CAN_MESSAGESTATE_VALID_MASK             0xFFFFFFFFUL                           /**< Bit mask for CAN_VALID */
+#define _CAN_MESSAGESTATE_VALID_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for CAN_MESSAGESTATE */
+#define CAN_MESSAGESTATE_VALID_DEFAULT           (_CAN_MESSAGESTATE_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGESTATE */
+
+/* Bit fields for CAN CONFIG */
+#define _CAN_CONFIG_RESETVALUE                   0x00000000UL                        /**< Default value for CAN_CONFIG */
+#define _CAN_CONFIG_MASK                         0x00008000UL                        /**< Mask for CAN_CONFIG */
+#define CAN_CONFIG_DBGHALT                       (0x1UL << 15)                       /**< Debug Halt */
+#define _CAN_CONFIG_DBGHALT_SHIFT                15                                  /**< Shift value for CAN_DBGHALT */
+#define _CAN_CONFIG_DBGHALT_MASK                 0x8000UL                            /**< Bit mask for CAN_DBGHALT */
+#define _CAN_CONFIG_DBGHALT_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CAN_CONFIG */
+#define _CAN_CONFIG_DBGHALT_NORMAL               0x00000000UL                        /**< Mode NORMAL for CAN_CONFIG */
+#define _CAN_CONFIG_DBGHALT_STALL                0x00000001UL                        /**< Mode STALL for CAN_CONFIG */
+#define CAN_CONFIG_DBGHALT_DEFAULT               (_CAN_CONFIG_DBGHALT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_CONFIG */
+#define CAN_CONFIG_DBGHALT_NORMAL                (_CAN_CONFIG_DBGHALT_NORMAL << 15)  /**< Shifted mode NORMAL for CAN_CONFIG */
+#define CAN_CONFIG_DBGHALT_STALL                 (_CAN_CONFIG_DBGHALT_STALL << 15)   /**< Shifted mode STALL for CAN_CONFIG */
+
+/* Bit fields for CAN IF0IF */
+#define _CAN_IF0IF_RESETVALUE                    0x00000000UL                      /**< Default value for CAN_IF0IF */
+#define _CAN_IF0IF_MASK                          0xFFFFFFFFUL                      /**< Mask for CAN_IF0IF */
+#define _CAN_IF0IF_MESSAGE_SHIFT                 0                                 /**< Shift value for CAN_MESSAGE */
+#define _CAN_IF0IF_MESSAGE_MASK                  0xFFFFFFFFUL                      /**< Bit mask for CAN_MESSAGE */
+#define _CAN_IF0IF_MESSAGE_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for CAN_IF0IF */
+#define CAN_IF0IF_MESSAGE_DEFAULT                (_CAN_IF0IF_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IF */
+
+/* Bit fields for CAN IF0IFS */
+#define _CAN_IF0IFS_RESETVALUE                   0x00000000UL                       /**< Default value for CAN_IF0IFS */
+#define _CAN_IF0IFS_MASK                         0xFFFFFFFFUL                       /**< Mask for CAN_IF0IFS */
+#define _CAN_IF0IFS_MESSAGE_SHIFT                0                                  /**< Shift value for CAN_MESSAGE */
+#define _CAN_IF0IFS_MESSAGE_MASK                 0xFFFFFFFFUL                       /**< Bit mask for CAN_MESSAGE */
+#define _CAN_IF0IFS_MESSAGE_DEFAULT              0x00000000UL                       /**< Mode DEFAULT for CAN_IF0IFS */
+#define CAN_IF0IFS_MESSAGE_DEFAULT               (_CAN_IF0IFS_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFS */
+
+/* Bit fields for CAN IF0IFC */
+#define _CAN_IF0IFC_RESETVALUE                   0x00000000UL                       /**< Default value for CAN_IF0IFC */
+#define _CAN_IF0IFC_MASK                         0xFFFFFFFFUL                       /**< Mask for CAN_IF0IFC */
+#define _CAN_IF0IFC_MESSAGE_SHIFT                0                                  /**< Shift value for CAN_MESSAGE */
+#define _CAN_IF0IFC_MESSAGE_MASK                 0xFFFFFFFFUL                       /**< Bit mask for CAN_MESSAGE */
+#define _CAN_IF0IFC_MESSAGE_DEFAULT              0x00000000UL                       /**< Mode DEFAULT for CAN_IF0IFC */
+#define CAN_IF0IFC_MESSAGE_DEFAULT               (_CAN_IF0IFC_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFC */
+
+/* Bit fields for CAN IF0IEN */
+#define _CAN_IF0IEN_RESETVALUE                   0xFFFFFFFFUL                       /**< Default value for CAN_IF0IEN */
+#define _CAN_IF0IEN_MASK                         0xFFFFFFFFUL                       /**< Mask for CAN_IF0IEN */
+#define _CAN_IF0IEN_MESSAGE_SHIFT                0                                  /**< Shift value for CAN_MESSAGE */
+#define _CAN_IF0IEN_MESSAGE_MASK                 0xFFFFFFFFUL                       /**< Bit mask for CAN_MESSAGE */
+#define _CAN_IF0IEN_MESSAGE_DEFAULT              0xFFFFFFFFUL                       /**< Mode DEFAULT for CAN_IF0IEN */
+#define CAN_IF0IEN_MESSAGE_DEFAULT               (_CAN_IF0IEN_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IEN */
+
+/* Bit fields for CAN IF1IF */
+#define _CAN_IF1IF_RESETVALUE                    0x00000000UL                     /**< Default value for CAN_IF1IF */
+#define _CAN_IF1IF_MASK                          0x00000001UL                     /**< Mask for CAN_IF1IF */
+#define CAN_IF1IF_STATUS                         (0x1UL << 0)                     /**< Status Interrupt Flag */
+#define _CAN_IF1IF_STATUS_SHIFT                  0                                /**< Shift value for CAN_STATUS */
+#define _CAN_IF1IF_STATUS_MASK                   0x1UL                            /**< Bit mask for CAN_STATUS */
+#define _CAN_IF1IF_STATUS_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for CAN_IF1IF */
+#define CAN_IF1IF_STATUS_DEFAULT                 (_CAN_IF1IF_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IF */
+
+/* Bit fields for CAN IF1IFS */
+#define _CAN_IF1IFS_RESETVALUE                   0x00000000UL                      /**< Default value for CAN_IF1IFS */
+#define _CAN_IF1IFS_MASK                         0x00000001UL                      /**< Mask for CAN_IF1IFS */
+#define CAN_IF1IFS_STATUS                        (0x1UL << 0)                      /**< Set STATUS Interrupt Flag */
+#define _CAN_IF1IFS_STATUS_SHIFT                 0                                 /**< Shift value for CAN_STATUS */
+#define _CAN_IF1IFS_STATUS_MASK                  0x1UL                             /**< Bit mask for CAN_STATUS */
+#define _CAN_IF1IFS_STATUS_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for CAN_IF1IFS */
+#define CAN_IF1IFS_STATUS_DEFAULT                (_CAN_IF1IFS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFS */
+
+/* Bit fields for CAN IF1IFC */
+#define _CAN_IF1IFC_RESETVALUE                   0x00000000UL                      /**< Default value for CAN_IF1IFC */
+#define _CAN_IF1IFC_MASK                         0x00000001UL                      /**< Mask for CAN_IF1IFC */
+#define CAN_IF1IFC_STATUS                        (0x1UL << 0)                      /**< Clear STATUS Interrupt Flag */
+#define _CAN_IF1IFC_STATUS_SHIFT                 0                                 /**< Shift value for CAN_STATUS */
+#define _CAN_IF1IFC_STATUS_MASK                  0x1UL                             /**< Bit mask for CAN_STATUS */
+#define _CAN_IF1IFC_STATUS_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for CAN_IF1IFC */
+#define CAN_IF1IFC_STATUS_DEFAULT                (_CAN_IF1IFC_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFC */
+
+/* Bit fields for CAN IF1IEN */
+#define _CAN_IF1IEN_RESETVALUE                   0x00000001UL                      /**< Default value for CAN_IF1IEN */
+#define _CAN_IF1IEN_MASK                         0x00000001UL                      /**< Mask for CAN_IF1IEN */
+#define CAN_IF1IEN_STATUS                        (0x1UL << 0)                      /**< STATUS Interrupt Enable */
+#define _CAN_IF1IEN_STATUS_SHIFT                 0                                 /**< Shift value for CAN_STATUS */
+#define _CAN_IF1IEN_STATUS_MASK                  0x1UL                             /**< Bit mask for CAN_STATUS */
+#define _CAN_IF1IEN_STATUS_DEFAULT               0x00000001UL                      /**< Mode DEFAULT for CAN_IF1IEN */
+#define CAN_IF1IEN_STATUS_DEFAULT                (_CAN_IF1IEN_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IEN */
+
+/* Bit fields for CAN ROUTE */
+#define _CAN_ROUTE_RESETVALUE                    0x00000000UL                    /**< Default value for CAN_ROUTE */
+#define _CAN_ROUTE_MASK                          0x0000071DUL                    /**< Mask for CAN_ROUTE */
+#define CAN_ROUTE_TXPEN                          (0x1UL << 0)                    /**< TX Pin Enable */
+#define _CAN_ROUTE_TXPEN_SHIFT                   0                               /**< Shift value for CAN_TXPEN */
+#define _CAN_ROUTE_TXPEN_MASK                    0x1UL                           /**< Bit mask for CAN_TXPEN */
+#define _CAN_ROUTE_TXPEN_DEFAULT                 0x00000000UL                    /**< Mode DEFAULT for CAN_ROUTE */
+#define CAN_ROUTE_TXPEN_DEFAULT                  (_CAN_ROUTE_TXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_SHIFT                   2                               /**< Shift value for CAN_RXLOC */
+#define _CAN_ROUTE_RXLOC_MASK                    0x1CUL                          /**< Bit mask for CAN_RXLOC */
+#define _CAN_ROUTE_RXLOC_LOC0                    0x00000000UL                    /**< Mode LOC0 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_DEFAULT                 0x00000000UL                    /**< Mode DEFAULT for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC1                    0x00000001UL                    /**< Mode LOC1 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC2                    0x00000002UL                    /**< Mode LOC2 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC3                    0x00000003UL                    /**< Mode LOC3 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC4                    0x00000004UL                    /**< Mode LOC4 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC5                    0x00000005UL                    /**< Mode LOC5 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC6                    0x00000006UL                    /**< Mode LOC6 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC0                     (_CAN_ROUTE_RXLOC_LOC0 << 2)    /**< Shifted mode LOC0 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_DEFAULT                  (_CAN_ROUTE_RXLOC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC1                     (_CAN_ROUTE_RXLOC_LOC1 << 2)    /**< Shifted mode LOC1 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC2                     (_CAN_ROUTE_RXLOC_LOC2 << 2)    /**< Shifted mode LOC2 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC3                     (_CAN_ROUTE_RXLOC_LOC3 << 2)    /**< Shifted mode LOC3 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC4                     (_CAN_ROUTE_RXLOC_LOC4 << 2)    /**< Shifted mode LOC4 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC5                     (_CAN_ROUTE_RXLOC_LOC5 << 2)    /**< Shifted mode LOC5 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC6                     (_CAN_ROUTE_RXLOC_LOC6 << 2)    /**< Shifted mode LOC6 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_SHIFT                   8                               /**< Shift value for CAN_TXLOC */
+#define _CAN_ROUTE_TXLOC_MASK                    0x700UL                         /**< Bit mask for CAN_TXLOC */
+#define _CAN_ROUTE_TXLOC_LOC0                    0x00000000UL                    /**< Mode LOC0 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_DEFAULT                 0x00000000UL                    /**< Mode DEFAULT for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC1                    0x00000001UL                    /**< Mode LOC1 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC2                    0x00000002UL                    /**< Mode LOC2 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC3                    0x00000003UL                    /**< Mode LOC3 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC4                    0x00000004UL                    /**< Mode LOC4 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC5                    0x00000005UL                    /**< Mode LOC5 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC6                    0x00000006UL                    /**< Mode LOC6 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC0                     (_CAN_ROUTE_TXLOC_LOC0 << 8)    /**< Shifted mode LOC0 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_DEFAULT                  (_CAN_ROUTE_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC1                     (_CAN_ROUTE_TXLOC_LOC1 << 8)    /**< Shifted mode LOC1 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC2                     (_CAN_ROUTE_TXLOC_LOC2 << 8)    /**< Shifted mode LOC2 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC3                     (_CAN_ROUTE_TXLOC_LOC3 << 8)    /**< Shifted mode LOC3 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC4                     (_CAN_ROUTE_TXLOC_LOC4 << 8)    /**< Shifted mode LOC4 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC5                     (_CAN_ROUTE_TXLOC_LOC5 << 8)    /**< Shifted mode LOC5 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC6                     (_CAN_ROUTE_TXLOC_LOC6 << 8)    /**< Shifted mode LOC6 for CAN_ROUTE */
+
+/* Bit fields for CAN MIR_CMDMASK */
+#define _CAN_MIR_CMDMASK_RESETVALUE              0x00000000UL                                 /**< Default value for CAN_MIR_CMDMASK */
+#define _CAN_MIR_CMDMASK_MASK                    0x000000FFUL                                 /**< Mask for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_DATAB                    (0x1UL << 0)                                 /**< CC Channel Mode */
+#define _CAN_MIR_CMDMASK_DATAB_SHIFT             0                                            /**< Shift value for CAN_DATAB */
+#define _CAN_MIR_CMDMASK_DATAB_MASK              0x1UL                                        /**< Bit mask for CAN_DATAB */
+#define _CAN_MIR_CMDMASK_DATAB_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_DATAB_DEFAULT            (_CAN_MIR_CMDMASK_DATAB_DEFAULT << 0)        /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_DATAA                    (0x1UL << 1)                                 /**< Access Data Bytes 0-3 */
+#define _CAN_MIR_CMDMASK_DATAA_SHIFT             1                                            /**< Shift value for CAN_DATAA */
+#define _CAN_MIR_CMDMASK_DATAA_MASK              0x2UL                                        /**< Bit mask for CAN_DATAA */
+#define _CAN_MIR_CMDMASK_DATAA_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_DATAA_DEFAULT            (_CAN_MIR_CMDMASK_DATAA_DEFAULT << 1)        /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_TXRQSTNEWDAT             (0x1UL << 2)                                 /**< Transmission Request Bit/ New Data Bit */
+#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_SHIFT      2                                            /**< Shift value for CAN_TXRQSTNEWDAT */
+#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_MASK       0x4UL                                        /**< Bit mask for CAN_TXRQSTNEWDAT */
+#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT    0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT     (_CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_CLRINTPND                (0x1UL << 3)                                 /**< Clear Interrupt Pending Bit */
+#define _CAN_MIR_CMDMASK_CLRINTPND_SHIFT         3                                            /**< Shift value for CAN_CLRINTPND */
+#define _CAN_MIR_CMDMASK_CLRINTPND_MASK          0x8UL                                        /**< Bit mask for CAN_CLRINTPND */
+#define _CAN_MIR_CMDMASK_CLRINTPND_DEFAULT       0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_CLRINTPND_DEFAULT        (_CAN_MIR_CMDMASK_CLRINTPND_DEFAULT << 3)    /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_CONTROL                  (0x1UL << 4)                                 /**< Access Control Bits */
+#define _CAN_MIR_CMDMASK_CONTROL_SHIFT           4                                            /**< Shift value for CAN_CONTROL */
+#define _CAN_MIR_CMDMASK_CONTROL_MASK            0x10UL                                       /**< Bit mask for CAN_CONTROL */
+#define _CAN_MIR_CMDMASK_CONTROL_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_CONTROL_DEFAULT          (_CAN_MIR_CMDMASK_CONTROL_DEFAULT << 4)      /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_ARBACC                   (0x1UL << 5)                                 /**< Access Arbitration Bits */
+#define _CAN_MIR_CMDMASK_ARBACC_SHIFT            5                                            /**< Shift value for CAN_ARBACC */
+#define _CAN_MIR_CMDMASK_ARBACC_MASK             0x20UL                                       /**< Bit mask for CAN_ARBACC */
+#define _CAN_MIR_CMDMASK_ARBACC_DEFAULT          0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_ARBACC_DEFAULT           (_CAN_MIR_CMDMASK_ARBACC_DEFAULT << 5)       /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_MASKACC                  (0x1UL << 6)                                 /**< Access Mask Bits */
+#define _CAN_MIR_CMDMASK_MASKACC_SHIFT           6                                            /**< Shift value for CAN_MASKACC */
+#define _CAN_MIR_CMDMASK_MASKACC_MASK            0x40UL                                       /**< Bit mask for CAN_MASKACC */
+#define _CAN_MIR_CMDMASK_MASKACC_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_MASKACC_DEFAULT          (_CAN_MIR_CMDMASK_MASKACC_DEFAULT << 6)      /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_WRRD                     (0x1UL << 7)                                 /**< Write/Read RAM */
+#define _CAN_MIR_CMDMASK_WRRD_SHIFT              7                                            /**< Shift value for CAN_WRRD */
+#define _CAN_MIR_CMDMASK_WRRD_MASK               0x80UL                                       /**< Bit mask for CAN_WRRD */
+#define _CAN_MIR_CMDMASK_WRRD_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define _CAN_MIR_CMDMASK_WRRD_READ               0x00000000UL                                 /**< Mode READ for CAN_MIR_CMDMASK */
+#define _CAN_MIR_CMDMASK_WRRD_WRITE              0x00000001UL                                 /**< Mode WRITE for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_WRRD_DEFAULT             (_CAN_MIR_CMDMASK_WRRD_DEFAULT << 7)         /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_WRRD_READ                (_CAN_MIR_CMDMASK_WRRD_READ << 7)            /**< Shifted mode READ for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_WRRD_WRITE               (_CAN_MIR_CMDMASK_WRRD_WRITE << 7)           /**< Shifted mode WRITE for CAN_MIR_CMDMASK */
+
+/* Bit fields for CAN MIR_MASK */
+#define _CAN_MIR_MASK_RESETVALUE                 0xDFFFFFFFUL                       /**< Default value for CAN_MIR_MASK */
+#define _CAN_MIR_MASK_MASK                       0xDFFFFFFFUL                       /**< Mask for CAN_MIR_MASK */
+#define _CAN_MIR_MASK_MASK_SHIFT                 0                                  /**< Shift value for CAN_MASK */
+#define _CAN_MIR_MASK_MASK_MASK                  0x1FFFFFFFUL                       /**< Bit mask for CAN_MASK */
+#define _CAN_MIR_MASK_MASK_DEFAULT               0x1FFFFFFFUL                       /**< Mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MASK_DEFAULT                (_CAN_MIR_MASK_MASK_DEFAULT << 0)  /**< Shifted mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MDIR                        (0x1UL << 30)                      /**< Mask Message Direction */
+#define _CAN_MIR_MASK_MDIR_SHIFT                 30                                 /**< Shift value for CAN_MDIR */
+#define _CAN_MIR_MASK_MDIR_MASK                  0x40000000UL                       /**< Bit mask for CAN_MDIR */
+#define _CAN_MIR_MASK_MDIR_DEFAULT               0x00000001UL                       /**< Mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MDIR_DEFAULT                (_CAN_MIR_MASK_MDIR_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MXTD                        (0x1UL << 31)                      /**< Mask Extended Identifier */
+#define _CAN_MIR_MASK_MXTD_SHIFT                 31                                 /**< Shift value for CAN_MXTD */
+#define _CAN_MIR_MASK_MXTD_MASK                  0x80000000UL                       /**< Bit mask for CAN_MXTD */
+#define _CAN_MIR_MASK_MXTD_DEFAULT               0x00000001UL                       /**< Mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MXTD_DEFAULT                (_CAN_MIR_MASK_MXTD_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
+
+/* Bit fields for CAN MIR_ARB */
+#define _CAN_MIR_ARB_RESETVALUE                  0x00000000UL                        /**< Default value for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_MASK                        0xFFFFFFFFUL                        /**< Mask for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_ID_SHIFT                    0                                   /**< Shift value for CAN_ID */
+#define _CAN_MIR_ARB_ID_MASK                     0x1FFFFFFFUL                        /**< Bit mask for CAN_ID */
+#define _CAN_MIR_ARB_ID_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_ID_DEFAULT                   (_CAN_MIR_ARB_ID_DEFAULT << 0)      /**< Shifted mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_DIR                          (0x1UL << 29)                       /**< Message Direction */
+#define _CAN_MIR_ARB_DIR_SHIFT                   29                                  /**< Shift value for CAN_DIR */
+#define _CAN_MIR_ARB_DIR_MASK                    0x20000000UL                        /**< Bit mask for CAN_DIR */
+#define _CAN_MIR_ARB_DIR_DEFAULT                 0x00000000UL                        /**< Mode DEFAULT for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_DIR_RX                      0x00000000UL                        /**< Mode RX for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_DIR_TX                      0x00000001UL                        /**< Mode TX for CAN_MIR_ARB */
+#define CAN_MIR_ARB_DIR_DEFAULT                  (_CAN_MIR_ARB_DIR_DEFAULT << 29)    /**< Shifted mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_DIR_RX                       (_CAN_MIR_ARB_DIR_RX << 29)         /**< Shifted mode RX for CAN_MIR_ARB */
+#define CAN_MIR_ARB_DIR_TX                       (_CAN_MIR_ARB_DIR_TX << 29)         /**< Shifted mode TX for CAN_MIR_ARB */
+#define CAN_MIR_ARB_XTD                          (0x1UL << 30)                       /**< Extended Identifier */
+#define _CAN_MIR_ARB_XTD_SHIFT                   30                                  /**< Shift value for CAN_XTD */
+#define _CAN_MIR_ARB_XTD_MASK                    0x40000000UL                        /**< Bit mask for CAN_XTD */
+#define _CAN_MIR_ARB_XTD_DEFAULT                 0x00000000UL                        /**< Mode DEFAULT for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_XTD_STD                     0x00000000UL                        /**< Mode STD for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_XTD_EXT                     0x00000001UL                        /**< Mode EXT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_XTD_DEFAULT                  (_CAN_MIR_ARB_XTD_DEFAULT << 30)    /**< Shifted mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_XTD_STD                      (_CAN_MIR_ARB_XTD_STD << 30)        /**< Shifted mode STD for CAN_MIR_ARB */
+#define CAN_MIR_ARB_XTD_EXT                      (_CAN_MIR_ARB_XTD_EXT << 30)        /**< Shifted mode EXT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_MSGVAL                       (0x1UL << 31)                       /**< Message Valid */
+#define _CAN_MIR_ARB_MSGVAL_SHIFT                31                                  /**< Shift value for CAN_MSGVAL */
+#define _CAN_MIR_ARB_MSGVAL_MASK                 0x80000000UL                        /**< Bit mask for CAN_MSGVAL */
+#define _CAN_MIR_ARB_MSGVAL_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_MSGVAL_DEFAULT               (_CAN_MIR_ARB_MSGVAL_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
+
+/* Bit fields for CAN MIR_CTRL */
+#define _CAN_MIR_CTRL_RESETVALUE                 0x00000000UL                            /**< Default value for CAN_MIR_CTRL */
+#define _CAN_MIR_CTRL_MASK                       0x0000FF8FUL                            /**< Mask for CAN_MIR_CTRL */
+#define _CAN_MIR_CTRL_DLC_SHIFT                  0                                       /**< Shift value for CAN_DLC */
+#define _CAN_MIR_CTRL_DLC_MASK                   0xFUL                                   /**< Bit mask for CAN_DLC */
+#define _CAN_MIR_CTRL_DLC_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_DLC_DEFAULT                 (_CAN_MIR_CTRL_DLC_DEFAULT << 0)        /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_EOB                         (0x1UL << 7)                            /**< End of Buffer */
+#define _CAN_MIR_CTRL_EOB_SHIFT                  7                                       /**< Shift value for CAN_EOB */
+#define _CAN_MIR_CTRL_EOB_MASK                   0x80UL                                  /**< Bit mask for CAN_EOB */
+#define _CAN_MIR_CTRL_EOB_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_EOB_DEFAULT                 (_CAN_MIR_CTRL_EOB_DEFAULT << 7)        /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_TXRQST                      (0x1UL << 8)                            /**< Transmit Request */
+#define _CAN_MIR_CTRL_TXRQST_SHIFT               8                                       /**< Shift value for CAN_TXRQST */
+#define _CAN_MIR_CTRL_TXRQST_MASK                0x100UL                                 /**< Bit mask for CAN_TXRQST */
+#define _CAN_MIR_CTRL_TXRQST_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_TXRQST_DEFAULT              (_CAN_MIR_CTRL_TXRQST_DEFAULT << 8)     /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_RMTEN                       (0x1UL << 9)                            /**< Remote Enable */
+#define _CAN_MIR_CTRL_RMTEN_SHIFT                9                                       /**< Shift value for CAN_RMTEN */
+#define _CAN_MIR_CTRL_RMTEN_MASK                 0x200UL                                 /**< Bit mask for CAN_RMTEN */
+#define _CAN_MIR_CTRL_RMTEN_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_RMTEN_DEFAULT               (_CAN_MIR_CTRL_RMTEN_DEFAULT << 9)      /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_RXIE                        (0x1UL << 10)                           /**< Receive Interrupt Enable */
+#define _CAN_MIR_CTRL_RXIE_SHIFT                 10                                      /**< Shift value for CAN_RXIE */
+#define _CAN_MIR_CTRL_RXIE_MASK                  0x400UL                                 /**< Bit mask for CAN_RXIE */
+#define _CAN_MIR_CTRL_RXIE_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_RXIE_DEFAULT                (_CAN_MIR_CTRL_RXIE_DEFAULT << 10)      /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_TXIE                        (0x1UL << 11)                           /**< Transmit Interrupt Enable */
+#define _CAN_MIR_CTRL_TXIE_SHIFT                 11                                      /**< Shift value for CAN_TXIE */
+#define _CAN_MIR_CTRL_TXIE_MASK                  0x800UL                                 /**< Bit mask for CAN_TXIE */
+#define _CAN_MIR_CTRL_TXIE_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_TXIE_DEFAULT                (_CAN_MIR_CTRL_TXIE_DEFAULT << 11)      /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_UMASK                       (0x1UL << 12)                           /**< Use Acceptance Mask */
+#define _CAN_MIR_CTRL_UMASK_SHIFT                12                                      /**< Shift value for CAN_UMASK */
+#define _CAN_MIR_CTRL_UMASK_MASK                 0x1000UL                                /**< Bit mask for CAN_UMASK */
+#define _CAN_MIR_CTRL_UMASK_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_UMASK_DEFAULT               (_CAN_MIR_CTRL_UMASK_DEFAULT << 12)     /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_INTPND                      (0x1UL << 13)                           /**< Interrupt Pending */
+#define _CAN_MIR_CTRL_INTPND_SHIFT               13                                      /**< Shift value for CAN_INTPND */
+#define _CAN_MIR_CTRL_INTPND_MASK                0x2000UL                                /**< Bit mask for CAN_INTPND */
+#define _CAN_MIR_CTRL_INTPND_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_INTPND_DEFAULT              (_CAN_MIR_CTRL_INTPND_DEFAULT << 13)    /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_MESSAGEOF                   (0x1UL << 14)                           /**< Message Lost (only Valid for Message Objects With Direction = Receive) */
+#define _CAN_MIR_CTRL_MESSAGEOF_SHIFT            14                                      /**< Shift value for CAN_MESSAGEOF */
+#define _CAN_MIR_CTRL_MESSAGEOF_MASK             0x4000UL                                /**< Bit mask for CAN_MESSAGEOF */
+#define _CAN_MIR_CTRL_MESSAGEOF_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_MESSAGEOF_DEFAULT           (_CAN_MIR_CTRL_MESSAGEOF_DEFAULT << 14) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_DATAVALID                   (0x1UL << 15)                           /**< New Data */
+#define _CAN_MIR_CTRL_DATAVALID_SHIFT            15                                      /**< Shift value for CAN_DATAVALID */
+#define _CAN_MIR_CTRL_DATAVALID_MASK             0x8000UL                                /**< Bit mask for CAN_DATAVALID */
+#define _CAN_MIR_CTRL_DATAVALID_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_DATAVALID_DEFAULT           (_CAN_MIR_CTRL_DATAVALID_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+
+/* Bit fields for CAN MIR_DATAL */
+#define _CAN_MIR_DATAL_RESETVALUE                0x00000000UL                         /**< Default value for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_MASK                      0xFFFFFFFFUL                         /**< Mask for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_DATA0_SHIFT               0                                    /**< Shift value for CAN_DATA0 */
+#define _CAN_MIR_DATAL_DATA0_MASK                0xFFUL                               /**< Bit mask for CAN_DATA0 */
+#define _CAN_MIR_DATAL_DATA0_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAL */
+#define CAN_MIR_DATAL_DATA0_DEFAULT              (_CAN_MIR_DATAL_DATA0_DEFAULT << 0)  /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_DATA1_SHIFT               8                                    /**< Shift value for CAN_DATA1 */
+#define _CAN_MIR_DATAL_DATA1_MASK                0xFF00UL                             /**< Bit mask for CAN_DATA1 */
+#define _CAN_MIR_DATAL_DATA1_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAL */
+#define CAN_MIR_DATAL_DATA1_DEFAULT              (_CAN_MIR_DATAL_DATA1_DEFAULT << 8)  /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_DATA2_SHIFT               16                                   /**< Shift value for CAN_DATA2 */
+#define _CAN_MIR_DATAL_DATA2_MASK                0xFF0000UL                           /**< Bit mask for CAN_DATA2 */
+#define _CAN_MIR_DATAL_DATA2_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAL */
+#define CAN_MIR_DATAL_DATA2_DEFAULT              (_CAN_MIR_DATAL_DATA2_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_DATA3_SHIFT               24                                   /**< Shift value for CAN_DATA3 */
+#define _CAN_MIR_DATAL_DATA3_MASK                0xFF000000UL                         /**< Bit mask for CAN_DATA3 */
+#define _CAN_MIR_DATAL_DATA3_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAL */
+#define CAN_MIR_DATAL_DATA3_DEFAULT              (_CAN_MIR_DATAL_DATA3_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
+
+/* Bit fields for CAN MIR_DATAH */
+#define _CAN_MIR_DATAH_RESETVALUE                0x00000000UL                         /**< Default value for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_MASK                      0xFFFFFFFFUL                         /**< Mask for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_DATA4_SHIFT               0                                    /**< Shift value for CAN_DATA4 */
+#define _CAN_MIR_DATAH_DATA4_MASK                0xFFUL                               /**< Bit mask for CAN_DATA4 */
+#define _CAN_MIR_DATAH_DATA4_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAH */
+#define CAN_MIR_DATAH_DATA4_DEFAULT              (_CAN_MIR_DATAH_DATA4_DEFAULT << 0)  /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_DATA5_SHIFT               8                                    /**< Shift value for CAN_DATA5 */
+#define _CAN_MIR_DATAH_DATA5_MASK                0xFF00UL                             /**< Bit mask for CAN_DATA5 */
+#define _CAN_MIR_DATAH_DATA5_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAH */
+#define CAN_MIR_DATAH_DATA5_DEFAULT              (_CAN_MIR_DATAH_DATA5_DEFAULT << 8)  /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_DATA6_SHIFT               16                                   /**< Shift value for CAN_DATA6 */
+#define _CAN_MIR_DATAH_DATA6_MASK                0xFF0000UL                           /**< Bit mask for CAN_DATA6 */
+#define _CAN_MIR_DATAH_DATA6_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAH */
+#define CAN_MIR_DATAH_DATA6_DEFAULT              (_CAN_MIR_DATAH_DATA6_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_DATA7_SHIFT               24                                   /**< Shift value for CAN_DATA7 */
+#define _CAN_MIR_DATAH_DATA7_MASK                0xFF000000UL                         /**< Bit mask for CAN_DATA7 */
+#define _CAN_MIR_DATAH_DATA7_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAH */
+#define CAN_MIR_DATAH_DATA7_DEFAULT              (_CAN_MIR_DATAH_DATA7_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
+
+/* Bit fields for CAN MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_RESETVALUE               0x00000001UL                          /**< Default value for CAN_MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_MASK                     0x0000803FUL                          /**< Mask for CAN_MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_MSGNUM_SHIFT             0                                     /**< Shift value for CAN_MSGNUM */
+#define _CAN_MIR_CMDREQ_MSGNUM_MASK              0x3FUL                                /**< Bit mask for CAN_MSGNUM */
+#define _CAN_MIR_CMDREQ_MSGNUM_DEFAULT           0x00000001UL                          /**< Mode DEFAULT for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_MSGNUM_DEFAULT            (_CAN_MIR_CMDREQ_MSGNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_BUSY                      (0x1UL << 15)                         /**< Busy Flag */
+#define _CAN_MIR_CMDREQ_BUSY_SHIFT               15                                    /**< Shift value for CAN_BUSY */
+#define _CAN_MIR_CMDREQ_BUSY_MASK                0x8000UL                              /**< Bit mask for CAN_BUSY */
+#define _CAN_MIR_CMDREQ_BUSY_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for CAN_MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_BUSY_FALSE               0x00000000UL                          /**< Mode FALSE for CAN_MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_BUSY_TRUE                0x00000001UL                          /**< Mode TRUE for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_BUSY_DEFAULT              (_CAN_MIR_CMDREQ_BUSY_DEFAULT << 15)  /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_BUSY_FALSE                (_CAN_MIR_CMDREQ_BUSY_FALSE << 15)    /**< Shifted mode FALSE for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_BUSY_TRUE                 (_CAN_MIR_CMDREQ_BUSY_TRUE << 15)     /**< Shifted mode TRUE for CAN_MIR_CMDREQ */
+
+/** @} */
+/** @} End of group EFM32GG12B_CAN */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_can_mir.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_can_mir.h
@ -0,0 +1,65 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_CAN_MIR register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief CAN_MIR CAN MIR Register
+ * @ingroup EFM32GG12B_CAN
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CMDMASK;       /**< Interface Command Mask Register  */
+  __IOM uint32_t MASK;          /**< Interface Mask Register  */
+  __IOM uint32_t ARB;           /**< Interface Arbitration Register  */
+  __IOM uint32_t CTRL;          /**< Interface Message Control Register  */
+  __IOM uint32_t DATAL;         /**< Interface Data a Register  */
+  __IOM uint32_t DATAH;         /**< Interface Data B Register  */
+  __IOM uint32_t CMDREQ;        /**< Interface Command Request Register  */
+  uint32_t       RESERVED0[1U]; /**< Reserved future */
+} CAN_MIR_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_cmu.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_cmu.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_cryotimer.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_cryotimer.h
@ -0,0 +1,183 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_CRYOTIMER register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_CRYOTIMER CRYOTIMER
+ * @{
+ * @brief EFM32GG12B_CRYOTIMER Register Declaration
+ ******************************************************************************/
+/** CRYOTIMER Register Declaration */
+typedef struct {
+  __IOM uint32_t CTRL;      /**< Control Register  */
+  __IOM uint32_t PERIODSEL; /**< Interrupt Duration  */
+  __IM uint32_t  CNT;       /**< Counter Value  */
+  __IOM uint32_t EM4WUEN;   /**< Wake Up Enable  */
+  __IM uint32_t  IF;        /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;       /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;       /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;       /**< Interrupt Enable Register  */
+} CRYOTIMER_TypeDef;        /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_CRYOTIMER
+ * @{
+ * @defgroup EFM32GG12B_CRYOTIMER_BitFields  CRYOTIMER Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CRYOTIMER CTRL */
+#define _CRYOTIMER_CTRL_RESETVALUE                0x00000000UL                            /**< Default value for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_MASK                      0x000000EFUL                            /**< Mask for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_EN                         (0x1UL << 0)                            /**< Enable CRYOTIMER */
+#define _CRYOTIMER_CTRL_EN_SHIFT                  0                                       /**< Shift value for CRYOTIMER_EN */
+#define _CRYOTIMER_CTRL_EN_MASK                   0x1UL                                   /**< Bit mask for CRYOTIMER_EN */
+#define _CRYOTIMER_CTRL_EN_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_EN_DEFAULT                 (_CRYOTIMER_CTRL_EN_DEFAULT << 0)       /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_DEBUGRUN                   (0x1UL << 1)                            /**< Debug Mode Run Enable */
+#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT            1                                       /**< Shift value for CRYOTIMER_DEBUGRUN */
+#define _CRYOTIMER_CTRL_DEBUGRUN_MASK             0x2UL                                   /**< Bit mask for CRYOTIMER_DEBUGRUN */
+#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT           (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_SHIFT              2                                       /**< Shift value for CRYOTIMER_OSCSEL */
+#define _CRYOTIMER_CTRL_OSCSEL_MASK               0xCUL                                   /**< Bit mask for CRYOTIMER_OSCSEL */
+#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_DISABLED           0x00000000UL                            /**< Mode DISABLED for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_LFRCO              0x00000001UL                            /**< Mode LFRCO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_LFXO               0x00000002UL                            /**< Mode LFXO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO             0x00000003UL                            /**< Mode ULFRCO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_DEFAULT             (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2)   /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_DISABLED            (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2)  /**< Shifted mode DISABLED for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_LFRCO               (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2)     /**< Shifted mode LFRCO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_LFXO                (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2)      /**< Shifted mode LFXO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_ULFRCO              (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2)    /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_SHIFT               5                                       /**< Shift value for CRYOTIMER_PRESC */
+#define _CRYOTIMER_CTRL_PRESC_MASK                0xE0UL                                  /**< Bit mask for CRYOTIMER_PRESC */
+#define _CRYOTIMER_CTRL_PRESC_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV1                0x00000000UL                            /**< Mode DIV1 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV2                0x00000001UL                            /**< Mode DIV2 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV4                0x00000002UL                            /**< Mode DIV4 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV8                0x00000003UL                            /**< Mode DIV8 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV16               0x00000004UL                            /**< Mode DIV16 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV32               0x00000005UL                            /**< Mode DIV32 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV64               0x00000006UL                            /**< Mode DIV64 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV128              0x00000007UL                            /**< Mode DIV128 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DEFAULT              (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5)    /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV1                 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5)       /**< Shifted mode DIV1 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV2                 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5)       /**< Shifted mode DIV2 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV4                 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5)       /**< Shifted mode DIV4 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV8                 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5)       /**< Shifted mode DIV8 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV16                (_CRYOTIMER_CTRL_PRESC_DIV16 << 5)      /**< Shifted mode DIV16 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV32                (_CRYOTIMER_CTRL_PRESC_DIV32 << 5)      /**< Shifted mode DIV32 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV64                (_CRYOTIMER_CTRL_PRESC_DIV64 << 5)      /**< Shifted mode DIV64 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV128               (_CRYOTIMER_CTRL_PRESC_DIV128 << 5)     /**< Shifted mode DIV128 for CRYOTIMER_CTRL */
+
+/* Bit fields for CRYOTIMER PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_RESETVALUE           0x00000020UL                                  /**< Default value for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_MASK                 0x0000003FUL                                  /**< Mask for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT      0                                             /**< Shift value for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK       0x3FUL                                        /**< Bit mask for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT    0x00000020UL                                  /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */
+#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT     (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */
+
+/* Bit fields for CRYOTIMER CNT */
+#define _CRYOTIMER_CNT_RESETVALUE                 0x00000000UL                      /**< Default value for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_MASK                       0xFFFFFFFFUL                      /**< Mask for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_SHIFT                  0                                 /**< Shift value for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_MASK                   0xFFFFFFFFUL                      /**< Bit mask for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for CRYOTIMER_CNT */
+#define CRYOTIMER_CNT_CNT_DEFAULT                 (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */
+
+/* Bit fields for CRYOTIMER EM4WUEN */
+#define _CRYOTIMER_EM4WUEN_RESETVALUE             0x00000000UL                            /**< Default value for CRYOTIMER_EM4WUEN */
+#define _CRYOTIMER_EM4WUEN_MASK                   0x00000001UL                            /**< Mask for CRYOTIMER_EM4WUEN */
+#define CRYOTIMER_EM4WUEN_EM4WU                   (0x1UL << 0)                            /**< EM4 Wake-up Enable */
+#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT            0                                       /**< Shift value for CRYOTIMER_EM4WU */
+#define _CRYOTIMER_EM4WUEN_EM4WU_MASK             0x1UL                                   /**< Bit mask for CRYOTIMER_EM4WU */
+#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
+#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT           (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */
+
+/* Bit fields for CRYOTIMER IF */
+#define _CRYOTIMER_IF_RESETVALUE                  0x00000000UL                        /**< Default value for CRYOTIMER_IF */
+#define _CRYOTIMER_IF_MASK                        0x00000001UL                        /**< Mask for CRYOTIMER_IF */
+#define CRYOTIMER_IF_PERIOD                       (0x1UL << 0)                        /**< Wakeup Event/Interrupt */
+#define _CRYOTIMER_IF_PERIOD_SHIFT                0                                   /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IF_PERIOD_MASK                 0x1UL                               /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IF_PERIOD_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CRYOTIMER_IF */
+#define CRYOTIMER_IF_PERIOD_DEFAULT               (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */
+
+/* Bit fields for CRYOTIMER IFS */
+#define _CRYOTIMER_IFS_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IFS */
+#define _CRYOTIMER_IFS_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IFS */
+#define CRYOTIMER_IFS_PERIOD                      (0x1UL << 0)                         /**< Set PERIOD Interrupt Flag */
+#define _CRYOTIMER_IFS_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFS_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFS_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IFS */
+#define CRYOTIMER_IFS_PERIOD_DEFAULT              (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */
+
+/* Bit fields for CRYOTIMER IFC */
+#define _CRYOTIMER_IFC_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IFC */
+#define _CRYOTIMER_IFC_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IFC */
+#define CRYOTIMER_IFC_PERIOD                      (0x1UL << 0)                         /**< Clear PERIOD Interrupt Flag */
+#define _CRYOTIMER_IFC_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFC_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFC_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IFC */
+#define CRYOTIMER_IFC_PERIOD_DEFAULT              (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */
+
+/* Bit fields for CRYOTIMER IEN */
+#define _CRYOTIMER_IEN_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IEN */
+#define _CRYOTIMER_IEN_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IEN */
+#define CRYOTIMER_IEN_PERIOD                      (0x1UL << 0)                         /**< PERIOD Interrupt Enable */
+#define _CRYOTIMER_IEN_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IEN_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IEN_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IEN */
+#define CRYOTIMER_IEN_PERIOD_DEFAULT              (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
+
+/** @} */
+/** @} End of group EFM32GG12B_CRYOTIMER */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_crypto.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_crypto.h
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_csen.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_csen.h
@ -0,0 +1,994 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_CSEN register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_CSEN CSEN
+ * @{
+ * @brief EFM32GG12B_CSEN Register Declaration
+ ******************************************************************************/
+/** CSEN Register Declaration */
+typedef struct {
+  __IOM uint32_t CTRL;          /**< Control  */
+  __IOM uint32_t TIMCTRL;       /**< Timing Control  */
+  __IOM uint32_t CMD;           /**< Command  */
+  __IM uint32_t  STATUS;        /**< Status  */
+  __IOM uint32_t PRSSEL;        /**< PRS Select  */
+  __IOM uint32_t DATA;          /**< Output Data  */
+  __IOM uint32_t SCANMASK0;     /**< Scan Channel Mask 0  */
+  __IOM uint32_t SCANINPUTSEL0; /**< Scan Input Selection 0  */
+  __IOM uint32_t SCANMASK1;     /**< Scan Channel Mask 1  */
+  __IOM uint32_t SCANINPUTSEL1; /**< Scan Input Selection 1  */
+  __IM uint32_t  APORTREQ;      /**< APORT Request Status  */
+  __IM uint32_t  APORTCONFLICT; /**< APORT Request Conflict  */
+  __IOM uint32_t CMPTHR;        /**< Comparator Threshold  */
+  __IOM uint32_t EMA;           /**< Exponential Moving Average  */
+  __IOM uint32_t EMACTRL;       /**< Exponential Moving Average Control  */
+  __IOM uint32_t SINGLECTRL;    /**< Single Conversion Control  */
+  __IOM uint32_t DMBASELINE;    /**< Delta Modulation Baseline  */
+  __IOM uint32_t DMCFG;         /**< Delta Modulation Configuration  */
+  __IOM uint32_t ANACTRL;       /**< Analog Control  */
+
+  uint32_t       RESERVED0[2U]; /**< Reserved for future use **/
+  __IM uint32_t  IF;            /**< Interrupt Flag  */
+  __IOM uint32_t IFS;           /**< Interrupt Flag Set  */
+  __IOM uint32_t IFC;           /**< Interrupt Flag Clear  */
+  __IOM uint32_t IEN;           /**< Interrupt Enable  */
+} CSEN_TypeDef;                 /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_CSEN
+ * @{
+ * @defgroup EFM32GG12B_CSEN_BitFields  CSEN Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CSEN CTRL */
+#define _CSEN_CTRL_RESETVALUE                                0x00030000UL                               /**< Default value for CSEN_CTRL */
+#define _CSEN_CTRL_MASK                                      0x1FFFF336UL                               /**< Mask for CSEN_CTRL */
+#define CSEN_CTRL_EN                                         (0x1UL << 1)                               /**< CSEN Enable */
+#define _CSEN_CTRL_EN_SHIFT                                  1                                          /**< Shift value for CSEN_EN */
+#define _CSEN_CTRL_EN_MASK                                   0x2UL                                      /**< Bit mask for CSEN_EN */
+#define _CSEN_CTRL_EN_DEFAULT                                0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_EN_DISABLE                                0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_EN_ENABLE                                 0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_EN_DEFAULT                                 (_CSEN_CTRL_EN_DEFAULT << 1)               /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_EN_DISABLE                                 (_CSEN_CTRL_EN_DISABLE << 1)               /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_EN_ENABLE                                  (_CSEN_CTRL_EN_ENABLE << 1)                /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_CMPPOL                                     (0x1UL << 2)                               /**< CSEN Digital Comparator Polarity Select */
+#define _CSEN_CTRL_CMPPOL_SHIFT                              2                                          /**< Shift value for CSEN_CMPPOL */
+#define _CSEN_CTRL_CMPPOL_MASK                               0x4UL                                      /**< Bit mask for CSEN_CMPPOL */
+#define _CSEN_CTRL_CMPPOL_DEFAULT                            0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CMPPOL_GT                                 0x00000000UL                               /**< Mode GT for CSEN_CTRL */
+#define _CSEN_CTRL_CMPPOL_LTE                                0x00000001UL                               /**< Mode LTE for CSEN_CTRL */
+#define CSEN_CTRL_CMPPOL_DEFAULT                             (_CSEN_CTRL_CMPPOL_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CMPPOL_GT                                  (_CSEN_CTRL_CMPPOL_GT << 2)                /**< Shifted mode GT for CSEN_CTRL */
+#define CSEN_CTRL_CMPPOL_LTE                                 (_CSEN_CTRL_CMPPOL_LTE << 2)               /**< Shifted mode LTE for CSEN_CTRL */
+#define _CSEN_CTRL_CM_SHIFT                                  4                                          /**< Shift value for CSEN_CM */
+#define _CSEN_CTRL_CM_MASK                                   0x30UL                                     /**< Bit mask for CSEN_CM */
+#define _CSEN_CTRL_CM_DEFAULT                                0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CM_SGL                                    0x00000000UL                               /**< Mode SGL for CSEN_CTRL */
+#define _CSEN_CTRL_CM_SCAN                                   0x00000001UL                               /**< Mode SCAN for CSEN_CTRL */
+#define _CSEN_CTRL_CM_CONTSGL                                0x00000002UL                               /**< Mode CONTSGL for CSEN_CTRL */
+#define _CSEN_CTRL_CM_CONTSCAN                               0x00000003UL                               /**< Mode CONTSCAN for CSEN_CTRL */
+#define CSEN_CTRL_CM_DEFAULT                                 (_CSEN_CTRL_CM_DEFAULT << 4)               /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CM_SGL                                     (_CSEN_CTRL_CM_SGL << 4)                   /**< Shifted mode SGL for CSEN_CTRL */
+#define CSEN_CTRL_CM_SCAN                                    (_CSEN_CTRL_CM_SCAN << 4)                  /**< Shifted mode SCAN for CSEN_CTRL */
+#define CSEN_CTRL_CM_CONTSGL                                 (_CSEN_CTRL_CM_CONTSGL << 4)               /**< Shifted mode CONTSGL for CSEN_CTRL */
+#define CSEN_CTRL_CM_CONTSCAN                                (_CSEN_CTRL_CM_CONTSCAN << 4)              /**< Shifted mode CONTSCAN for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_SHIFT                               8                                          /**< Shift value for CSEN_SARCR */
+#define _CSEN_CTRL_SARCR_MASK                                0x300UL                                    /**< Bit mask for CSEN_SARCR */
+#define _CSEN_CTRL_SARCR_DEFAULT                             0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_CLK10                               0x00000000UL                               /**< Mode CLK10 for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_CLK12                               0x00000001UL                               /**< Mode CLK12 for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_CLK14                               0x00000002UL                               /**< Mode CLK14 for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_CLK16                               0x00000003UL                               /**< Mode CLK16 for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_DEFAULT                              (_CSEN_CTRL_SARCR_DEFAULT << 8)            /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_CLK10                                (_CSEN_CTRL_SARCR_CLK10 << 8)              /**< Shifted mode CLK10 for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_CLK12                                (_CSEN_CTRL_SARCR_CLK12 << 8)              /**< Shifted mode CLK12 for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_CLK14                                (_CSEN_CTRL_SARCR_CLK14 << 8)              /**< Shifted mode CLK14 for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_CLK16                                (_CSEN_CTRL_SARCR_CLK16 << 8)              /**< Shifted mode CLK16 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_SHIFT                                 12                                         /**< Shift value for CSEN_ACU */
+#define _CSEN_CTRL_ACU_MASK                                  0x7000UL                                   /**< Bit mask for CSEN_ACU */
+#define _CSEN_CTRL_ACU_DEFAULT                               0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC1                                  0x00000000UL                               /**< Mode ACC1 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC2                                  0x00000001UL                               /**< Mode ACC2 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC4                                  0x00000002UL                               /**< Mode ACC4 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC8                                  0x00000003UL                               /**< Mode ACC8 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC16                                 0x00000004UL                               /**< Mode ACC16 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC32                                 0x00000005UL                               /**< Mode ACC32 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC64                                 0x00000006UL                               /**< Mode ACC64 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_DEFAULT                                (_CSEN_CTRL_ACU_DEFAULT << 12)             /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC1                                   (_CSEN_CTRL_ACU_ACC1 << 12)                /**< Shifted mode ACC1 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC2                                   (_CSEN_CTRL_ACU_ACC2 << 12)                /**< Shifted mode ACC2 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC4                                   (_CSEN_CTRL_ACU_ACC4 << 12)                /**< Shifted mode ACC4 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC8                                   (_CSEN_CTRL_ACU_ACC8 << 12)                /**< Shifted mode ACC8 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC16                                  (_CSEN_CTRL_ACU_ACC16 << 12)               /**< Shifted mode ACC16 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC32                                  (_CSEN_CTRL_ACU_ACC32 << 12)               /**< Shifted mode ACC32 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC64                                  (_CSEN_CTRL_ACU_ACC64 << 12)               /**< Shifted mode ACC64 for CSEN_CTRL */
+#define CSEN_CTRL_MCEN                                       (0x1UL << 15)                              /**< CSEN Multiple Channel Enable */
+#define _CSEN_CTRL_MCEN_SHIFT                                15                                         /**< Shift value for CSEN_MCEN */
+#define _CSEN_CTRL_MCEN_MASK                                 0x8000UL                                   /**< Bit mask for CSEN_MCEN */
+#define _CSEN_CTRL_MCEN_DEFAULT                              0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_MCEN_DISABLE                              0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_MCEN_ENABLE                               0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_MCEN_DEFAULT                               (_CSEN_CTRL_MCEN_DEFAULT << 15)            /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_MCEN_DISABLE                               (_CSEN_CTRL_MCEN_DISABLE << 15)            /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_MCEN_ENABLE                                (_CSEN_CTRL_MCEN_ENABLE << 15)             /**< Shifted mode ENABLE for CSEN_CTRL */
+#define _CSEN_CTRL_STM_SHIFT                                 16                                         /**< Shift value for CSEN_STM */
+#define _CSEN_CTRL_STM_MASK                                  0x30000UL                                  /**< Bit mask for CSEN_STM */
+#define _CSEN_CTRL_STM_PRS                                   0x00000000UL                               /**< Mode PRS for CSEN_CTRL */
+#define _CSEN_CTRL_STM_TIMER                                 0x00000001UL                               /**< Mode TIMER for CSEN_CTRL */
+#define _CSEN_CTRL_STM_START                                 0x00000002UL                               /**< Mode START for CSEN_CTRL */
+#define _CSEN_CTRL_STM_DEFAULT                               0x00000003UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_STM_DEFAULT                               0x00000003UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_STM_PRS                                    (_CSEN_CTRL_STM_PRS << 16)                 /**< Shifted mode PRS for CSEN_CTRL */
+#define CSEN_CTRL_STM_TIMER                                  (_CSEN_CTRL_STM_TIMER << 16)               /**< Shifted mode TIMER for CSEN_CTRL */
+#define CSEN_CTRL_STM_START                                  (_CSEN_CTRL_STM_START << 16)               /**< Shifted mode START for CSEN_CTRL */
+#define CSEN_CTRL_STM_DEFAULT                                (_CSEN_CTRL_STM_DEFAULT << 16)             /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_STM_DEFAULT                                (_CSEN_CTRL_STM_DEFAULT << 16)             /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CMPEN                                      (0x1UL << 18)                              /**< CSEN Digital Comparator Enable */
+#define _CSEN_CTRL_CMPEN_SHIFT                               18                                         /**< Shift value for CSEN_CMPEN */
+#define _CSEN_CTRL_CMPEN_MASK                                0x40000UL                                  /**< Bit mask for CSEN_CMPEN */
+#define _CSEN_CTRL_CMPEN_DEFAULT                             0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CMPEN_DISABLE                             0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_CMPEN_ENABLE                              0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_CMPEN_DEFAULT                              (_CSEN_CTRL_CMPEN_DEFAULT << 18)           /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CMPEN_DISABLE                              (_CSEN_CTRL_CMPEN_DISABLE << 18)           /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_CMPEN_ENABLE                               (_CSEN_CTRL_CMPEN_ENABLE << 18)            /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_DRSF                                       (0x1UL << 19)                              /**< CSEN Disable Right-Shift */
+#define _CSEN_CTRL_DRSF_SHIFT                                19                                         /**< Shift value for CSEN_DRSF */
+#define _CSEN_CTRL_DRSF_MASK                                 0x80000UL                                  /**< Bit mask for CSEN_DRSF */
+#define _CSEN_CTRL_DRSF_DEFAULT                              0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_DRSF_DISABLE                              0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_DRSF_ENABLE                               0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_DRSF_DEFAULT                               (_CSEN_CTRL_DRSF_DEFAULT << 19)            /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_DRSF_DISABLE                               (_CSEN_CTRL_DRSF_DISABLE << 19)            /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_DRSF_ENABLE                                (_CSEN_CTRL_DRSF_ENABLE << 19)             /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_DMAEN                                      (0x1UL << 20)                              /**< CSEN DMA Enable Bit */
+#define _CSEN_CTRL_DMAEN_SHIFT                               20                                         /**< Shift value for CSEN_DMAEN */
+#define _CSEN_CTRL_DMAEN_MASK                                0x100000UL                                 /**< Bit mask for CSEN_DMAEN */
+#define _CSEN_CTRL_DMAEN_DEFAULT                             0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_DMAEN_DISABLE                             0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_DMAEN_ENABLE                              0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_DMAEN_DEFAULT                              (_CSEN_CTRL_DMAEN_DEFAULT << 20)           /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_DMAEN_DISABLE                              (_CSEN_CTRL_DMAEN_DISABLE << 20)           /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_DMAEN_ENABLE                               (_CSEN_CTRL_DMAEN_ENABLE << 20)            /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_CONVSEL                                    (0x1UL << 21)                              /**< CSEN Converter Select */
+#define _CSEN_CTRL_CONVSEL_SHIFT                             21                                         /**< Shift value for CSEN_CONVSEL */
+#define _CSEN_CTRL_CONVSEL_MASK                              0x200000UL                                 /**< Bit mask for CSEN_CONVSEL */
+#define _CSEN_CTRL_CONVSEL_DEFAULT                           0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CONVSEL_SAR                               0x00000000UL                               /**< Mode SAR for CSEN_CTRL */
+#define _CSEN_CTRL_CONVSEL_DM                                0x00000001UL                               /**< Mode DM for CSEN_CTRL */
+#define CSEN_CTRL_CONVSEL_DEFAULT                            (_CSEN_CTRL_CONVSEL_DEFAULT << 21)         /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CONVSEL_SAR                                (_CSEN_CTRL_CONVSEL_SAR << 21)             /**< Shifted mode SAR for CSEN_CTRL */
+#define CSEN_CTRL_CONVSEL_DM                                 (_CSEN_CTRL_CONVSEL_DM << 21)              /**< Shifted mode DM for CSEN_CTRL */
+#define CSEN_CTRL_CHOPEN                                     (0x1UL << 22)                              /**< CSEN Chop Enable */
+#define _CSEN_CTRL_CHOPEN_SHIFT                              22                                         /**< Shift value for CSEN_CHOPEN */
+#define _CSEN_CTRL_CHOPEN_MASK                               0x400000UL                                 /**< Bit mask for CSEN_CHOPEN */
+#define _CSEN_CTRL_CHOPEN_DEFAULT                            0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CHOPEN_DISABLE                            0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_CHOPEN_ENABLE                             0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_CHOPEN_DEFAULT                             (_CSEN_CTRL_CHOPEN_DEFAULT << 22)          /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CHOPEN_DISABLE                             (_CSEN_CTRL_CHOPEN_DISABLE << 22)          /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_CHOPEN_ENABLE                              (_CSEN_CTRL_CHOPEN_ENABLE << 22)           /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_AUTOGND                                    (0x1UL << 23)                              /**< CSEN Automatic Ground Enable */
+#define _CSEN_CTRL_AUTOGND_SHIFT                             23                                         /**< Shift value for CSEN_AUTOGND */
+#define _CSEN_CTRL_AUTOGND_MASK                              0x800000UL                                 /**< Bit mask for CSEN_AUTOGND */
+#define _CSEN_CTRL_AUTOGND_DEFAULT                           0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_AUTOGND_DISABLE                           0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_AUTOGND_ENABLE                            0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_AUTOGND_DEFAULT                            (_CSEN_CTRL_AUTOGND_DEFAULT << 23)         /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_AUTOGND_DISABLE                            (_CSEN_CTRL_AUTOGND_DISABLE << 23)         /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_AUTOGND_ENABLE                             (_CSEN_CTRL_AUTOGND_ENABLE << 23)          /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_MXUC                                       (0x1UL << 24)                              /**< CSEN Mux Disconnect */
+#define _CSEN_CTRL_MXUC_SHIFT                                24                                         /**< Shift value for CSEN_MXUC */
+#define _CSEN_CTRL_MXUC_MASK                                 0x1000000UL                                /**< Bit mask for CSEN_MXUC */
+#define _CSEN_CTRL_MXUC_DEFAULT                              0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_MXUC_CONN                                 0x00000000UL                               /**< Mode CONN for CSEN_CTRL */
+#define _CSEN_CTRL_MXUC_UNC                                  0x00000001UL                               /**< Mode UNC for CSEN_CTRL */
+#define CSEN_CTRL_MXUC_DEFAULT                               (_CSEN_CTRL_MXUC_DEFAULT << 24)            /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_MXUC_CONN                                  (_CSEN_CTRL_MXUC_CONN << 24)               /**< Shifted mode CONN for CSEN_CTRL */
+#define CSEN_CTRL_MXUC_UNC                                   (_CSEN_CTRL_MXUC_UNC << 24)                /**< Shifted mode UNC for CSEN_CTRL */
+#define CSEN_CTRL_EMACMPEN                                   (0x1UL << 25)                              /**< Greater and Less Than Comparison Using the Exponential Moving Average (EMA) is Enabled */
+#define _CSEN_CTRL_EMACMPEN_SHIFT                            25                                         /**< Shift value for CSEN_EMACMPEN */
+#define _CSEN_CTRL_EMACMPEN_MASK                             0x2000000UL                                /**< Bit mask for CSEN_EMACMPEN */
+#define _CSEN_CTRL_EMACMPEN_DEFAULT                          0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_EMACMPEN_DEFAULT                           (_CSEN_CTRL_EMACMPEN_DEFAULT << 25)        /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_WARMUPMODE                                 (0x1UL << 26)                              /**< Select Warmup Mode for CSEN */
+#define _CSEN_CTRL_WARMUPMODE_SHIFT                          26                                         /**< Shift value for CSEN_WARMUPMODE */
+#define _CSEN_CTRL_WARMUPMODE_MASK                           0x4000000UL                                /**< Bit mask for CSEN_WARMUPMODE */
+#define _CSEN_CTRL_WARMUPMODE_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_WARMUPMODE_NORMAL                         0x00000000UL                               /**< Mode NORMAL for CSEN_CTRL */
+#define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM                   0x00000001UL                               /**< Mode KEEPCSENWARM for CSEN_CTRL */
+#define CSEN_CTRL_WARMUPMODE_DEFAULT                         (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26)      /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_WARMUPMODE_NORMAL                          (_CSEN_CTRL_WARMUPMODE_NORMAL << 26)       /**< Shifted mode NORMAL for CSEN_CTRL */
+#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM                    (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */
+#define CSEN_CTRL_LOCALSENS                                  (0x1UL << 27)                              /**< Local Sensing Enable */
+#define _CSEN_CTRL_LOCALSENS_SHIFT                           27                                         /**< Shift value for CSEN_LOCALSENS */
+#define _CSEN_CTRL_LOCALSENS_MASK                            0x8000000UL                                /**< Bit mask for CSEN_LOCALSENS */
+#define _CSEN_CTRL_LOCALSENS_DEFAULT                         0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_LOCALSENS_DEFAULT                          (_CSEN_CTRL_LOCALSENS_DEFAULT << 27)       /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CPACCURACY                                 (0x1UL << 28)                              /**< Charge Pump Accuracy */
+#define _CSEN_CTRL_CPACCURACY_SHIFT                          28                                         /**< Shift value for CSEN_CPACCURACY */
+#define _CSEN_CTRL_CPACCURACY_MASK                           0x10000000UL                               /**< Bit mask for CSEN_CPACCURACY */
+#define _CSEN_CTRL_CPACCURACY_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CPACCURACY_LO                             0x00000000UL                               /**< Mode LO for CSEN_CTRL */
+#define _CSEN_CTRL_CPACCURACY_HI                             0x00000001UL                               /**< Mode HI for CSEN_CTRL */
+#define CSEN_CTRL_CPACCURACY_DEFAULT                         (_CSEN_CTRL_CPACCURACY_DEFAULT << 28)      /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CPACCURACY_LO                              (_CSEN_CTRL_CPACCURACY_LO << 28)           /**< Shifted mode LO for CSEN_CTRL */
+#define CSEN_CTRL_CPACCURACY_HI                              (_CSEN_CTRL_CPACCURACY_HI << 28)           /**< Shifted mode HI for CSEN_CTRL */
+
+/* Bit fields for CSEN TIMCTRL */
+#define _CSEN_TIMCTRL_RESETVALUE                             0x00000000UL                            /**< Default value for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_MASK                                   0x0003FF07UL                            /**< Mask for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_SHIFT                          0                                       /**< Shift value for CSEN_PCPRESC */
+#define _CSEN_TIMCTRL_PCPRESC_MASK                           0x7UL                                   /**< Bit mask for CSEN_PCPRESC */
+#define _CSEN_TIMCTRL_PCPRESC_DEFAULT                        0x00000000UL                            /**< Mode DEFAULT for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV1                           0x00000000UL                            /**< Mode DIV1 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV2                           0x00000001UL                            /**< Mode DIV2 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV4                           0x00000002UL                            /**< Mode DIV4 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV8                           0x00000003UL                            /**< Mode DIV8 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV16                          0x00000004UL                            /**< Mode DIV16 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV32                          0x00000005UL                            /**< Mode DIV32 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV64                          0x00000006UL                            /**< Mode DIV64 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV128                         0x00000007UL                            /**< Mode DIV128 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DEFAULT                         (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0)    /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV1                            (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0)       /**< Shifted mode DIV1 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV2                            (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0)       /**< Shifted mode DIV2 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV4                            (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0)       /**< Shifted mode DIV4 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV8                            (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0)       /**< Shifted mode DIV8 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV16                           (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0)      /**< Shifted mode DIV16 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV32                           (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0)      /**< Shifted mode DIV32 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV64                           (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0)      /**< Shifted mode DIV64 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV128                          (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0)     /**< Shifted mode DIV128 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCTOP_SHIFT                            8                                       /**< Shift value for CSEN_PCTOP */
+#define _CSEN_TIMCTRL_PCTOP_MASK                             0xFF00UL                                /**< Bit mask for CSEN_PCTOP */
+#define _CSEN_TIMCTRL_PCTOP_DEFAULT                          0x00000000UL                            /**< Mode DEFAULT for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCTOP_DEFAULT                           (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8)      /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_WARMUPCNT_SHIFT                        16                                      /**< Shift value for CSEN_WARMUPCNT */
+#define _CSEN_TIMCTRL_WARMUPCNT_MASK                         0x30000UL                               /**< Bit mask for CSEN_WARMUPCNT */
+#define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_WARMUPCNT_DEFAULT                       (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
+
+/* Bit fields for CSEN CMD */
+#define _CSEN_CMD_RESETVALUE                                 0x00000000UL                   /**< Default value for CSEN_CMD */
+#define _CSEN_CMD_MASK                                       0x00000001UL                   /**< Mask for CSEN_CMD */
+#define CSEN_CMD_START                                       (0x1UL << 0)                   /**< Start Software-Triggered Conversions */
+#define _CSEN_CMD_START_SHIFT                                0                              /**< Shift value for CSEN_START */
+#define _CSEN_CMD_START_MASK                                 0x1UL                          /**< Bit mask for CSEN_START */
+#define _CSEN_CMD_START_DEFAULT                              0x00000000UL                   /**< Mode DEFAULT for CSEN_CMD */
+#define CSEN_CMD_START_DEFAULT                               (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */
+
+/* Bit fields for CSEN STATUS */
+#define _CSEN_STATUS_RESETVALUE                              0x00000000UL                         /**< Default value for CSEN_STATUS */
+#define _CSEN_STATUS_MASK                                    0x00000001UL                         /**< Mask for CSEN_STATUS */
+#define CSEN_STATUS_CSENBUSY                                 (0x1UL << 0)                         /**< Busy Flag */
+#define _CSEN_STATUS_CSENBUSY_SHIFT                          0                                    /**< Shift value for CSEN_CSENBUSY */
+#define _CSEN_STATUS_CSENBUSY_MASK                           0x1UL                                /**< Bit mask for CSEN_CSENBUSY */
+#define _CSEN_STATUS_CSENBUSY_DEFAULT                        0x00000000UL                         /**< Mode DEFAULT for CSEN_STATUS */
+#define _CSEN_STATUS_CSENBUSY_IDLE                           0x00000000UL                         /**< Mode IDLE for CSEN_STATUS */
+#define _CSEN_STATUS_CSENBUSY_BUSY                           0x00000001UL                         /**< Mode BUSY for CSEN_STATUS */
+#define CSEN_STATUS_CSENBUSY_DEFAULT                         (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */
+#define CSEN_STATUS_CSENBUSY_IDLE                            (_CSEN_STATUS_CSENBUSY_IDLE << 0)    /**< Shifted mode IDLE for CSEN_STATUS */
+#define CSEN_STATUS_CSENBUSY_BUSY                            (_CSEN_STATUS_CSENBUSY_BUSY << 0)    /**< Shifted mode BUSY for CSEN_STATUS */
+
+/* Bit fields for CSEN PRSSEL */
+#define _CSEN_PRSSEL_RESETVALUE                              0x00000000UL                       /**< Default value for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_MASK                                    0x0000000FUL                       /**< Mask for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_SHIFT                            0                                  /**< Shift value for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_MASK                             0xFUL                              /**< Bit mask for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH0                           0x00000000UL                       /**< Mode PRSCH0 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH1                           0x00000001UL                       /**< Mode PRSCH1 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH2                           0x00000002UL                       /**< Mode PRSCH2 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH3                           0x00000003UL                       /**< Mode PRSCH3 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH4                           0x00000004UL                       /**< Mode PRSCH4 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH5                           0x00000005UL                       /**< Mode PRSCH5 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH6                           0x00000006UL                       /**< Mode PRSCH6 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH7                           0x00000007UL                       /**< Mode PRSCH7 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH8                           0x00000008UL                       /**< Mode PRSCH8 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH9                           0x00000009UL                       /**< Mode PRSCH9 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH10                          0x0000000AUL                       /**< Mode PRSCH10 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH11                          0x0000000BUL                       /**< Mode PRSCH11 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH12                          0x0000000CUL                       /**< Mode PRSCH12 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH13                          0x0000000DUL                       /**< Mode PRSCH13 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH14                          0x0000000EUL                       /**< Mode PRSCH14 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH15                          0x0000000FUL                       /**< Mode PRSCH15 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_DEFAULT                           (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH0                            (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0)  /**< Shifted mode PRSCH0 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH1                            (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0)  /**< Shifted mode PRSCH1 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH2                            (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0)  /**< Shifted mode PRSCH2 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH3                            (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0)  /**< Shifted mode PRSCH3 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH4                            (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0)  /**< Shifted mode PRSCH4 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH5                            (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0)  /**< Shifted mode PRSCH5 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH6                            (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0)  /**< Shifted mode PRSCH6 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH7                            (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0)  /**< Shifted mode PRSCH7 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH8                            (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0)  /**< Shifted mode PRSCH8 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH9                            (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0)  /**< Shifted mode PRSCH9 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH10                           (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH11                           (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH12                           (_CSEN_PRSSEL_PRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH13                           (_CSEN_PRSSEL_PRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH14                           (_CSEN_PRSSEL_PRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH15                           (_CSEN_PRSSEL_PRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for CSEN_PRSSEL */
+
+/* Bit fields for CSEN DATA */
+#define _CSEN_DATA_RESETVALUE                                0x00000000UL                   /**< Default value for CSEN_DATA */
+#define _CSEN_DATA_MASK                                      0xFFFFFFFFUL                   /**< Mask for CSEN_DATA */
+#define _CSEN_DATA_DATA_SHIFT                                0                              /**< Shift value for CSEN_DATA */
+#define _CSEN_DATA_DATA_MASK                                 0xFFFFFFFFUL                   /**< Bit mask for CSEN_DATA */
+#define _CSEN_DATA_DATA_DEFAULT                              0x00000000UL                   /**< Mode DEFAULT for CSEN_DATA */
+#define CSEN_DATA_DATA_DEFAULT                               (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */
+
+/* Bit fields for CSEN SCANMASK0 */
+#define _CSEN_SCANMASK0_RESETVALUE                           0x00000000UL                               /**< Default value for CSEN_SCANMASK0 */
+#define _CSEN_SCANMASK0_MASK                                 0xFFFFFFFFUL                               /**< Mask for CSEN_SCANMASK0 */
+#define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT                    0                                          /**< Shift value for CSEN_SCANINPUTEN */
+#define _CSEN_SCANMASK0_SCANINPUTEN_MASK                     0xFFFFFFFFUL                               /**< Bit mask for CSEN_SCANINPUTEN */
+#define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for CSEN_SCANMASK0 */
+#define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT                   (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */
+
+/* Bit fields for CSEN SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_RESETVALUE                       0x00000000UL                                              /**< Default value for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_MASK                             0x0F0F0F0FUL                                              /**< Mask for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT               0                                                         /**< Shift value for CSEN_INPUT0TO7SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK                0xFUL                                                     /**< Bit mask for CSEN_INPUT0TO7SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT             0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7        0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15       0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23      0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31      0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7        0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15       0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23      0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31      0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT              (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7         (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0)      /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15        (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0)     /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23       (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0)    /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31       (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0)    /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7         (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0)      /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15        (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0)     /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23       (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0)    /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31       (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0)    /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT              8                                                         /**< Shift value for CSEN_INPUT8TO15SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK               0xF00UL                                                   /**< Bit mask for CSEN_INPUT8TO15SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT            0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7       0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15      0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23     0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31     0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7       0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15      0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23     0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31     0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT             (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8)          /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7        (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8)     /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15       (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8)    /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23      (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8)   /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31      (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8)   /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7        (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8)     /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15       (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8)    /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23      (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8)   /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31      (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8)   /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT             16                                                        /**< Shift value for CSEN_INPUT16TO23SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK              0xF0000UL                                                 /**< Bit mask for CSEN_INPUT16TO23SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT            (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16)        /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16)   /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16)  /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16)   /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16)  /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT             24                                                        /**< Shift value for CSEN_INPUT24TO31SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK              0xF000000UL                                               /**< Bit mask for CSEN_INPUT24TO31SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT            (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24)        /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24)   /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24)  /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24)   /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24)  /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+
+/* Bit fields for CSEN SCANMASK1 */
+#define _CSEN_SCANMASK1_RESETVALUE                           0x00000000UL                               /**< Default value for CSEN_SCANMASK1 */
+#define _CSEN_SCANMASK1_MASK                                 0xFFFFFFFFUL                               /**< Mask for CSEN_SCANMASK1 */
+#define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT                    0                                          /**< Shift value for CSEN_SCANINPUTEN */
+#define _CSEN_SCANMASK1_SCANINPUTEN_MASK                     0xFFFFFFFFUL                               /**< Bit mask for CSEN_SCANINPUTEN */
+#define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for CSEN_SCANMASK1 */
+#define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT                   (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */
+
+/* Bit fields for CSEN SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_RESETVALUE                       0x00000000UL                                              /**< Default value for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_MASK                             0x0F0F0F0FUL                                              /**< Mask for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT             0                                                         /**< Shift value for CSEN_INPUT32TO39SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK              0xFUL                                                     /**< Bit mask for CSEN_INPUT32TO39SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT            (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0)         /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0)    /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0)   /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0)  /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0)  /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0)    /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0)   /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0)  /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0)  /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT             8                                                         /**< Shift value for CSEN_INPUT40TO47SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK              0xF00UL                                                   /**< Bit mask for CSEN_INPUT40TO47SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT            (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8)         /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8)    /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8)   /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8)  /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8)  /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8)    /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8)   /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8)  /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8)  /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT             16                                                        /**< Shift value for CSEN_INPUT48TO55SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK              0xF0000UL                                                 /**< Bit mask for CSEN_INPUT48TO55SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT            (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16)        /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16)   /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16)  /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16)   /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16)  /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT             24                                                        /**< Shift value for CSEN_INPUT56TO63SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK              0xF000000UL                                               /**< Bit mask for CSEN_INPUT56TO63SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT            (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24)        /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24)   /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24)  /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24)   /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24)  /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+
+/* Bit fields for CSEN APORTREQ */
+#define _CSEN_APORTREQ_RESETVALUE                            0x00000000UL                             /**< Default value for CSEN_APORTREQ */
+#define _CSEN_APORTREQ_MASK                                  0x000003FCUL                             /**< Mask for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT1XREQ                             (0x1UL << 2)                             /**< 1 If the Bus Connected to APORT2X is Requested */
+#define _CSEN_APORTREQ_APORT1XREQ_SHIFT                      2                                        /**< Shift value for CSEN_APORT1XREQ */
+#define _CSEN_APORTREQ_APORT1XREQ_MASK                       0x4UL                                    /**< Bit mask for CSEN_APORT1XREQ */
+#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT1XREQ_DEFAULT                     (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT1YREQ                             (0x1UL << 3)                             /**< 1 If the Bus Connected to APORT1X is Requested */
+#define _CSEN_APORTREQ_APORT1YREQ_SHIFT                      3                                        /**< Shift value for CSEN_APORT1YREQ */
+#define _CSEN_APORTREQ_APORT1YREQ_MASK                       0x8UL                                    /**< Bit mask for CSEN_APORT1YREQ */
+#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT1YREQ_DEFAULT                     (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT2XREQ                             (0x1UL << 4)                             /**< 1 If the Bus Connected to APORT2X is Requested */
+#define _CSEN_APORTREQ_APORT2XREQ_SHIFT                      4                                        /**< Shift value for CSEN_APORT2XREQ */
+#define _CSEN_APORTREQ_APORT2XREQ_MASK                       0x10UL                                   /**< Bit mask for CSEN_APORT2XREQ */
+#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT2XREQ_DEFAULT                     (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT2YREQ                             (0x1UL << 5)                             /**< 1 If the Bus Connected to APORT2Y is Requested */
+#define _CSEN_APORTREQ_APORT2YREQ_SHIFT                      5                                        /**< Shift value for CSEN_APORT2YREQ */
+#define _CSEN_APORTREQ_APORT2YREQ_MASK                       0x20UL                                   /**< Bit mask for CSEN_APORT2YREQ */
+#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT2YREQ_DEFAULT                     (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT3XREQ                             (0x1UL << 6)                             /**< 1 If the Bus Connected to APORT3X is Requested */
+#define _CSEN_APORTREQ_APORT3XREQ_SHIFT                      6                                        /**< Shift value for CSEN_APORT3XREQ */
+#define _CSEN_APORTREQ_APORT3XREQ_MASK                       0x40UL                                   /**< Bit mask for CSEN_APORT3XREQ */
+#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT3XREQ_DEFAULT                     (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT3YREQ                             (0x1UL << 7)                             /**< 1 If the Bus Connected to APORT3Y is Requested */
+#define _CSEN_APORTREQ_APORT3YREQ_SHIFT                      7                                        /**< Shift value for CSEN_APORT3YREQ */
+#define _CSEN_APORTREQ_APORT3YREQ_MASK                       0x80UL                                   /**< Bit mask for CSEN_APORT3YREQ */
+#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT3YREQ_DEFAULT                     (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT4XREQ                             (0x1UL << 8)                             /**< 1 If the Bus Connected to APORT4X is Requested */
+#define _CSEN_APORTREQ_APORT4XREQ_SHIFT                      8                                        /**< Shift value for CSEN_APORT4XREQ */
+#define _CSEN_APORTREQ_APORT4XREQ_MASK                       0x100UL                                  /**< Bit mask for CSEN_APORT4XREQ */
+#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT4XREQ_DEFAULT                     (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT4YREQ                             (0x1UL << 9)                             /**< 1 If the Bus Connected to APORT4Y is Requested */
+#define _CSEN_APORTREQ_APORT4YREQ_SHIFT                      9                                        /**< Shift value for CSEN_APORT4YREQ */
+#define _CSEN_APORTREQ_APORT4YREQ_MASK                       0x200UL                                  /**< Bit mask for CSEN_APORT4YREQ */
+#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT4YREQ_DEFAULT                     (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+
+/* Bit fields for CSEN APORTCONFLICT */
+#define _CSEN_APORTCONFLICT_RESETVALUE                       0x00000000UL                                       /**< Default value for CSEN_APORTCONFLICT */
+#define _CSEN_APORTCONFLICT_MASK                             0x000003FCUL                                       /**< Mask for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT1XCONFLICT                   (0x1UL << 2)                                       /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT            2                                                  /**< Shift value for CSEN_APORT1XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK             0x4UL                                              /**< Bit mask for CSEN_APORT1XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT1YCONFLICT                   (0x1UL << 3)                                       /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT            3                                                  /**< Shift value for CSEN_APORT1YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK             0x8UL                                              /**< Bit mask for CSEN_APORT1YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT2XCONFLICT                   (0x1UL << 4)                                       /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT            4                                                  /**< Shift value for CSEN_APORT2XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK             0x10UL                                             /**< Bit mask for CSEN_APORT2XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT2YCONFLICT                   (0x1UL << 5)                                       /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT            5                                                  /**< Shift value for CSEN_APORT2YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK             0x20UL                                             /**< Bit mask for CSEN_APORT2YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT3XCONFLICT                   (0x1UL << 6)                                       /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT            6                                                  /**< Shift value for CSEN_APORT3XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK             0x40UL                                             /**< Bit mask for CSEN_APORT3XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT3YCONFLICT                   (0x1UL << 7)                                       /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT            7                                                  /**< Shift value for CSEN_APORT3YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK             0x80UL                                             /**< Bit mask for CSEN_APORT3YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT4XCONFLICT                   (0x1UL << 8)                                       /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT            8                                                  /**< Shift value for CSEN_APORT4XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK             0x100UL                                            /**< Bit mask for CSEN_APORT4XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT4YCONFLICT                   (0x1UL << 9)                                       /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT            9                                                  /**< Shift value for CSEN_APORT4YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK             0x200UL                                            /**< Bit mask for CSEN_APORT4YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+
+/* Bit fields for CSEN CMPTHR */
+#define _CSEN_CMPTHR_RESETVALUE                              0x00000000UL                       /**< Default value for CSEN_CMPTHR */
+#define _CSEN_CMPTHR_MASK                                    0x0000FFFFUL                       /**< Mask for CSEN_CMPTHR */
+#define _CSEN_CMPTHR_CMPTHR_SHIFT                            0                                  /**< Shift value for CSEN_CMPTHR */
+#define _CSEN_CMPTHR_CMPTHR_MASK                             0xFFFFUL                           /**< Bit mask for CSEN_CMPTHR */
+#define _CSEN_CMPTHR_CMPTHR_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for CSEN_CMPTHR */
+#define CSEN_CMPTHR_CMPTHR_DEFAULT                           (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */
+
+/* Bit fields for CSEN EMA */
+#define _CSEN_EMA_RESETVALUE                                 0x00000000UL                 /**< Default value for CSEN_EMA */
+#define _CSEN_EMA_MASK                                       0x003FFFFFUL                 /**< Mask for CSEN_EMA */
+#define _CSEN_EMA_EMA_SHIFT                                  0                            /**< Shift value for CSEN_EMA */
+#define _CSEN_EMA_EMA_MASK                                   0x3FFFFFUL                   /**< Bit mask for CSEN_EMA */
+#define _CSEN_EMA_EMA_DEFAULT                                0x00000000UL                 /**< Mode DEFAULT for CSEN_EMA */
+#define CSEN_EMA_EMA_DEFAULT                                 (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */
+
+/* Bit fields for CSEN EMACTRL */
+#define _CSEN_EMACTRL_RESETVALUE                             0x00000000UL                           /**< Default value for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_MASK                                   0x00000007UL                           /**< Mask for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_SHIFT                        0                                      /**< Shift value for CSEN_EMASAMPLE */
+#define _CSEN_EMACTRL_EMASAMPLE_MASK                         0x7UL                                  /**< Bit mask for CSEN_EMASAMPLE */
+#define _CSEN_EMACTRL_EMASAMPLE_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W1                           0x00000000UL                           /**< Mode W1 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W2                           0x00000001UL                           /**< Mode W2 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W4                           0x00000002UL                           /**< Mode W4 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W8                           0x00000003UL                           /**< Mode W8 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W16                          0x00000004UL                           /**< Mode W16 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W32                          0x00000005UL                           /**< Mode W32 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W64                          0x00000006UL                           /**< Mode W64 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_DEFAULT                       (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W1                            (_CSEN_EMACTRL_EMASAMPLE_W1 << 0)      /**< Shifted mode W1 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W2                            (_CSEN_EMACTRL_EMASAMPLE_W2 << 0)      /**< Shifted mode W2 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W4                            (_CSEN_EMACTRL_EMASAMPLE_W4 << 0)      /**< Shifted mode W4 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W8                            (_CSEN_EMACTRL_EMASAMPLE_W8 << 0)      /**< Shifted mode W8 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W16                           (_CSEN_EMACTRL_EMASAMPLE_W16 << 0)     /**< Shifted mode W16 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W32                           (_CSEN_EMACTRL_EMASAMPLE_W32 << 0)     /**< Shifted mode W32 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W64                           (_CSEN_EMACTRL_EMASAMPLE_W64 << 0)     /**< Shifted mode W64 for CSEN_EMACTRL */
+
+/* Bit fields for CSEN SINGLECTRL */
+#define _CSEN_SINGLECTRL_RESETVALUE                          0x00000000UL                                  /**< Default value for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_MASK                                0x000007F0UL                                  /**< Mask for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_SHIFT                     4                                             /**< Shift value for CSEN_SINGLESEL */
+#define _CSEN_SINGLECTRL_SINGLESEL_MASK                      0x7F0UL                                       /**< Bit mask for CSEN_SINGLESEL */
+#define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT                   0x00000000UL                                  /**< Mode DEFAULT for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0                0x00000020UL                                  /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1                0x00000021UL                                  /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2                0x00000022UL                                  /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3                0x00000023UL                                  /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4                0x00000024UL                                  /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5                0x00000025UL                                  /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6                0x00000026UL                                  /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7                0x00000027UL                                  /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8                0x00000028UL                                  /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9                0x00000029UL                                  /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10               0x0000002AUL                                  /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11               0x0000002BUL                                  /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12               0x0000002CUL                                  /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13               0x0000002DUL                                  /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14               0x0000002EUL                                  /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15               0x0000002FUL                                  /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16               0x00000030UL                                  /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17               0x00000031UL                                  /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18               0x00000032UL                                  /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19               0x00000033UL                                  /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20               0x00000034UL                                  /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21               0x00000035UL                                  /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22               0x00000036UL                                  /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23               0x00000037UL                                  /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24               0x00000038UL                                  /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25               0x00000039UL                                  /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26               0x0000003AUL                                  /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27               0x0000003BUL                                  /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28               0x0000003CUL                                  /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29               0x0000003DUL                                  /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30               0x0000003EUL                                  /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31               0x0000003FUL                                  /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0                0x00000060UL                                  /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1                0x00000061UL                                  /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2                0x00000062UL                                  /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3                0x00000063UL                                  /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4                0x00000064UL                                  /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5                0x00000065UL                                  /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6                0x00000066UL                                  /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7                0x00000067UL                                  /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8                0x00000068UL                                  /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9                0x00000069UL                                  /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10               0x0000006AUL                                  /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11               0x0000006BUL                                  /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12               0x0000006CUL                                  /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13               0x0000006DUL                                  /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14               0x0000006EUL                                  /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15               0x0000006FUL                                  /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16               0x00000070UL                                  /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17               0x00000071UL                                  /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18               0x00000072UL                                  /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19               0x00000073UL                                  /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20               0x00000074UL                                  /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21               0x00000075UL                                  /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22               0x00000076UL                                  /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23               0x00000077UL                                  /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24               0x00000078UL                                  /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25               0x00000079UL                                  /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26               0x0000007AUL                                  /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27               0x0000007BUL                                  /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28               0x0000007CUL                                  /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29               0x0000007DUL                                  /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30               0x0000007EUL                                  /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31               0x0000007FUL                                  /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_DEFAULT                    (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4)     /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4)  /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4)  /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4)  /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4)  /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4)  /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4)  /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4)  /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4)  /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4)  /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4)  /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4)  /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4)  /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4)  /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4)  /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4)  /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4)  /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4)  /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4)  /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4)  /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4)  /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */
+
+/* Bit fields for CSEN DMBASELINE */
+#define _CSEN_DMBASELINE_RESETVALUE                          0x00000000UL                                /**< Default value for CSEN_DMBASELINE */
+#define _CSEN_DMBASELINE_MASK                                0xFFFFFFFFUL                                /**< Mask for CSEN_DMBASELINE */
+#define _CSEN_DMBASELINE_BASELINEUP_SHIFT                    0                                           /**< Shift value for CSEN_BASELINEUP */
+#define _CSEN_DMBASELINE_BASELINEUP_MASK                     0xFFFFUL                                    /**< Bit mask for CSEN_BASELINEUP */
+#define _CSEN_DMBASELINE_BASELINEUP_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CSEN_DMBASELINE */
+#define CSEN_DMBASELINE_BASELINEUP_DEFAULT                   (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0)  /**< Shifted mode DEFAULT for CSEN_DMBASELINE */
+#define _CSEN_DMBASELINE_BASELINEDN_SHIFT                    16                                          /**< Shift value for CSEN_BASELINEDN */
+#define _CSEN_DMBASELINE_BASELINEDN_MASK                     0xFFFF0000UL                                /**< Bit mask for CSEN_BASELINEDN */
+#define _CSEN_DMBASELINE_BASELINEDN_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CSEN_DMBASELINE */
+#define CSEN_DMBASELINE_BASELINEDN_DEFAULT                   (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */
+
+/* Bit fields for CSEN DMCFG */
+#define _CSEN_DMCFG_RESETVALUE                               0x00000000UL                        /**< Default value for CSEN_DMCFG */
+#define _CSEN_DMCFG_MASK                                     0x103F0FFFUL                        /**< Mask for CSEN_DMCFG */
+#define _CSEN_DMCFG_DMG_SHIFT                                0                                   /**< Shift value for CSEN_DMG */
+#define _CSEN_DMCFG_DMG_MASK                                 0xFFUL                              /**< Bit mask for CSEN_DMG */
+#define _CSEN_DMCFG_DMG_DEFAULT                              0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_DMG_DEFAULT                               (_CSEN_DMCFG_DMG_DEFAULT << 0)      /**< Shifted mode DEFAULT for CSEN_DMCFG */
+#define _CSEN_DMCFG_DMR_SHIFT                                8                                   /**< Shift value for CSEN_DMR */
+#define _CSEN_DMCFG_DMR_MASK                                 0xF00UL                             /**< Bit mask for CSEN_DMR */
+#define _CSEN_DMCFG_DMR_DEFAULT                              0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_DMR_DEFAULT                               (_CSEN_DMCFG_DMR_DEFAULT << 8)      /**< Shifted mode DEFAULT for CSEN_DMCFG */
+#define _CSEN_DMCFG_DMCR_SHIFT                               16                                  /**< Shift value for CSEN_DMCR */
+#define _CSEN_DMCFG_DMCR_MASK                                0xF0000UL                           /**< Bit mask for CSEN_DMCR */
+#define _CSEN_DMCFG_DMCR_DEFAULT                             0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_DMCR_DEFAULT                              (_CSEN_DMCFG_DMCR_DEFAULT << 16)    /**< Shifted mode DEFAULT for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_SHIFT                             20                                  /**< Shift value for CSEN_CRMODE */
+#define _CSEN_DMCFG_CRMODE_MASK                              0x300000UL                          /**< Bit mask for CSEN_CRMODE */
+#define _CSEN_DMCFG_CRMODE_DEFAULT                           0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_DM10                              0x00000000UL                        /**< Mode DM10 for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_DM12                              0x00000001UL                        /**< Mode DM12 for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_DM14                              0x00000002UL                        /**< Mode DM14 for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_DM16                              0x00000003UL                        /**< Mode DM16 for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DEFAULT                            (_CSEN_DMCFG_CRMODE_DEFAULT << 20)  /**< Shifted mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DM10                               (_CSEN_DMCFG_CRMODE_DM10 << 20)     /**< Shifted mode DM10 for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DM12                               (_CSEN_DMCFG_CRMODE_DM12 << 20)     /**< Shifted mode DM12 for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DM14                               (_CSEN_DMCFG_CRMODE_DM14 << 20)     /**< Shifted mode DM14 for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DM16                               (_CSEN_DMCFG_CRMODE_DM16 << 20)     /**< Shifted mode DM16 for CSEN_DMCFG */
+#define CSEN_DMCFG_DMGRDIS                                   (0x1UL << 28)                       /**< Delta Modulation Gain Step Reduction Disable */
+#define _CSEN_DMCFG_DMGRDIS_SHIFT                            28                                  /**< Shift value for CSEN_DMGRDIS */
+#define _CSEN_DMCFG_DMGRDIS_MASK                             0x10000000UL                        /**< Bit mask for CSEN_DMGRDIS */
+#define _CSEN_DMCFG_DMGRDIS_DEFAULT                          0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_DMGRDIS_DEFAULT                           (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */
+
+/* Bit fields for CSEN ANACTRL */
+#define _CSEN_ANACTRL_RESETVALUE                             0x00000070UL                           /**< Default value for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_MASK                                   0x00700770UL                           /**< Mask for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_IREFPROG_SHIFT                         4                                      /**< Shift value for CSEN_IREFPROG */
+#define _CSEN_ANACTRL_IREFPROG_MASK                          0x70UL                                 /**< Bit mask for CSEN_IREFPROG */
+#define _CSEN_ANACTRL_IREFPROG_DEFAULT                       0x00000007UL                           /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_IREFPROG_DEFAULT                        (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4)  /**< Shifted mode DEFAULT for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_IDACIREFS_SHIFT                        8                                      /**< Shift value for CSEN_IDACIREFS */
+#define _CSEN_ANACTRL_IDACIREFS_MASK                         0x700UL                                /**< Bit mask for CSEN_IDACIREFS */
+#define _CSEN_ANACTRL_IDACIREFS_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_IDACIREFS_DEFAULT                       (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_TRSTPROG_SHIFT                         20                                     /**< Shift value for CSEN_TRSTPROG */
+#define _CSEN_ANACTRL_TRSTPROG_MASK                          0x700000UL                             /**< Bit mask for CSEN_TRSTPROG */
+#define _CSEN_ANACTRL_TRSTPROG_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_TRSTPROG_DEFAULT                        (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
+
+/* Bit fields for CSEN IF */
+#define _CSEN_IF_RESETVALUE                                  0x00000000UL                          /**< Default value for CSEN_IF */
+#define _CSEN_IF_MASK                                        0x0000001FUL                          /**< Mask for CSEN_IF */
+#define CSEN_IF_CMP                                          (0x1UL << 0)                          /**< Digital Comparator Interrupt Flag */
+#define _CSEN_IF_CMP_SHIFT                                   0                                     /**< Shift value for CSEN_CMP */
+#define _CSEN_IF_CMP_MASK                                    0x1UL                                 /**< Bit mask for CSEN_CMP */
+#define _CSEN_IF_CMP_DEFAULT                                 0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_CMP_DEFAULT                                  (_CSEN_IF_CMP_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_IF */
+#define CSEN_IF_CONV                                         (0x1UL << 1)                          /**< Conversion Done Interrupt Flag */
+#define _CSEN_IF_CONV_SHIFT                                  1                                     /**< Shift value for CSEN_CONV */
+#define _CSEN_IF_CONV_MASK                                   0x2UL                                 /**< Bit mask for CSEN_CONV */
+#define _CSEN_IF_CONV_DEFAULT                                0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_CONV_DEFAULT                                 (_CSEN_IF_CONV_DEFAULT << 1)          /**< Shifted mode DEFAULT for CSEN_IF */
+#define CSEN_IF_EOS                                          (0x1UL << 2)                          /**< End of Scan Interrupt Flag. */
+#define _CSEN_IF_EOS_SHIFT                                   2                                     /**< Shift value for CSEN_EOS */
+#define _CSEN_IF_EOS_MASK                                    0x4UL                                 /**< Bit mask for CSEN_EOS */
+#define _CSEN_IF_EOS_DEFAULT                                 0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_EOS_DEFAULT                                  (_CSEN_IF_EOS_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_IF */
+#define CSEN_IF_DMAOF                                        (0x1UL << 3)                          /**< DMA Overflow Interrupt Flag. */
+#define _CSEN_IF_DMAOF_SHIFT                                 3                                     /**< Shift value for CSEN_DMAOF */
+#define _CSEN_IF_DMAOF_MASK                                  0x8UL                                 /**< Bit mask for CSEN_DMAOF */
+#define _CSEN_IF_DMAOF_DEFAULT                               0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_DMAOF_DEFAULT                                (_CSEN_IF_DMAOF_DEFAULT << 3)         /**< Shifted mode DEFAULT for CSEN_IF */
+#define CSEN_IF_APORTCONFLICT                                (0x1UL << 4)                          /**< APORT Conflict Interrupt Flag */
+#define _CSEN_IF_APORTCONFLICT_SHIFT                         4                                     /**< Shift value for CSEN_APORTCONFLICT */
+#define _CSEN_IF_APORTCONFLICT_MASK                          0x10UL                                /**< Bit mask for CSEN_APORTCONFLICT */
+#define _CSEN_IF_APORTCONFLICT_DEFAULT                       0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_APORTCONFLICT_DEFAULT                        (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */
+
+/* Bit fields for CSEN IFS */
+#define _CSEN_IFS_RESETVALUE                                 0x00000000UL                           /**< Default value for CSEN_IFS */
+#define _CSEN_IFS_MASK                                       0x0000001FUL                           /**< Mask for CSEN_IFS */
+#define CSEN_IFS_CMP                                         (0x1UL << 0)                           /**< Set CMP Interrupt Flag */
+#define _CSEN_IFS_CMP_SHIFT                                  0                                      /**< Shift value for CSEN_CMP */
+#define _CSEN_IFS_CMP_MASK                                   0x1UL                                  /**< Bit mask for CSEN_CMP */
+#define _CSEN_IFS_CMP_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_CMP_DEFAULT                                 (_CSEN_IFS_CMP_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_CONV                                        (0x1UL << 1)                           /**< Set CONV Interrupt Flag */
+#define _CSEN_IFS_CONV_SHIFT                                 1                                      /**< Shift value for CSEN_CONV */
+#define _CSEN_IFS_CONV_MASK                                  0x2UL                                  /**< Bit mask for CSEN_CONV */
+#define _CSEN_IFS_CONV_DEFAULT                               0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_CONV_DEFAULT                                (_CSEN_IFS_CONV_DEFAULT << 1)          /**< Shifted mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_EOS                                         (0x1UL << 2)                           /**< Set EOS Interrupt Flag */
+#define _CSEN_IFS_EOS_SHIFT                                  2                                      /**< Shift value for CSEN_EOS */
+#define _CSEN_IFS_EOS_MASK                                   0x4UL                                  /**< Bit mask for CSEN_EOS */
+#define _CSEN_IFS_EOS_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_EOS_DEFAULT                                 (_CSEN_IFS_EOS_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_DMAOF                                       (0x1UL << 3)                           /**< Set DMAOF Interrupt Flag */
+#define _CSEN_IFS_DMAOF_SHIFT                                3                                      /**< Shift value for CSEN_DMAOF */
+#define _CSEN_IFS_DMAOF_MASK                                 0x8UL                                  /**< Bit mask for CSEN_DMAOF */
+#define _CSEN_IFS_DMAOF_DEFAULT                              0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_DMAOF_DEFAULT                               (_CSEN_IFS_DMAOF_DEFAULT << 3)         /**< Shifted mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_APORTCONFLICT                               (0x1UL << 4)                           /**< Set APORTCONFLICT Interrupt Flag */
+#define _CSEN_IFS_APORTCONFLICT_SHIFT                        4                                      /**< Shift value for CSEN_APORTCONFLICT */
+#define _CSEN_IFS_APORTCONFLICT_MASK                         0x10UL                                 /**< Bit mask for CSEN_APORTCONFLICT */
+#define _CSEN_IFS_APORTCONFLICT_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_APORTCONFLICT_DEFAULT                       (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */
+
+/* Bit fields for CSEN IFC */
+#define _CSEN_IFC_RESETVALUE                                 0x00000000UL                           /**< Default value for CSEN_IFC */
+#define _CSEN_IFC_MASK                                       0x0000001FUL                           /**< Mask for CSEN_IFC */
+#define CSEN_IFC_CMP                                         (0x1UL << 0)                           /**< Clear CMP Interrupt Flag */
+#define _CSEN_IFC_CMP_SHIFT                                  0                                      /**< Shift value for CSEN_CMP */
+#define _CSEN_IFC_CMP_MASK                                   0x1UL                                  /**< Bit mask for CSEN_CMP */
+#define _CSEN_IFC_CMP_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_CMP_DEFAULT                                 (_CSEN_IFC_CMP_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_CONV                                        (0x1UL << 1)                           /**< Clear CONV Interrupt Flag */
+#define _CSEN_IFC_CONV_SHIFT                                 1                                      /**< Shift value for CSEN_CONV */
+#define _CSEN_IFC_CONV_MASK                                  0x2UL                                  /**< Bit mask for CSEN_CONV */
+#define _CSEN_IFC_CONV_DEFAULT                               0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_CONV_DEFAULT                                (_CSEN_IFC_CONV_DEFAULT << 1)          /**< Shifted mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_EOS                                         (0x1UL << 2)                           /**< Clear EOS Interrupt Flag */
+#define _CSEN_IFC_EOS_SHIFT                                  2                                      /**< Shift value for CSEN_EOS */
+#define _CSEN_IFC_EOS_MASK                                   0x4UL                                  /**< Bit mask for CSEN_EOS */
+#define _CSEN_IFC_EOS_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_EOS_DEFAULT                                 (_CSEN_IFC_EOS_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_DMAOF                                       (0x1UL << 3)                           /**< Clear DMAOF Interrupt Flag */
+#define _CSEN_IFC_DMAOF_SHIFT                                3                                      /**< Shift value for CSEN_DMAOF */
+#define _CSEN_IFC_DMAOF_MASK                                 0x8UL                                  /**< Bit mask for CSEN_DMAOF */
+#define _CSEN_IFC_DMAOF_DEFAULT                              0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_DMAOF_DEFAULT                               (_CSEN_IFC_DMAOF_DEFAULT << 3)         /**< Shifted mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_APORTCONFLICT                               (0x1UL << 4)                           /**< Clear APORTCONFLICT Interrupt Flag */
+#define _CSEN_IFC_APORTCONFLICT_SHIFT                        4                                      /**< Shift value for CSEN_APORTCONFLICT */
+#define _CSEN_IFC_APORTCONFLICT_MASK                         0x10UL                                 /**< Bit mask for CSEN_APORTCONFLICT */
+#define _CSEN_IFC_APORTCONFLICT_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_APORTCONFLICT_DEFAULT                       (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */
+
+/* Bit fields for CSEN IEN */
+#define _CSEN_IEN_RESETVALUE                                 0x00000000UL                           /**< Default value for CSEN_IEN */
+#define _CSEN_IEN_MASK                                       0x0000001FUL                           /**< Mask for CSEN_IEN */
+#define CSEN_IEN_CMP                                         (0x1UL << 0)                           /**< CMP Interrupt Enable */
+#define _CSEN_IEN_CMP_SHIFT                                  0                                      /**< Shift value for CSEN_CMP */
+#define _CSEN_IEN_CMP_MASK                                   0x1UL                                  /**< Bit mask for CSEN_CMP */
+#define _CSEN_IEN_CMP_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_CMP_DEFAULT                                 (_CSEN_IEN_CMP_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_CONV                                        (0x1UL << 1)                           /**< CONV Interrupt Enable */
+#define _CSEN_IEN_CONV_SHIFT                                 1                                      /**< Shift value for CSEN_CONV */
+#define _CSEN_IEN_CONV_MASK                                  0x2UL                                  /**< Bit mask for CSEN_CONV */
+#define _CSEN_IEN_CONV_DEFAULT                               0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_CONV_DEFAULT                                (_CSEN_IEN_CONV_DEFAULT << 1)          /**< Shifted mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_EOS                                         (0x1UL << 2)                           /**< EOS Interrupt Enable */
+#define _CSEN_IEN_EOS_SHIFT                                  2                                      /**< Shift value for CSEN_EOS */
+#define _CSEN_IEN_EOS_MASK                                   0x4UL                                  /**< Bit mask for CSEN_EOS */
+#define _CSEN_IEN_EOS_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_EOS_DEFAULT                                 (_CSEN_IEN_EOS_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_DMAOF                                       (0x1UL << 3)                           /**< DMAOF Interrupt Enable */
+#define _CSEN_IEN_DMAOF_SHIFT                                3                                      /**< Shift value for CSEN_DMAOF */
+#define _CSEN_IEN_DMAOF_MASK                                 0x8UL                                  /**< Bit mask for CSEN_DMAOF */
+#define _CSEN_IEN_DMAOF_DEFAULT                              0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_DMAOF_DEFAULT                               (_CSEN_IEN_DMAOF_DEFAULT << 3)         /**< Shifted mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_APORTCONFLICT                               (0x1UL << 4)                           /**< APORTCONFLICT Interrupt Enable */
+#define _CSEN_IEN_APORTCONFLICT_SHIFT                        4                                      /**< Shift value for CSEN_APORTCONFLICT */
+#define _CSEN_IEN_APORTCONFLICT_MASK                         0x10UL                                 /**< Bit mask for CSEN_APORTCONFLICT */
+#define _CSEN_IEN_APORTCONFLICT_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_APORTCONFLICT_DEFAULT                       (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */
+
+/** @} */
+/** @} End of group EFM32GG12B_CSEN */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+
--- a/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_devinfo.h
+++ b/cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_devinfo.h
--- a/Show More
+++ b/Show More