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Merge pull request #15043 from aabadie/pr/boards/stm32f2f4f7_remove_96_180

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boards/stm32f4: remove default clock configuration for 96MHz and 168MHz CPUs
This commit is contained in:
benpicco 2020-10-19 19:42:52 +02:00 committed by GitHub
commit d98f93513f
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GPG Key ID: 4AEE18F83AFDEB23
13 changed files with 63 additions and 193 deletions
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23
boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h
View File

@ -33,17 +33,36 @@ extern "C" {
* @name Clock PLL settings (100MHz)
* @{
*/
/* The following parameters configure a 100MHz system clock with HSE (8MHz or
16MHz) or HSI (16MHz) as PLL input clock */
/* The following parameters configure a 100MHz system clock with HSE (8MHz, 16MHz or
25MHz) or HSI (16MHz) as PLL input clock.
If USB is used and no alternative 48MHz is available, the clock frequency is
decreased to 96MHZ so the PLLQ can output 48MHz.
*/
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_M (25)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_USED(MODULE_PERIPH_USBDEV) && defined(CPU_LINE_STM32F411xE)
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (96)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (192)
#else
#define CONFIG_CLOCK_PLL_N (48)
#endif
#else
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (100)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (200)
#else
#define CONFIG_CLOCK_PLL_N (50)
#endif
#endif /* MODULE_PERIPH_USBDEV */
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)

90
boards/common/stm32/include/f2f4f7/cfg_clock_default_168.h
View File

@ -1,90 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F4 clock configuration for 168MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_168_H
#define F2F4F7_CFG_CLOCK_DEFAULT_168_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (180MHz)
*
* The PLL settings provided here can be used for USB on CPU with a max
* frequency of 180MHz.
* @{
*/
/* The following parameters configure a 168MHz system clock with HSE
(8MHz, 12MHz or 16MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
#define CONFIG_CLOCK_PLL_M (12)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
#define CONFIG_CLOCK_PLL_N (336)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (168)
#else
#define CONFIG_CLOCK_PLL_N (84)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (7)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (0)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(180)
#error "SYSCLK cannot exceed 180MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_168_H */
/** @} */

35
boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h
View File

@ -33,24 +33,55 @@ extern "C" {
* @name Clock PLL settings (180MHz)
* @{
*/
/* The following parameters configure a 180MHz system clock with HSE (8MHz or
16MHz) or HSI (16MHz) as PLL input clock */
/* The following parameters configure a 180MHz system clock with HSE (8MHz,
12MHz or 16MHz) or HSI (16MHz) as PLL input clock.
If USB is used and no alternative 48MHz is available, the clock frequency is
decreased to 168MHZ so the PLLQ can output 48MHz.
*/
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
#define CONFIG_CLOCK_PLL_M (12)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_USED(MODULE_PERIPH_USBDEV) && \
(defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (168)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
#define CONFIG_CLOCK_PLL_N (336)
#else
#define CONFIG_CLOCK_PLL_N (84)
#endif
#else
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (180)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
#define CONFIG_CLOCK_PLL_N (360)
#else
#define CONFIG_CLOCK_PLL_N (90)
#endif
#endif /* MODULE_PERIPH_USBDEV */
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#if IS_USED(MODULE_PERIPH_USBDEV) && \
(defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
#define CONFIG_CLOCK_PLL_Q (7)
#else
#define CONFIG_CLOCK_PLL_Q (8)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (8)
#endif

90
boards/common/stm32/include/f2f4f7/cfg_clock_default_96.h
View File

@ -1,90 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F4 clock configuration for 96MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_96_H
#define F2F4F7_CFG_CLOCK_DEFAULT_96_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (100MHz)
*
* The PLL settings provided here can be used for USB on CPU with a max
* frequency of 100MHz.
* @{
*/
/* The following parameters configure a 96MHz system clock with HSE (8MHz, 16MHz or
25MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_M (25)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (192)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (96)
#else
#define CONFIG_CLOCK_PLL_N (48)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (4)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (4)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (2) /* max 50MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1) /* max 100MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(100)
#error "SYSCLK cannot exceed 100MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_96_H */
/** @} */

2
boards/f4vi1/include/periph_conf.h
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@ -30,7 +30,7 @@
#define CLOCK_HSE MHZ(16)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "f2f4f7/cfg_clock_default_180.h"
#ifdef __cplusplus
extern "C" {

2
boards/msbiot/include/periph_conf.h
View File

@ -28,7 +28,7 @@
#define CLOCK_HSE MHZ(16)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "f2f4f7/cfg_clock_default_180.h"
#ifdef __cplusplus
extern "C" {

2
boards/nucleo-f410rb/include/periph_conf.h
View File

@ -30,7 +30,7 @@
#endif
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_96.h"
#include "f2f4f7/cfg_clock_default_100.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

2
boards/nucleo-f429zi/include/periph_conf.h
View File

@ -30,7 +30,7 @@
#endif
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

2
boards/pyboard/include/periph_conf.h
View File

@ -35,7 +35,7 @@
#define CLOCK_HSE MHZ(12)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus

2
boards/stm32f429i-disc1/include/periph_conf.h
View File

@ -30,7 +30,7 @@
#endif
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_hs_fs.h"

2
boards/stm32f4discovery/include/periph_conf.h
View File

@ -26,7 +26,7 @@
#endif
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus

2
boards/ublox-c030-u201/include/periph_conf.h
View File

@ -33,7 +33,7 @@
#define CLOCK_HSE MHZ(12)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_timer_tim5.h"
#ifdef __cplusplus

2
boards/weact-f411ce/include/periph_conf.h
View File

@ -36,7 +36,7 @@
#define CLOCK_HSE MHZ(25)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_96.h"
#include "f2f4f7/cfg_clock_default_100.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"