From 0828400eb0182bb08618d52d3cba6e0958b64af7 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 18 Sep 2020 09:53:49 +0200 Subject: [PATCH 1/5] boards/stm32f2f4f7: adapt 100MHz clock config for USB --- .../include/f2f4f7/cfg_clock_default_100.h | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h b/boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h index 0fa770e538..802772b1ab 100644 --- a/boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h +++ b/boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h @@ -33,17 +33,36 @@ extern "C" { * @name Clock PLL settings (100MHz) * @{ */ -/* The following parameters configure a 100MHz system clock with HSE (8MHz or - 16MHz) or HSI (16MHz) as PLL input clock */ +/* The following parameters configure a 100MHz system clock with HSE (8MHz, 16MHz or + 25MHz) or HSI (16MHz) as PLL input clock. + If USB is used and no alternative 48MHz is available, the clock frequency is + decreased to 96MHZ so the PLLQ can output 48MHz. + */ #ifndef CONFIG_CLOCK_PLL_M +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#define CONFIG_CLOCK_PLL_M (25) +#else #define CONFIG_CLOCK_PLL_M (4) #endif +#endif #ifndef CONFIG_CLOCK_PLL_N +#if IS_USED(MODULE_PERIPH_USBDEV) && defined(CPU_LINE_STM32F411xE) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#define CONFIG_CLOCK_PLL_N (96) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#define CONFIG_CLOCK_PLL_N (192) +#else +#define CONFIG_CLOCK_PLL_N (48) +#endif +#else #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (100) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#define CONFIG_CLOCK_PLL_N (200) #else #define CONFIG_CLOCK_PLL_N (50) #endif +#endif /* MODULE_PERIPH_USBDEV */ #endif #ifndef CONFIG_CLOCK_PLL_P #define CONFIG_CLOCK_PLL_P (2) From 67d03c91d159dbfdf6ca4ccdc07a523b3d2229b9 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 18 Sep 2020 09:54:01 +0200 Subject: [PATCH 2/5] boards/stm32f2f4f7: adapt 180MHz clock config for USB --- .../include/f2f4f7/cfg_clock_default_180.h | 35 +++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h b/boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h index ae0c378ce5..09d0653d4e 100644 --- a/boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h +++ b/boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h @@ -33,24 +33,55 @@ extern "C" { * @name Clock PLL settings (180MHz) * @{ */ -/* The following parameters configure a 180MHz system clock with HSE (8MHz or - 16MHz) or HSI (16MHz) as PLL input clock */ +/* The following parameters configure a 180MHz system clock with HSE (8MHz, + 12MHz or 16MHz) or HSI (16MHz) as PLL input clock. + If USB is used and no alternative 48MHz is available, the clock frequency is + decreased to 168MHZ so the PLLQ can output 48MHz. + */ #ifndef CONFIG_CLOCK_PLL_M +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12)) +#define CONFIG_CLOCK_PLL_M (12) +#else #define CONFIG_CLOCK_PLL_M (4) #endif +#endif #ifndef CONFIG_CLOCK_PLL_N +#if IS_USED(MODULE_PERIPH_USBDEV) && \ + (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \ + defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \ + defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \ + defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#define CONFIG_CLOCK_PLL_N (168) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12)) +#define CONFIG_CLOCK_PLL_N (336) +#else +#define CONFIG_CLOCK_PLL_N (84) +#endif +#else #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (180) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12)) +#define CONFIG_CLOCK_PLL_N (360) #else #define CONFIG_CLOCK_PLL_N (90) #endif +#endif /* MODULE_PERIPH_USBDEV */ #endif #ifndef CONFIG_CLOCK_PLL_P #define CONFIG_CLOCK_PLL_P (2) #endif #ifndef CONFIG_CLOCK_PLL_Q +#if IS_USED(MODULE_PERIPH_USBDEV) && \ + (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \ + defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \ + defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \ + defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx)) +#define CONFIG_CLOCK_PLL_Q (7) +#else #define CONFIG_CLOCK_PLL_Q (8) #endif +#endif #ifndef CONFIG_CLOCK_PLL_R #define CONFIG_CLOCK_PLL_R (8) #endif From 022d3d5e9edf51f17f3c216b30237ac7efd75b7c Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 18 Sep 2020 09:54:47 +0200 Subject: [PATCH 3/5] boards/stm32f410/411: use 100MHz default clock header --- boards/nucleo-f410rb/include/periph_conf.h | 2 +- boards/weact-f411ce/include/periph_conf.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/nucleo-f410rb/include/periph_conf.h b/boards/nucleo-f410rb/include/periph_conf.h index c46a30a4b2..a7c14dddbe 100644 --- a/boards/nucleo-f410rb/include/periph_conf.h +++ b/boards/nucleo-f410rb/include/periph_conf.h @@ -30,7 +30,7 @@ #endif #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_96.h" +#include "f2f4f7/cfg_clock_default_100.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_timer_tim5.h" diff --git a/boards/weact-f411ce/include/periph_conf.h b/boards/weact-f411ce/include/periph_conf.h index 5a2662512b..226c4b8bf1 100644 --- a/boards/weact-f411ce/include/periph_conf.h +++ b/boards/weact-f411ce/include/periph_conf.h @@ -36,7 +36,7 @@ #define CLOCK_HSE MHZ(25) #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_96.h" +#include "f2f4f7/cfg_clock_default_100.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_timer_tim5.h" #include "cfg_usb_otg_fs.h" From 95fb362a5c296aaf0e0af139f36cf981848cc0cb Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 18 Sep 2020 09:55:12 +0200 Subject: [PATCH 4/5] boards/stm32f4xx: use 180MHz default clock header --- boards/f4vi1/include/periph_conf.h | 2 +- boards/msbiot/include/periph_conf.h | 2 +- boards/nucleo-f429zi/include/periph_conf.h | 2 +- boards/pyboard/include/periph_conf.h | 2 +- boards/stm32f429i-disc1/include/periph_conf.h | 2 +- boards/stm32f4discovery/include/periph_conf.h | 2 +- boards/ublox-c030-u201/include/periph_conf.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/boards/f4vi1/include/periph_conf.h b/boards/f4vi1/include/periph_conf.h index a60e04dc01..94f327f0bb 100644 --- a/boards/f4vi1/include/periph_conf.h +++ b/boards/f4vi1/include/periph_conf.h @@ -30,7 +30,7 @@ #define CLOCK_HSE MHZ(16) #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_168.h" +#include "f2f4f7/cfg_clock_default_180.h" #ifdef __cplusplus extern "C" { diff --git a/boards/msbiot/include/periph_conf.h b/boards/msbiot/include/periph_conf.h index 9e9184a7a1..86670a9e50 100644 --- a/boards/msbiot/include/periph_conf.h +++ b/boards/msbiot/include/periph_conf.h @@ -28,7 +28,7 @@ #define CLOCK_HSE MHZ(16) #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_168.h" +#include "f2f4f7/cfg_clock_default_180.h" #ifdef __cplusplus extern "C" { diff --git a/boards/nucleo-f429zi/include/periph_conf.h b/boards/nucleo-f429zi/include/periph_conf.h index 6e07991082..1577dd4d7b 100644 --- a/boards/nucleo-f429zi/include/periph_conf.h +++ b/boards/nucleo-f429zi/include/periph_conf.h @@ -30,7 +30,7 @@ #endif #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_168.h" +#include "f2f4f7/cfg_clock_default_180.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_timer_tim5.h" #include "cfg_usb_otg_fs.h" diff --git a/boards/pyboard/include/periph_conf.h b/boards/pyboard/include/periph_conf.h index aa680818fb..cc0da38bb6 100644 --- a/boards/pyboard/include/periph_conf.h +++ b/boards/pyboard/include/periph_conf.h @@ -35,7 +35,7 @@ #define CLOCK_HSE MHZ(12) #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_168.h" +#include "f2f4f7/cfg_clock_default_180.h" #include "cfg_usb_otg_fs.h" #ifdef __cplusplus diff --git a/boards/stm32f429i-disc1/include/periph_conf.h b/boards/stm32f429i-disc1/include/periph_conf.h index a3fa8f2bc0..091536431f 100644 --- a/boards/stm32f429i-disc1/include/periph_conf.h +++ b/boards/stm32f429i-disc1/include/periph_conf.h @@ -30,7 +30,7 @@ #endif #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_168.h" +#include "f2f4f7/cfg_clock_default_180.h" #include "cfg_timer_tim5.h" #include "cfg_usb_otg_hs_fs.h" diff --git a/boards/stm32f4discovery/include/periph_conf.h b/boards/stm32f4discovery/include/periph_conf.h index 4128622416..1a985fcbb3 100644 --- a/boards/stm32f4discovery/include/periph_conf.h +++ b/boards/stm32f4discovery/include/periph_conf.h @@ -26,7 +26,7 @@ #endif #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_168.h" +#include "f2f4f7/cfg_clock_default_180.h" #include "cfg_usb_otg_fs.h" #ifdef __cplusplus diff --git a/boards/ublox-c030-u201/include/periph_conf.h b/boards/ublox-c030-u201/include/periph_conf.h index 142aa06149..fe582f8b31 100644 --- a/boards/ublox-c030-u201/include/periph_conf.h +++ b/boards/ublox-c030-u201/include/periph_conf.h @@ -33,7 +33,7 @@ #define CLOCK_HSE MHZ(12) #include "periph_cpu.h" -#include "f2f4f7/cfg_clock_default_168.h" +#include "f2f4f7/cfg_clock_default_180.h" #include "cfg_timer_tim5.h" #ifdef __cplusplus From 6b3c11b1519febd9a604359e995986a625d7f094 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 18 Sep 2020 12:51:40 +0200 Subject: [PATCH 5/5] boards/stm32: remove unused default 96 and 168MHz common headers --- .../include/f2f4f7/cfg_clock_default_168.h | 90 ------------------- .../include/f2f4f7/cfg_clock_default_96.h | 90 ------------------- 2 files changed, 180 deletions(-) delete mode 100644 boards/common/stm32/include/f2f4f7/cfg_clock_default_168.h delete mode 100644 boards/common/stm32/include/f2f4f7/cfg_clock_default_96.h diff --git a/boards/common/stm32/include/f2f4f7/cfg_clock_default_168.h b/boards/common/stm32/include/f2f4f7/cfg_clock_default_168.h deleted file mode 100644 index ba843c18c5..0000000000 --- a/boards/common/stm32/include/f2f4f7/cfg_clock_default_168.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2018 Freie Universität Berlin - * 2017 OTA keys S.A. - * 2018-2020 Inria - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup boards_common_stm32 - * @{ - * - * @file - * @brief Default STM32F4 clock configuration for 168MHz boards - * - * @author Hauke Petersen - * @author Vincent Dupont - * @author Alexandre Abadie - */ - -#ifndef F2F4F7_CFG_CLOCK_DEFAULT_168_H -#define F2F4F7_CFG_CLOCK_DEFAULT_168_H - -#include "f2f4f7/cfg_clock_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name Clock PLL settings (180MHz) - * - * The PLL settings provided here can be used for USB on CPU with a max - * frequency of 180MHz. - * @{ - */ -/* The following parameters configure a 168MHz system clock with HSE - (8MHz, 12MHz or 16MHz) or HSI (16MHz) as PLL input clock */ -#ifndef CONFIG_CLOCK_PLL_M -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12)) -#define CONFIG_CLOCK_PLL_M (12) -#else -#define CONFIG_CLOCK_PLL_M (4) -#endif -#endif -#ifndef CONFIG_CLOCK_PLL_N -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12)) -#define CONFIG_CLOCK_PLL_N (336) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) -#define CONFIG_CLOCK_PLL_N (168) -#else -#define CONFIG_CLOCK_PLL_N (84) -#endif -#endif -#ifndef CONFIG_CLOCK_PLL_P -#define CONFIG_CLOCK_PLL_P (2) -#endif -#ifndef CONFIG_CLOCK_PLL_Q -#define CONFIG_CLOCK_PLL_Q (7) -#endif -#ifndef CONFIG_CLOCK_PLL_R -#define CONFIG_CLOCK_PLL_R (0) -#endif -/** @} */ - -/** - * @name Clock bus settings (APB1 and APB2) - */ -#ifndef CONFIG_CLOCK_APB1_DIV -#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */ -#endif -#ifndef CONFIG_CLOCK_APB2_DIV -#define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */ -#endif -/** @} */ - -#ifdef __cplusplus -} -#endif - -#include "f2f4f7/cfg_clock_values.h" - -#if CLOCK_CORECLOCK > MHZ(180) -#error "SYSCLK cannot exceed 180MHz" -#endif - -#endif /* F2F4F7_CFG_CLOCK_DEFAULT_168_H */ -/** @} */ diff --git a/boards/common/stm32/include/f2f4f7/cfg_clock_default_96.h b/boards/common/stm32/include/f2f4f7/cfg_clock_default_96.h deleted file mode 100644 index 8e7cf0a626..0000000000 --- a/boards/common/stm32/include/f2f4f7/cfg_clock_default_96.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2018 Freie Universität Berlin - * 2017 OTA keys S.A. - * 2018-2020 Inria - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup boards_common_stm32 - * @{ - * - * @file - * @brief Default STM32F4 clock configuration for 96MHz boards - * - * @author Hauke Petersen - * @author Vincent Dupont - * @author Alexandre Abadie - */ - -#ifndef F2F4F7_CFG_CLOCK_DEFAULT_96_H -#define F2F4F7_CFG_CLOCK_DEFAULT_96_H - -#include "f2f4f7/cfg_clock_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name Clock PLL settings (100MHz) - * - * The PLL settings provided here can be used for USB on CPU with a max - * frequency of 100MHz. - * @{ - */ -/* The following parameters configure a 96MHz system clock with HSE (8MHz, 16MHz or - 25MHz) or HSI (16MHz) as PLL input clock */ -#ifndef CONFIG_CLOCK_PLL_M -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) -#define CONFIG_CLOCK_PLL_M (25) -#else -#define CONFIG_CLOCK_PLL_M (4) -#endif -#endif -#ifndef CONFIG_CLOCK_PLL_N -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) -#define CONFIG_CLOCK_PLL_N (192) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) -#define CONFIG_CLOCK_PLL_N (96) -#else -#define CONFIG_CLOCK_PLL_N (48) -#endif -#endif -#ifndef CONFIG_CLOCK_PLL_P -#define CONFIG_CLOCK_PLL_P (2) -#endif -#ifndef CONFIG_CLOCK_PLL_Q -#define CONFIG_CLOCK_PLL_Q (4) -#endif -#ifndef CONFIG_CLOCK_PLL_R -#define CONFIG_CLOCK_PLL_R (4) -#endif -/** @} */ - -/** - * @name Clock bus settings (APB1 and APB2) - */ -#ifndef CONFIG_CLOCK_APB1_DIV -#define CONFIG_CLOCK_APB1_DIV (2) /* max 50MHz */ -#endif -#ifndef CONFIG_CLOCK_APB2_DIV -#define CONFIG_CLOCK_APB2_DIV (1) /* max 100MHz */ -#endif -/** @} */ - -#ifdef __cplusplus -} -#endif - -#include "f2f4f7/cfg_clock_values.h" - -#if CLOCK_CORECLOCK > MHZ(100) -#error "SYSCLK cannot exceed 100MHz" -#endif - -#endif /* F2F4F7_CFG_CLOCK_DEFAULT_96_H */ -/** @} */