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Merge #19170 #19190 #19191

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19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht

### Contribution description

This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`.

**[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards.

This PR depends on PR #19166 and includes this PR for the moment.

### Testing procedure

t.b.d.

### Issues/PRs references

Depends on PR #19166

19190: pkg/wolfssl: Fix memory leaks in wolfSSL sock_tls r=benpicco a=Flole998

When sk->ssl is NULL it doesn't need to be free()d, otherwise it may be free()d

19191: Fix SX126X-STM32WL module in Kconfig r=MrKevinWeiss a=MrKevinWeiss

### Contribution description

Master is broken due to kconfig mismatch for the `nucleo-wl55jc`.  The radio was just not declared.

This fixes the board and cleans up some of the SX126X kconfig.


### Testing procedure

Murdock should pass

### Issues/PRs references



Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Flole998 <Flole998@users.noreply.github.com>
Co-authored-by: MrKevinWeiss <weiss.kevin604@gmail.com>
This commit is contained in:
bors[bot] 2023-01-24 12:08:46 +00:00 committed by GitHub
commit d1072c287d
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35 changed files with 601 additions and 98 deletions
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20
boards/common/gd32v/Kconfig Normal file
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@ -0,0 +1,20 @@
# Copyright (c) 2023 Gunar Schorcht
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config BOARD_HAS_HXTAL
bool
help
Indicates that the board is providing an HXTAL oscillator
config BOARD_HAS_LXTAL
bool
help
Indicates that the board is providing an LXTAL oscillator
config CLOCK_HXTAL
int
default 8000000

0
boards/common/gd32v/Makefile.dep Normal file
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1
boards/common/gd32v/Makefile.features Normal file
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@ -0,0 +1 @@
CPU = gd32v

14
boards/common/gd32v/Makefile.include Normal file
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@ -0,0 +1,14 @@
# include this module into the build
INCLUDES += -I$(RIOTBOARD)/common/gd32v/include
# configure the serial interface
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
# configure the flasher
PROGRAMMER ?= openocd
OPENOCD_CONFIG ?= $(RIOTBOARD)/common/gd32v/dist/openocd.cfg
OPENOCD_DEBUG_ADAPTER ?= ftdi
OPENOCD_FTDI_ADAPTER ?= openocd-usb
OPENOCD_TRANSPORT = jtag
OPENOCD_RESET_USE_CONNECT_ASSERT_SRST = 1

0
boards/seeedstudio-gd32/dist/openocd.cfg → boards/common/gd32v/dist/openocd.cfg vendored
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17
boards/common/gd32v/doc.txt Normal file
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@ -0,0 +1,17 @@
/*
* Copyright (C) 2023 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_common_gd32v GD32V Common Configuration
* @ingroup boards_common
* @brief Definitions and configurations that are common for
* all GD32VF103 boards.
*
* All boards using a MCU from the GD32VF103 family share some parts of their
* configuration.
*/

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boards/common/gd32v/include/cfg_timer_default.h Normal file
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@ -0,0 +1,88 @@
/*
* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
* 2023 Gunar Schorcht <gunar@schorcht.net>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_gd32v
* @{
*
* @file
* @brief Default timer configuration for GD32VF103 boards
*
* @author Koen Zandberg <koen@bergzand.net>
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef CFG_TIMER_DEFAULT_H
#define CFG_TIMER_DEFAULT_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Timer configuration
*
* All GD32VF103xx variants have at least one advanced timer TIMER0 and two
* general timers TIMER1 and TIMER2. GD32VF10x8 and GD32VF10xB have two
* additional general timers TIMER3 and TIMER4.
*
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIMER1,
.max = 0x0000ffff,
.rcu_mask = RCU_APB1EN_TIMER1EN_Msk,
.bus = APB1,
.irqn = TIMER1_IRQn
},
{
.dev = TIMER2,
.max = 0x0000ffff,
.rcu_mask = RCU_APB1EN_TIMER2EN_Msk,
.bus = APB1,
.irqn = TIMER2_IRQn
},
#if defined(CPU_MODEL_GD32VF103C8T6) || defined(CPU_MODEL_GD32VF103CBT6) || \
defined(CPU_MODEL_GD32VF103R8T6) || defined(CPU_MODEL_GD32VF103RBT6) || \
defined(CPU_MODEL_GD32VF103T8U6) || defined(CPU_MODEL_GD32VF103TBU6) || \
defined(CPU_MODEL_GD32VF103V8T6) || defined(CPU_MODEL_GD32VF103VBT6)
{
.dev = TIMER3,
.max = 0x0000ffff,
.rcu_mask = RCU_APB1EN_TIMER3EN_Msk,
.bus = APB1,
.irqn = TIMER3_IRQn
},
{
.dev = TIMER4,
.max = 0x0000ffff,
.rcu_mask = RCU_APB1EN_TIMER4EN_Msk,
.bus = APB1,
.irqn = TIMER4_IRQn
}
#endif
};
#define TIMER_0_IRQN TIMER1_IRQn
#define TIMER_1_IRQN TIMER2_IRQn
#define TIMER_2_IRQN TIMER3_IRQn
#define TIMER_3_IRQN TIMER4_IRQn
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CFG_TIMER_DEFAULT_H */
/** @} */

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boards/common/gd32v/include/cfg_uart_default.h Normal file
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@ -0,0 +1,55 @@
/*
* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
* 2023 Gunar Schorcht <gunar@schorcht.net>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_gd32v
* @{
*
* @file
* @brief Default UART configuration for GD32VF103 boards
*
* @author Koen Zandberg <koen@bergzand.net>
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef CFG_UART_DEFAULT_H
#define CFG_UART_DEFAULT_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART0,
.rcu_mask = RCU_APB2EN_USART0EN_Msk,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.bus = APB2,
.irqn = USART0_IRQn,
},
};
#define UART_0_IRQN USART0_IRQn
#define UART_NUMOF ARRAY_SIZE(uart_config)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CFG_UART_DEFAULT_H */
/** @} */

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boards/common/gd32v/include/periph_common_conf.h Normal file
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/*
* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
* 2023 Gunar Schorcht <gunar@schorcht.net>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_gd32v
* @{
*
* @file
* @brief Common peripheral configuration for GD32VF103 boards
*
* @author Koen Zandberg <koen@bergzand.net>
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef PERIPH_COMMON_CONF_H
#define PERIPH_COMMON_CONF_H
#include "macros/units.h"
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CLOCK_CORECLOCK MHZ(108) /**< CPU clock frequency in Hz */
#define CLOCK_AHB CLOCK_CORECLOCK /**< Equal to the CPU clock */
#define CLOCK_APB1 CLOCK_AHB/2 /**< Half AHB clock */
#define CLOCK_APB2 CLOCK_AHB /**< Equal to the AHB clock */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_COMMON_CONF_H */
/** @} */

3
boards/nucleo-wl55jc/Kconfig
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@ -25,6 +25,9 @@ config BOARD_NUCLEO_WL55JC
# Put other features for this board (in alphabetical order)
select HAS_ARDUINO
select HAS_RIOTBOOT
select HAS_PERIPH_GPIO_IRQ
select HAVE_SX126X_STM32WL
select HAVE_SX126X_RF_SWITCH
select MODULE_PERIPH_LPUART if MODULE_STDIO_UART && HAS_PERIPH_LPUART

17
boards/seeedstudio-gd32/Kconfig
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@ -12,21 +12,10 @@ config BOARD_SEEEDSTUDIO_GD32
bool
default y
select CPU_MODEL_GD32VF103VBT6
select HAS_PERIPH_UART
select BOARD_HAS_HXTAL
select BOARD_HAS_LXTAL
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAVE_SAUL_GPIO
config BOARD_HAS_HXTAL
bool
help
Indicates that the board is providing an HXTAL oscillator
config BOARD_HAS_LXTAL
bool
help
Indicates that the board is providing an LXTAL oscillator
config CLOCK_HXTAL
int
default 8000000
source "$(RIOTBOARD)/common/gd32v/Kconfig"

2
boards/seeedstudio-gd32/Makefile.dep
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@ -1,3 +1,5 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
include $(RIOTBOARD)/common/gd32v/Makefile.dep

3
boards/seeedstudio-gd32/Makefile.features
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@ -1,6 +1,7 @@
CPU = gd32v
CPU_MODEL = gd32vf103vbt6
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
include $(RIOTBOARD)/common/gd32v/Makefile.features

11
boards/seeedstudio-gd32/Makefile.include
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@ -1,10 +1 @@
# configure the serial interface
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
# configure the flasher
PROGRAMMER ?= openocd
OPENOCD_DEBUG_ADAPTER ?= ftdi
OPENOCD_FTDI_ADAPTER ?= openocd-usb
OPENOCD_TRANSPORT = jtag
OPENOCD_RESET_USE_CONNECT_ASSERT_SRST = 1
include $(RIOTBOARD)/common/gd32v/Makefile.include

10
boards/seeedstudio-gd32/include/board.h
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@ -25,8 +25,6 @@
extern "C" {
#endif
#include "macros/units.h"
/**
* @name Button pin definitions
* @{
@ -67,14 +65,6 @@ extern "C" {
#define LED_BLUE_PIN LED2_PIN /**< LED2 is blue */
/** @} */
/**
* @name Xtimer configuration
* @{
*/
#define XTIMER_HZ MHZ(1)
#define XTIMER_WIDTH (16)
/** @} */
#ifdef __cplusplus
}
#endif

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boards/seeedstudio-gd32/include/periph_conf.h
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@ -19,15 +19,14 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "macros/units.h"
#include "periph_cpu.h"
#include "periph_common_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "cfg_timer_default.h"
#include "cfg_uart_default.h"
#ifndef CONFIG_BOARD_HAS_HXTAL
#define CONFIG_BOARD_HAS_HXTAL 1 /**< This board provides an high frequency oscillator */
#define CONFIG_BOARD_HAS_HXTAL 1 /**< The board provides a high frequency oscillator. */
#endif
#ifndef CONFIG_BOARD_HAS_LXTAL
@ -38,54 +37,9 @@ extern "C" {
#define CONFIG_CLOCK_HXTAL MHZ(8) /**< HXTAL frequency */
#endif
#define CLOCK_CORECLOCK MHZ(108) /**< CPU clock frequency in Hz */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIMER2,
.max = 0x0000ffff,
.rcu_mask = RCU_APB1EN_TIMER2EN_Msk,
.bus = APB1,
.irqn = TIMER2_IRQn
},
{
.dev = TIMER3,
.max = 0x0000ffff,
.rcu_mask = RCU_APB1EN_TIMER3EN_Msk,
.bus = APB1,
.irqn = TIMER3_IRQn
}
};
#define TIMER_0_IRQN TIMER2_IRQn
#define TIMER_1_IRQN TIMER3_IRQn
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART0,
.rcu_mask = RCU_APB2EN_USART0EN_Msk,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.bus = APB2,
.irqn = USART0_IRQn,
},
};
#define UART_0_IRQN USART0_IRQn
#define UART_NUMOF ARRAY_SIZE(uart_config)
/** @} */
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}

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boards/sipeed-longan-nano/Kconfig Normal file
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@ -0,0 +1,21 @@
# Copyright (c) 2023 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config BOARD
default "sipeed-longan-nano" if BOARD_SIPEED_LONGAN_NANO
config BOARD_SIPEED_LONGAN_NANO
bool
default y
select CPU_MODEL_GD32VF103CBT6
select BOARD_HAS_HXTAL
select BOARD_HAS_LXTAL
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAVE_SAUL_GPIO
source "$(RIOTBOARD)/common/gd32v/Kconfig"

3
boards/sipeed-longan-nano/Makefile Normal file
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@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

5
boards/sipeed-longan-nano/Makefile.dep Normal file
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@ -0,0 +1,5 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
include $(RIOTBOARD)/common/gd32v/Makefile.dep

7
boards/sipeed-longan-nano/Makefile.features Normal file
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@ -0,0 +1,7 @@
CPU_MODEL = gd32vf103cbt6
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
include $(RIOTBOARD)/common/gd32v/Makefile.features

1
boards/sipeed-longan-nano/Makefile.include Normal file
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@ -0,0 +1 @@
include $(RIOTBOARD)/common/gd32v/Makefile.include

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boards/sipeed-longan-nano/doc.txt Normal file
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/**
@defgroup boards_sipeed_longan_nano Sipeed Longan Nano board
@ingroup boards
@brief Support for the Sipeed Longan Nano board
@author Gunar Schorcht <gunar@schorcht.net>
## Overview
The [Sipeed Longan Nano](https://longan.sipeed.com/en) is a
development board for the GigaDevice GD32VF103CBT6 MCU with the following
on-board components:
- GD32VF103CBT6 RISC-V MCU @108MHz
- USB Type C
- TF card slot
- 3 user LEDs
@image html "https://media-cdn.seeedstudio.com/media/catalog/product/cache/7f7f32ef807b8c2c2215b49801c56084/1/1/114992425_1.jpg" "Sipeed Longan Nano" width=600
## Hardware:
| MCU | GD32VF103CBT6 | Supported |
|:----------- |:-------------------------------------- | --------- |
| Family | RISC-V with ECLIC | |
| Vendor | GigaDevice | |
| RAM | 32 kByte | |
| Flash | 128 KByte | |
| Frequency | 108 MHz | |
| Power Modes | 3 (Sleep, Deep Sleep, Standby) | no |
| GPIOs | 37 | yes |
| Timers | 5 x 16-bit timer | yes |
| RTC | 1 x 32-bit counter, 20-bit prescaler | yes |
| WDT | 2 x 12-bit counter, 3-bit prescaler | yes |
| ADC | 2 x 12-bit units, 16 channels, 1 Msps | no |
| DAC | 2 x 12-bit channel | no |
| UART | - | yes |
| USART | 3 | yes |
| SPI | 3 | no |
| I2C | 2 x Fast Mode 400 kHz | no |
| I2S | 2 | no |
| CAN | 2 x CAN 2.0B with up to 1 Mbps | no |
| PWM | 6 Channels | no |
| USB | 1 x USB FS OTG | no |
| Vcc | 3.0V - 3.6V | |
| Datasheet | [Datasheet](https://gd32mcu.com/data/documents/datasheet/GD32VF103_Datasheet_Rev1.6.pdf) | |
| Reference Manual | [Reference Manual](https://gd32mcu.com/download/down/document_id/222/path_type/1) | |
| Board Manual | [Board Manual](https://longan.sipeed.com/en/) | |
| Board Schematic | [Board Schematic](http://dl.sipeed.com/fileList/LONGAN/Nano/HDK/Longan%20Nano%203302/2_Schematic/Longan_nano_3302_Schematic.pdf) | |
## Pin Layout / Configuration
The general pin layout is shown below.
@image html "https://longan.sipeed.com/assets/longan_nano_pinout_v1.1.0_w5676_h4000_large.png" "Sipeed Longan Nano Pinout" width=800
The following table shows the connection of the on-board components with the
MCU pins and their configuration in RIOT.
| MCU Pin | MCU Peripheral | RIOT Peripheral | Board Function |
|:--------|:---------------|:--------------------|:----------------------|
| PA9 | USART0 TX | UART_DEV(0) TX | UART TX |
| PA10 | USART0 RX | UART_DEV(0) RX | UART RX |
| PB0 | | | LED1 |
| PB1 | | | LED2 |
| PB5 | | | LED0 |
## Flash the board
The board is flashed via a JTAG interface with OpenOCD (at least [release version 0.12.0]
(https://github.com/openocd-org/openocd/tree/9ea7f3d647c8ecf6b0f1424002dfc3f4504a162c)).
By default, an FTDI adapter according to the configuration defined in
[`interface/openocd-usb.cfg`]
(https://github.com/openocd-org/openocd/blob/9ea7f3d647c8ecf6b0f1424002dfc3f4504a162c/tcl/interface/ftdi/openocd-usb.cfg)
is assumed.
```
BOARD=seeedstudio-gd32 make -C examples/hello-world flash
```
To use an FTDI adapter with a different configuration, the configuration can be
defined using the variable `OPENOCD_FTDI_ADAPTER`, for example:
```
OPENOCD_FTDI_ADAPTER=tigar BOARD=seeedstudio-gd32 make -C examples/hello-world flash
```
If another adapter is used, it can be specified using variable
`OPENOCD_DEBUG_ADAPTER`, for example for a Segger J-Link adapter:
```
OPENOCD_DEBUG_ADAPTER=jlink BOARD=seeedstudio-gd32 make -C examples/hello-world flash
```
## Accessing STDIO via UART
The `stdio` is directly accessible through the first UART interface. If an
external USB-to-UART interface is used, this interface is mapped to
`/dev/ttyUSB<n>` on a Linux host, where `<n>` is the index of the UART
interface, which is 0 by default.
Use the `term` target to connect to the board using `/dev/ttyUSB0`:
```
BOARD=seeedstudio-gd32 make -C examples/hello-world term
```
If the UART interface index of board's USB to UART bridge is not 0, use
the following command to connect:
```
BOARD=seeedstudio-gd32 make -C examples/hello-world term PORT=/dev/ttyUSB<n>
```
*/

59
boards/sipeed-longan-nano/include/board.h Normal file
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@ -0,0 +1,59 @@
/*
* Copyright (C) 2023 Gunar Schorcht <gunar@schorcht.net>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_sipeed_longan_nano
* @{
*
* @file
* @brief Board specific definitions for the Sipeed Longan Nano board
*
* @author Koen Zandberg <koen@bergzand.net>
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef BOARD_H
#define BOARD_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name LED (on-board) configuration
* @{
*/
#define LED0_PIN GPIO_PIN(PORT_C, 13)
#define LED0_MASK (1 << 13)
#define LED0_ON (GPIOC->BC = LED0_MASK)
#define LED0_OFF (GPIOC->BOP = LED0_MASK)
#define LED0_TOGGLE (GPIOC->OCTL ^= LED0_MASK)
#define LED1_PIN GPIO_PIN(PORT_A, 1)
#define LED1_MASK (1 << 1)
#define LED1_ON (GPIOA->BC = LED1_MASK)
#define LED1_OFF (GPIOA->BOP = LED1_MASK)
#define LED1_TOGGLE (GPIOA->OCTL ^= LED1_MASK)
#define LED2_PIN GPIO_PIN(PORT_A, 2)
#define LED2_MASK (1 << 2)
#define LED2_ON (GPIOA->BC = LED2_MASK)
#define LED2_OFF (GPIOA->BOP = LED2_MASK)
#define LED2_TOGGLE (GPIOA->OCTL ^= LED2_MASK)
#define LED_RED_PIN LED0_PIN /**< LED0 is red */
#define LED_GREEN_PIN LED1_PIN /**< LED1 is green */
#define LED_BLUE_PIN LED2_PIN /**< LED2 is blue */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

59
boards/sipeed-longan-nano/include/gpio_params.h Normal file
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@ -0,0 +1,59 @@
/*
* Copyright (C) 2020 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_sipeed_longan_nano
* @{
*
* @file
* @brief Configuration of SAUL mapped GPIO pins
*
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LED/Button SAUL configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LED RED",
.pin = LED0_PIN,
.mode = GPIO_OUT,
.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR),
},
{
.name = "LED GREEN",
.pin = LED1_PIN,
.mode = GPIO_OUT,
.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR),
},
{
.name = "LED BLUE",
.pin = LED2_PIN,
.mode = GPIO_OUT,
.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR),
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

49
boards/sipeed-longan-nano/include/periph_conf.h Normal file
View File

@ -0,0 +1,49 @@
/*
* Copyright (C) 2023 Gunar Schorcht <gunar@schorcht.net>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_sipeed_longan_nano
* @{
*
* @file
* @brief Board specific definitions for the SeeedStudio GD32 RISC-V board
*
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "periph_common_conf.h"
#include "cfg_timer_default.h"
#include "cfg_uart_default.h"
#ifndef CONFIG_BOARD_HAS_HXTAL
#define CONFIG_BOARD_HAS_HXTAL 1 /**< The board provides a high frequency oscillator. */
#endif
#ifndef CONFIG_BOARD_HAS_LXTAL
#define CONFIG_BOARD_HAS_LXTAL 1 /**< The board provides a low frequency oscillator. */
#endif
#ifndef CONFIG_CLOCK_HXTAL
#define CONFIG_CLOCK_HXTAL MHZ(8) /**< HXTAL frequency */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

7
cpu/gd32v/Kconfig
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@ -23,6 +23,10 @@ config CPU_FAM_GD32V
select MODULE_PERIPH_CLIC if TEST_KCONFIG
select MODULE_PERIPH_WDT if MODULE_PERIPH_PM && HAS_PERIPH_WDT
config CPU_MODEL_GD32VF103CBT6
bool
select CPU_FAM_GD32V
config CPU_MODEL_GD32VF103VBT6
bool
select CPU_FAM_GD32V
@ -36,6 +40,9 @@ config HAS_CPU_GD32V
config CPU_FAM
default "gd32v" if CPU_FAM_GD32V
config CPU_MODEL
default "gd32vf103cbt6" if CPU_MODEL_GD32VF103CBT6
config CPU_MODEL
default "gd32vf103vbt6" if CPU_MODEL_GD32VF103VBT6

2
cpu/gd32v/Makefile.include
View File

@ -6,4 +6,6 @@ ROM_LEN ?= 128K
LINKER_SCRIPT ?= riscv.ld
CFLAGS += -DCPU_MODEL_$(call uppercase_and_underscore,$(CPU_MODEL))
include $(RIOTCPU)/riscv_common/Makefile.include

4
cpu/gd32v/clock.c
View File

@ -21,10 +21,6 @@
#include "cpu.h"
#include "periph_conf.h"
#define CLOCK_AHB CLOCK_CORECLOCK /* Equal to the CPU clock */
#define CLOCK_APB1 CLOCK_AHB/2 /* Half AHB clock */
#define CLOCK_APB2 CLOCK_AHB /* Equal to the AHB clock */
#define CLOCK_AHB_DIV 0 /* Max speed at 108 MHz */
#define CLOCK_APB1_DIV (0x04 | 0) /* Max speed at 54 MHz */
#define CLOCK_APB2_DIV (0x0 | 0) /* Max speed at 108 MHz */

6
dist/tools/doccheck/generic_exclude_patterns vendored
View File

@ -41,9 +41,15 @@ warning: Member PULSE_COUNTER_SAUL_INFO \(macro definition\) of
warning: Member SHT1X_PARAMS \(macro definition\) of
warning: Member SHT1X_PARAM_[A-Z0-9_]* \(macro definition\) of
warning: Member SHT1X_SAULINFO \(macro definition\) of
warning: Member TIMER_[0-9]_IRQN \(macro definition\) of
warning: Member TIMER_NUMOF \(macro definition\) of
warning: Member timer_config\[\] \(variable\) of
warning: Member TMP00X_PARAM_ADDR \(macro definition\) of
warning: Member TMP00X_PARAM_I2C \(macro definition\) of
warning: Member TMP00X_PARAM_RATE \(macro definition\) of
warning: Member UART_[0-9]_IRQN \(macro definition\) of
warning: Member UART_NUMOF \(macro definition\) of
warning: Member uart_config\[\] \(variable\) of
warning: Member XTIMER_BACKOFF \(macro definition\) of
warning: Member XTIMER_CHAN \(macro definition\) of
warning: Member XTIMER_DEV \(macro definition\) of

22
drivers/sx126x/Kconfig
View File

@ -16,12 +16,14 @@ menuconfig MODULE_SX126X
select MODULE_IOLIST
select MODULE_NETDEV_LEGACY_API
select MODULE_PERIPH_GPIO
select MODULE_PERIPH_GPIO_IRQ
select MODULE_PERIPH_SPI
select PACKAGE_DRIVER_SX126X
if MODULE_SX126X
choice
bool "Radio variant"
depends on MODULE_SX126X
default MODULE_SX1261 if HAVE_SX1261
default MODULE_SX1262 if HAVE_SX1262
default MODULE_SX1268 if HAVE_SX1268
@ -30,25 +32,30 @@ choice
config MODULE_SX1261
bool "SX1261"
select MODULE_PERIPH_GPIO_IRQ
config MODULE_SX1262
bool "SX1262"
select MODULE_PERIPH_GPIO_IRQ
config MODULE_SX1268
bool "SX1268"
select MODULE_PERIPH_GPIO_IRQ
config MODULE_LLCC68
bool "LLCC68"
select MODULE_PERIPH_GPIO_IRQ
config MODULE_SX126X_STM32WL
bool "SX126X-STM32WL"
endchoice
config MODULE_SX126X_RF_SWITCH
bool "Enable RF switch support"
default y if HAVE_SX126X_RF_SWITCH
depends on MODULE_SX126X
depends on HAS_PERIPH_GPIO
select MODULE_PERIPH_GPIO
endif # MODULE_SX126X
config HAVE_SX1261
bool
select HAVE_SX126X
@ -83,3 +90,8 @@ config HAVE_SX126X
bool
help
Indicates that an sx126x transceiver is present.
config HAVE_SX126X_RF_SWITCH
bool
help
Indicates that an sx126x rf switch pin is wired.

1
examples/dtls-wolfssl/Makefile.ci
View File

@ -32,6 +32,7 @@ BOARD_INSUFFICIENT_MEMORY := \
saml10-xpro \
saml11-xpro \
seeedstudio-gd32 \
sipeed-longan-nano \
slstk3400a \
spark-core \
stk3200 \

1
examples/javascript/Makefile.ci
View File

@ -47,6 +47,7 @@ BOARD_INSUFFICIENT_MEMORY := \
saml10-xpro \
saml11-xpro \
seeedstudio-gd32 \
sipeed-longan-nano \
slstk3400a \
spark-core \
stk3200 \

2
pkg/wolfssl/sock_tls/sock_tls.c
View File

@ -65,7 +65,7 @@ static int tls_session_create(sock_tls_t *sk)
static void tls_session_destroy(sock_tls_t *sk)
{
if (!sk || sk->ssl)
if (!sk || !sk->ssl)
return;
wolfSSL_free(sk->ssl);
}

1
tests/pkg_utensor/Makefile.ci
View File

@ -37,6 +37,7 @@ BOARD_INSUFFICIENT_MEMORY := \
saml10-xpro \
saml11-xpro \
seeedstudio-gd32 \
sipeed-longan-nano \
slstk3400a \
spark-core \
stk3200 \

1
tests/unittests/Makefile.ci
View File

@ -97,6 +97,7 @@ BOARD_INSUFFICIENT_MEMORY := \
samr30-xpro \
samr34-xpro \
seeedstudio-gd32 \
sipeed-longan-nano \
sensebox_samd21 \
slstk3400a \
slstk3401a \