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nucleo-f334: add SPI pin defines
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@ -1,4 +1,5 @@
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += cpp
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FEATURES_MCU_GROUP = cortex_m4
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@ -14,6 +14,7 @@
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* @brief Peripheral MCU configuration for the nucleo-f334 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Kaspar Schleiser <kaspar.schleiser@fu-berlin.de>
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*/
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#ifndef __PERIPH_CONF_H
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@ -78,6 +79,36 @@ extern "C" {
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#define UART_0_AF 7
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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#define SPI_0_EN 1
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#define SPI_IRQ_PRIO 1
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/* SPI 0 device config */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_IRQ_HANDLER isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_SCK_PORT GPIOA
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#define SPI_0_SCK_PIN 5
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#define SPI_0_SCK_AF 5
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#define SPI_0_SCK_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_MISO_PORT GPIOA
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#define SPI_0_MISO_PIN 6
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#define SPI_0_MISO_AF 5
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#define SPI_0_MISO_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_MOSI_PORT GPIOA
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#define SPI_0_MOSI_PIN 7
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#define SPI_0_MOSI_AF 5
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#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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