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cpu/sam0_common/gpio: use explicit GCLK names

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For consistency, use named GCLKs.

 - `SAM0_GCLK_32KHZ` will always be 2 for samd21
 - `SAM0_GCLK_MAIN` will always be 0

So no change in functionality, just makes the code easier to understand.
This commit is contained in:
Benjamin Valentin 2020-02-21 14:25:43 +01:00
parent ea24d30e7a
commit b77afadb49
1 changed files with 4 additions and 4 deletions
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8
cpu/sam0_common/periph/gpio.c
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@ -186,14 +186,14 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
PM->APBAMASK.reg |= PM_APBAMASK_EIC;
/* SAMD21 used GCLK2 which is supplied by either the ultra low power
internal or external 32 kHz */
GCLK->CLKCTRL.reg = (EIC_GCLK_ID |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK2);
GCLK->CLKCTRL.reg = EIC_GCLK_ID
| GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN(SAM0_GCLK_32KHZ);
while (GCLK->STATUS.bit.SYNCBUSY) {}
#else /* CPU_FAM_SAML21 */
/* enable clocks for the EIC module */
MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0;
GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(SAM0_GCLK_MAIN);
/* disable the EIC module*/
_EIC->CTRLA.reg = 0;
while (_EIC->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) {}