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cpu/esp32: use usbdev_synopsys_dwc2 driver as periph_usbdev

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This commit is contained in:
Gunar Schorcht 2022-09-24 23:36:15 +02:00
parent 641e343f7d
commit 9d5a7ac083
8 changed files with 141 additions and 8 deletions
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1
cpu/esp32/Kconfig.esp32s2
View File

@ -25,6 +25,7 @@ config CPU_FAM_ESP32S2
select MODULE_PS if MODULE_SHELL
select MODULE_PTHREAD if MODULE_CPP
select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC
select MODULE_USBDEV_SYNOPSYS_DWC2 if HAS_PERIPH_USBDEV && MODULE_PERIPH_USBDEV
imply MODULE_NEWLIB_NANO
config CPU_FAM

1
cpu/esp32/Kconfig.esp32s3
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@ -31,6 +31,7 @@ config CPU_FAM_ESP32S3
select MODULE_PS if MODULE_SHELL
select MODULE_PTHREAD if MODULE_CPP
select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC
select MODULE_USBDEV_SYNOPSYS_DWC2 if HAS_PERIPH_USBDEV && MODULE_PERIPH_USBDEV
imply MODULE_NEWLIB_NANO
config CPU_FAM

1
cpu/esp32/Makefile.dep
View File

@ -159,6 +159,7 @@ endif
ifneq (,$(filter periph_usbdev,$(USEMODULE)))
USEMODULE += esp_idf_usb
USEMODULE += usbdev_synopsys_dwc2
USEMODULE += ztimer_msec
endif

16
cpu/esp32/include/periph_cpu.h
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@ -811,7 +811,21 @@ typedef struct {
/**
* @brief Maximum number of UART interfaces
*/
#define UART_NUMOF_MAX (SOC_UART_NUM)
#define UART_NUMOF_MAX (SOC_UART_NUM)
/** @} */
/**
* @name USB device configuration
* @{
*
* ESP32x SoCs integrate depending on the specific ESP32x SoC variant (family) an USB OTG FS controller based on the Synopsys DWC2 IP core.
*/
#include "usbdev_synopsys_dwc2.h"
/**
* @brief Maximum number of USB OTG FS interfaces
*/
#define USBDEV_NUMOF_MAX (SOC_USB_PERIPH_NUM)
/** @} */
#ifdef __cplusplus

62
cpu/esp32/include/periph_cpu_esp32s2.h
View File

@ -212,9 +212,69 @@ extern "C" {
* UART_DEV(2) | RxD | - |`UART2_RXD` | optional, can be overridden (no direct I/O)
*
* </center><br>
*
*/
/**
* @name USB device configuration
*
* ESP32x SoCs have:
* - a bidirectional control endpoint EP0 IN and EP0 OUT
* - six additional endpoints EP1 .. EP6 that can be configured as IN our OUT
* - a maximum of five IN endpoints concurrently active at any time (including EP0 IN)
* - all OUT endpoints share a single RX FIFO
* - each IN endpoint has a dedicated TX FIFO
*
* To avoid a lot of special case handling, the maximum number of IN an OUT
* endpoints including the control endpoint EP0 is 5.
*
* @{
*/
/**
* @brief Enable the USB OTG FS peripheral
*
* At the moment, only FS is supported on ESP32x SoCs.
*/
#define DWC2_USB_OTG_FS_ENABLED 1
/**
* @brief Number of USB OTG FS IN endpoints including the control endpoint
*/
#define DWC2_USB_OTG_FS_NUM_EP (5)
/**
* @brief Number of USB OTG HS OUT endpoints including the control endpoint
*/
#define DWC2_USB_OTG_HS_NUM_EP (5)
/**
* @brief Size of the FIFO shared by all USB OTG FS OUT endpoints
*/
#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE
#define DWC2_USB_OTG_FS_RX_FIFO_SIZE (128U)
#endif
/**
* @brief Size of the FIFO shared by all USB OTG HS OUT endpoints
*/
#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE
#define DWC2_USB_OTG_HS_RX_FIFO_SIZE (512U)
#endif
/**
* @brief Total size of the FIFO
*/
#ifndef DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE
#define DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE (1024U)
#endif
/**
* @brief Buffers have to be word aligned for DMA
*/
#define USBDEV_CPU_DMA_ALIGNMENT (4)
/** @} */
#ifdef __cplusplus
}
#endif

60
cpu/esp32/include/periph_cpu_esp32s3.h
View File

@ -215,6 +215,66 @@ extern "C" {
*
*/
/**
* @name USB device configuration
*
* ESP32x SoCs have:
* - a bidirectional control endpoint EP0 IN and EP0 OUT
* - six additional endpoints EP1 .. EP6 that can be configured as IN our OUT
* - a maximum of five IN endpoints concurrently active at any time (including EP0 IN)
* - all OUT endpoints share a single RX FIFO
* - each IN endpoint has a dedicated TX FIFO
*
* To avoid a lot of special case handling, the maximum number of IN an OUT
* endpoints including the control endpoint EP0 is 5.
*
* @{
*/
/**
* @brief Enable the USB OTG FS peripheral
*
* At the moment, only FS is supported on ESP32x SoCs.
*/
#define DWC2_USB_OTG_FS_ENABLED 1
/**
* @brief Number of USB OTG FS IN endpoints including the control endpoint
*/
#define DWC2_USB_OTG_FS_NUM_EP (5)
/**
* @brief Number of USB OTG HS OUT endpoints including the control endpoint
*/
#define DWC2_USB_OTG_HS_NUM_EP (5)
/**
* @brief Size of the FIFO shared by all USB OTG FS OUT endpoints
*/
#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE
#define DWC2_USB_OTG_FS_RX_FIFO_SIZE (128U)
#endif
/**
* @brief Size of the FIFO shared by all USB OTG HS OUT endpoints
*/
#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE
#define DWC2_USB_OTG_HS_RX_FIFO_SIZE (512U)
#endif
/**
* @brief Total size of the FIFO
*/
#ifndef DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE
#define DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE (1024U)
#endif
/**
* @brief Buffers have to be word aligned for DMA
*/
#define USBDEV_CPU_DMA_ALIGNMENT (4)
/** @} */
#ifdef __cplusplus
}
#endif

4
cpu/esp32/include/sdkconfig_esp32s2.h
View File

@ -105,9 +105,7 @@ extern "C" {
/**
* ESP32-S2 specific PHY configuration
*/
#define CONFIG_USB_OTG_SUPPORTED 0
#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256
#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1
#define CONFIG_USB_OTG_SUPPORTED 1
/**
* ESP32-S2 specific SPI RAM configuration

4
cpu/esp32/include/sdkconfig_esp32s3.h
View File

@ -110,9 +110,7 @@ extern "C" {
* ESP32-S3 specific PHY configuration
*/
#define CONFIG_ESP_PHY_ENABLE_USB 1
#define CONFIG_USB_OTG_SUPPORTED 0
#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256
#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1
#define CONFIG_USB_OTG_SUPPORTED 1
/**
* ESP32-S3 specific SPI RAM configuration