From 9d5a7ac0839d766657e8a28c4d782d0b0f78105f Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Sat, 24 Sep 2022 23:36:15 +0200 Subject: [PATCH] cpu/esp32: use usbdev_synopsys_dwc2 driver as periph_usbdev --- cpu/esp32/Kconfig.esp32s2 | 1 + cpu/esp32/Kconfig.esp32s3 | 1 + cpu/esp32/Makefile.dep | 1 + cpu/esp32/include/periph_cpu.h | 16 ++++++- cpu/esp32/include/periph_cpu_esp32s2.h | 62 +++++++++++++++++++++++++- cpu/esp32/include/periph_cpu_esp32s3.h | 60 +++++++++++++++++++++++++ cpu/esp32/include/sdkconfig_esp32s2.h | 4 +- cpu/esp32/include/sdkconfig_esp32s3.h | 4 +- 8 files changed, 141 insertions(+), 8 deletions(-) diff --git a/cpu/esp32/Kconfig.esp32s2 b/cpu/esp32/Kconfig.esp32s2 index 6478c56238..275ad3f7f1 100644 --- a/cpu/esp32/Kconfig.esp32s2 +++ b/cpu/esp32/Kconfig.esp32s2 @@ -25,6 +25,7 @@ config CPU_FAM_ESP32S2 select MODULE_PS if MODULE_SHELL select MODULE_PTHREAD if MODULE_CPP select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC + select MODULE_USBDEV_SYNOPSYS_DWC2 if HAS_PERIPH_USBDEV && MODULE_PERIPH_USBDEV imply MODULE_NEWLIB_NANO config CPU_FAM diff --git a/cpu/esp32/Kconfig.esp32s3 b/cpu/esp32/Kconfig.esp32s3 index ddbd1f2408..83d7c47e57 100644 --- a/cpu/esp32/Kconfig.esp32s3 +++ b/cpu/esp32/Kconfig.esp32s3 @@ -31,6 +31,7 @@ config CPU_FAM_ESP32S3 select MODULE_PS if MODULE_SHELL select MODULE_PTHREAD if MODULE_CPP select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC + select MODULE_USBDEV_SYNOPSYS_DWC2 if HAS_PERIPH_USBDEV && MODULE_PERIPH_USBDEV imply MODULE_NEWLIB_NANO config CPU_FAM diff --git a/cpu/esp32/Makefile.dep b/cpu/esp32/Makefile.dep index 9437efa133..5ada3f39ab 100644 --- a/cpu/esp32/Makefile.dep +++ b/cpu/esp32/Makefile.dep @@ -159,6 +159,7 @@ endif ifneq (,$(filter periph_usbdev,$(USEMODULE))) USEMODULE += esp_idf_usb + USEMODULE += usbdev_synopsys_dwc2 USEMODULE += ztimer_msec endif diff --git a/cpu/esp32/include/periph_cpu.h b/cpu/esp32/include/periph_cpu.h index a3d419bbb4..10a5761c5a 100644 --- a/cpu/esp32/include/periph_cpu.h +++ b/cpu/esp32/include/periph_cpu.h @@ -811,7 +811,21 @@ typedef struct { /** * @brief Maximum number of UART interfaces */ -#define UART_NUMOF_MAX (SOC_UART_NUM) +#define UART_NUMOF_MAX (SOC_UART_NUM) +/** @} */ + +/** + * @name USB device configuration + * @{ + * + * ESP32x SoCs integrate depending on the specific ESP32x SoC variant (family) an USB OTG FS controller based on the Synopsys DWC2 IP core. + */ +#include "usbdev_synopsys_dwc2.h" + +/** + * @brief Maximum number of USB OTG FS interfaces + */ +#define USBDEV_NUMOF_MAX (SOC_USB_PERIPH_NUM) /** @} */ #ifdef __cplusplus diff --git a/cpu/esp32/include/periph_cpu_esp32s2.h b/cpu/esp32/include/periph_cpu_esp32s2.h index 3491ed9a71..5f9f6b572e 100644 --- a/cpu/esp32/include/periph_cpu_esp32s2.h +++ b/cpu/esp32/include/periph_cpu_esp32s2.h @@ -212,9 +212,69 @@ extern "C" { * UART_DEV(2) | RxD | - |`UART2_RXD` | optional, can be overridden (no direct I/O) * *
- * */ +/** + * @name USB device configuration + * + * ESP32x SoCs have: + * - a bidirectional control endpoint EP0 IN and EP0 OUT + * - six additional endpoints EP1 .. EP6 that can be configured as IN our OUT + * - a maximum of five IN endpoints concurrently active at any time (including EP0 IN) + * - all OUT endpoints share a single RX FIFO + * - each IN endpoint has a dedicated TX FIFO + * + * To avoid a lot of special case handling, the maximum number of IN an OUT + * endpoints including the control endpoint EP0 is 5. + * + * @{ + */ + +/** + * @brief Enable the USB OTG FS peripheral + * + * At the moment, only FS is supported on ESP32x SoCs. + */ +#define DWC2_USB_OTG_FS_ENABLED 1 + +/** + * @brief Number of USB OTG FS IN endpoints including the control endpoint + */ +#define DWC2_USB_OTG_FS_NUM_EP (5) + +/** + * @brief Number of USB OTG HS OUT endpoints including the control endpoint + */ +#define DWC2_USB_OTG_HS_NUM_EP (5) + +/** + * @brief Size of the FIFO shared by all USB OTG FS OUT endpoints + */ +#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE +#define DWC2_USB_OTG_FS_RX_FIFO_SIZE (128U) +#endif + +/** + * @brief Size of the FIFO shared by all USB OTG HS OUT endpoints + */ +#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE +#define DWC2_USB_OTG_HS_RX_FIFO_SIZE (512U) +#endif + +/** + * @brief Total size of the FIFO + */ +#ifndef DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE +#define DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE (1024U) +#endif + +/** + * @brief Buffers have to be word aligned for DMA + */ +#define USBDEV_CPU_DMA_ALIGNMENT (4) +/** @} */ + + #ifdef __cplusplus } #endif diff --git a/cpu/esp32/include/periph_cpu_esp32s3.h b/cpu/esp32/include/periph_cpu_esp32s3.h index 1f214d5582..90e5c5b5c0 100644 --- a/cpu/esp32/include/periph_cpu_esp32s3.h +++ b/cpu/esp32/include/periph_cpu_esp32s3.h @@ -215,6 +215,66 @@ extern "C" { * */ +/** + * @name USB device configuration + * + * ESP32x SoCs have: + * - a bidirectional control endpoint EP0 IN and EP0 OUT + * - six additional endpoints EP1 .. EP6 that can be configured as IN our OUT + * - a maximum of five IN endpoints concurrently active at any time (including EP0 IN) + * - all OUT endpoints share a single RX FIFO + * - each IN endpoint has a dedicated TX FIFO + * + * To avoid a lot of special case handling, the maximum number of IN an OUT + * endpoints including the control endpoint EP0 is 5. + * + * @{ + */ + +/** + * @brief Enable the USB OTG FS peripheral + * + * At the moment, only FS is supported on ESP32x SoCs. + */ +#define DWC2_USB_OTG_FS_ENABLED 1 + +/** + * @brief Number of USB OTG FS IN endpoints including the control endpoint + */ +#define DWC2_USB_OTG_FS_NUM_EP (5) + +/** + * @brief Number of USB OTG HS OUT endpoints including the control endpoint + */ +#define DWC2_USB_OTG_HS_NUM_EP (5) + +/** + * @brief Size of the FIFO shared by all USB OTG FS OUT endpoints + */ +#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE +#define DWC2_USB_OTG_FS_RX_FIFO_SIZE (128U) +#endif + +/** + * @brief Size of the FIFO shared by all USB OTG HS OUT endpoints + */ +#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE +#define DWC2_USB_OTG_HS_RX_FIFO_SIZE (512U) +#endif + +/** + * @brief Total size of the FIFO + */ +#ifndef DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE +#define DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE (1024U) +#endif + +/** + * @brief Buffers have to be word aligned for DMA + */ +#define USBDEV_CPU_DMA_ALIGNMENT (4) +/** @} */ + #ifdef __cplusplus } #endif diff --git a/cpu/esp32/include/sdkconfig_esp32s2.h b/cpu/esp32/include/sdkconfig_esp32s2.h index 5969ce2e37..d80d3c2c1e 100644 --- a/cpu/esp32/include/sdkconfig_esp32s2.h +++ b/cpu/esp32/include/sdkconfig_esp32s2.h @@ -105,9 +105,7 @@ extern "C" { /** * ESP32-S2 specific PHY configuration */ -#define CONFIG_USB_OTG_SUPPORTED 0 -#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256 -#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1 +#define CONFIG_USB_OTG_SUPPORTED 1 /** * ESP32-S2 specific SPI RAM configuration diff --git a/cpu/esp32/include/sdkconfig_esp32s3.h b/cpu/esp32/include/sdkconfig_esp32s3.h index 0c10f474a9..511061867e 100644 --- a/cpu/esp32/include/sdkconfig_esp32s3.h +++ b/cpu/esp32/include/sdkconfig_esp32s3.h @@ -110,9 +110,7 @@ extern "C" { * ESP32-S3 specific PHY configuration */ #define CONFIG_ESP_PHY_ENABLE_USB 1 -#define CONFIG_USB_OTG_SUPPORTED 0 -#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256 -#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1 +#define CONFIG_USB_OTG_SUPPORTED 1 /** * ESP32-S3 specific SPI RAM configuration