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boards: add support for nucleo-l412kb
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Marius
parent
aae86e860f
commit
9c040ff3bd
5
boards/nucleo-l412kb/Makefile
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5
boards/nucleo-l412kb/Makefile
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MODULE = board
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DIRS = $(RIOTBOARD)/common/nucleo
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include $(RIOTBASE)/Makefile.base
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1
boards/nucleo-l412kb/Makefile.dep
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boards/nucleo-l412kb/Makefile.dep
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include $(RIOTBOARD)/common/nucleo/Makefile.dep
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19
boards/nucleo-l412kb/Makefile.features
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boards/nucleo-l412kb/Makefile.features
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CPU = stm32l4
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CPU_MODEL = stm32l412kb
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Put other features for this board (in alphabetical order)
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# Note that a recent version of OpenOCD with a slightly patched code is required
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# for flashing this board. Refer to the following PR for more info:
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# https://github.com/RIOT-OS/RIOT/pull/12144#issuecomment-527090161
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FEATURES_PROVIDED += riotboot
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# load the common Makefile.features for Nucleo-32 boards
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include $(RIOTBOARD)/common/nucleo32/Makefile.features
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2
boards/nucleo-l412kb/Makefile.include
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boards/nucleo-l412kb/Makefile.include
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# load the common Makefile.include for Nucleo-32 boards
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include $(RIOTBOARD)/common/nucleo32/Makefile.include
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5
boards/nucleo-l412kb/doc.txt
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5
boards/nucleo-l412kb/doc.txt
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/**
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@defgroup boards_nucleo-l412kb STM32 Nucleo-L412KB
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@ingroup boards_common_nucleo32
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@brief Support for the STM32 Nucleo-L412KB
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*/
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185
boards/nucleo-l412kb/include/periph_conf.h
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185
boards/nucleo-l412kb/include/periph_conf.h
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/*
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* Copyright (C) 2019 twostairs
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* 2017 Inria
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* 2017 OTA keys
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-l412kb
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-l412kb board
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*
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* @author Marius <marius@twostairs.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "cfg_i2c1_pb6_pb7.h"
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#include "cfg_timer_tim2.h"
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#include "cfg_rtt_default.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
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#define CLOCK_MSI_LSE_PLL (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2,4,6,8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 80MHz MAX!
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR1_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 15),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF3,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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.type = STM32_USART,
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.clk_src = 0, /* Use APB clock */
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},
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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.type = STM32_USART,
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.clk_src = 0, /* Use APB clock */
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},
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_1_ISR (isr_usart1)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM1,
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.rcc_mask = RCC_APB2ENR_TIM1EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
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.af = GPIO_AF1,
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.bus = APB2
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}
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};
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 20000000Hz */
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7, /* -> 78125Hz */
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5, /* -> 312500Hz */
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3, /* -> 1250000Hz */
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1, /* -> 5000000Hz */
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0 /* -> 10000000Hz */
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},
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{ /* for APB2 @ 40000000Hz */
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7, /* -> 156250Hz */
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6, /* -> 312500Hz */
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4, /* -> 1250000Hz */
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2, /* -> 5000000Hz */
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1 /* -> 10000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_B, 5),
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.miso_pin = GPIO_PIN(PORT_B, 4),
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.sclk_pin = GPIO_PIN(PORT_B, 3),
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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